JPS59168676A - LDMOS device and method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a DMOS) transistor and an integrated circuit using the transistor. More particularly, the apparatus and method of the present invention facilitates the integration of lateral DMOS (LDMOS) used in high voltage applications to conventional bipolar processes. The LDMOS device according to the present invention exhibits a significantly enhanced P-type well with respect to substrate bunch-through voltage, and only minimal degradation in drain-to-source breakdown voltage. Accordingly, LDMOS devices and integrated circuits including devices made according to the methods disclosed herein are particularly suited for high voltage applications such as display drivers, automotive ICs, voltage regulators, and the like.

The number of semiconductor manufacturers attempting to integrate LDMOS transistors into bipolar manufacturing processes is relatively small. The fabricated devices suffer from relatively low bunch-through voltage (VPT) between the deep P-well (which is used as the LDMOS channel) and the substrate. Typically these devices exhibit a VPT on the order of 10-50V. This low bunch-through voltage is primarily due to the fact that the P-type well must be relatively deep to increase the breakdown voltage of the device and minimize any possibility of parasitic SCR effects. Furthermore, the value of Vp, , is generally not controlled because the epi-substrate junction depends on the ratio of substrate to shrimp doping level, which can vary by approximately a factor of 3. Increasing the thickness of the shrimp to increase VPT requires deeper isolation wavenumbers between adjacent devices in integrated circuit implementations, and therefore requires larger die sizes. Conventional LDMOS devices thus have low bunch-through voltage characteristics, thus limiting their application in circuit design. It is clear that this bunch-through problem can be solved by placing a standard buried layer below the LDMOS device and extending the buried layer below the deep P-type well into the N+ drain region. Such structures have already been reported. However, such a buried layer placed completely below the device increases VPT to about 200 V, whereas the layer is about 30 volts below the breakdown voltage of the drain to source of the device.
This results in a concomitant reduction from the normal breakdown voltage of 0V to a level of about 100V. This fact is primarily due to the fact that the expansion of the deflation under the device is limited by the thickness of the shrimp.

Various values for this low drain-to-source breakdown voltage
l-1”rresult concept j (”resurf con
For example, Lu
dxkhutze.

``High Voltage DMOS and PMOS in Analog ICs'', published by A.W.
MO8J can be mentioned. Also, werner, wolf
gangM, and 5checkel, Bruno
1981 IEEE International Solid State Circuits Conference, 1981 IEEE International Solid State Circuits Conference, 1-Gate Underlay Transistors on Buried Layers Used as Collector of NPN Transistors in which Buried Layers are Utilized with High Voltage Ipolar Transistors, pages 40-41.

However, any LDM-O8 device that incorporates a buried layer to increase the chip-through voltage and provide a concomitantly high drain-to-source breakdown voltage that approaches the breakdown voltage of a device that does not utilize such a buried layer, or A method for making such a device has also not been previously disclosed.

Accordingly, it is an object of the present invention to provide improved LDMO3 devices and methods and integrated circuits made therefrom.

Furthermore, it is an object of the present invention to provide an improved LDMO8 device and method, and an integrated circuit manufactured by the method described above, which can be integrated into current bipolar manufacturing processes.

The present invention further significantly increases the bunch-through voltage, -
It is an object of the present invention to provide an improved LDMO8 device and method, and an integrated circuit made thereby, that does not appreciably reduce the drain-to-source breakdown voltage of the blade device.

It is still a further object of the present invention to provide an improved LDMO8 device and method, as well as integrated circuits made therefrom, which allow the application of such devices to the high voltage field.

SUMMARY OF THE INVENTION The foregoing and other objects are achieved in the present invention, which includes a DMO8 device comprising a semiconductor substrate having a major surface free of impurities of a first type, an integrated circuit and method for manufacturing the same. Also provided are integrated circuits made thereon. An overlay layer of a second type of impurity opposite in nature to the first type of impurity is formed on the major surface of the substrate. (from the first type of impurity, DMC)
A first region forming a channel for use in the S device is disposed within the overlay layer. second and third regions are formed having a relatively high concentration of a second type of impurity, the second region being disposed within the first region and forming the source of the DMOS device; a third region is disposed within the overlay layer, laterally spaced from the first region, and DM
Form the drain of the OS device. A gate electrode is interposed between the source and drain over a portion of the first region and the overlay layer. A buried layer having a high concentration of a second type of impurity is interposed between the main entrance surface of the substrate and the overlay layer, and is generally located below and coextensive with the first region. . During its operation, the buried layer:
The bunch-through voltage between the first region and the substrate is increased significantly, and the breakdown voltage between the drain and source is not appreciably reduced.

By optimally selecting the position of the buried layer under the P-type well, it is possible to create an LDMO8 device with a large PT (about 150 V), while reducing the drain-to-source breakdown voltage of the buried layer. Deterioration found in equipment that does not have (
(approximately 300V) deterioration of 2% or less is induced. This unexpected result is due to the fact that, for example, when the drain potential is 200
This can be explained by considering the two-dimensional degradation region associated with the structure of the device when the source and substrate are grounded at v and the gate is at an arbitrary voltage. The embedded layer is P
There is no extension beyond the type well, so the depletion region from the P-type well and the substrate are together. This occurs at approximately V2VPT. This in turn “locks” the spread of depression in the local region at the edge of the P-well.
do. This is because in this local region, no more charge can be removed within the N-type region of the shrimp.

Therefore, depression cannot become a woman unless it spreads further laterally.

The current generated in the free electron fxfeh under an electric field is suppressed by the parasitic JFET thus formed, resulting in pinch-on. Since the normal current in the LDMO8 transistor flows along its surface, this pinch-off has no effect when the device is in the on state. As a result, VPT is greatly enhanced (from about 5 UV without a buried layer to 150 V with an optimal buried layer).
), and the avalanche breakdown characteristics are hardly degraded. Devices made according to the invention broke down above 300 volts. Previously, the shrimp to substrate ratio was the limiting factor for breakdown voltage. Furthermore, yields within 10% of the ideal planar yield have been achieved with the apparatus and method of the present invention.

Description of the preferred embodiment In FIG. 1, a prior art LDMO8IO is shown.

The LDMO8 device 10 is formed on a substrate 12, which in the illustrated embodiment comprises a conventional P-type semiconductor material. Thereafter, an epitaxial layer 14 is grown on the substrate 12 to a predetermined thickness and concentration. For the illustrated P-type substrate 12, the epitaxial layer 14 is given an N-type impurity and concentration σ. Thereafter, an LDMO8 device 16 is formed within the epitaxial layer 14 and, in an integrated circuit embodiment, is It is separated from other devices on the common substrate 12.

In the illustrated embodiment, the isolation region 18 consists of P+ material.

LDMO8 device 16 has a source electrode 20, a drain electrode 22, and a gate electrode 24. The channel of the LDMO8 device 16 is formed in a P-type well 26, which in the illustrated embodiment is obtained by implanting boron. A P+ region 28 is formed within the P-type well 26 to form an ohmic contact to the well.

Also, a source 30 is formed within the P-type well, which in the illustrated embodiment is obtained by implanting the N-type conductor doping. Although P+ region 28 and source 30 are shown as being electrically common, they need not be held at the same potential.

A drain 32 is laterally spaced from the P-type well 26;
It is formed similarly to the above description for source 30. P
Epitaxial layer 1 between type well 26 and drain 32
That portion of the conduit 14 consists of the drift region of the LDMO8 device 16.

The conventional LDMO80MO8 device 10 of FIG. 1 shows a somewhat uncontrolled P-type well 26 that is relatively low relative to the bunch-through voltage (VPT) of the substrate 12. The resulting punch-through voltage is low as the P-type well must be relatively deep to increase the breakdown voltage and minimize the potential for parasitic SCR effects. P type Tsuni/I/2
The non-controllability over the substrate 12 bunch-through voltage of 6 is due to the fact that the epitaxial layer 14 to substrate 12 junction depends on the doping ratio of the substrate 12 to epitaxial layer 14 which can vary by a factor of about 3. Furthermore, the thickness of the epitaxial layer 14 may be arbitrarily large because as the thickness of the epitaxial layer 14 increases, the isolation region 18 must be made deeper, which in turn requires a larger die. You cannot try to increase vPT by doing so.

Another prior art LDMO8 device 10 is shown in FIG. In Figures 2-4, structures that are common to those already described with respect to Figure 1 are numbered the same and the previous description remains unchanged.

The conventional LDMO8 device 40 has an extended buried layer intended to increase the punch-through voltage of the LDMO3 device 16, which would otherwise be low. However, when using the extending buried layer 34, the LDMO3
The breakdown voltage of the drain 32 to the source 3o of the device 6 is significantly reduced. This significant reduction in breakdown voltage is due to the epitaxial layer 14 being limited within ma. The device with the extended buried layer 34 of the package shown in FIG. 2 typically exhibits a reduction in breakdown voltage of approximately 200 V to a level of approximately 1 OOV compared to the device of FIG. show. Therefore, by using the extended buried layer 34, the punch-through voltage increases significantly;
The concomitant degradation of the breakdown voltage from drain 32 to source 3o makes the structure of the device undesirable.

FIG. 3 shows an improved LDMO8 device incorporating an optimized buried layer 36. As shown, an optimized buried layer 36 is located below and generally coextends with the P-well 26.

When positioning the optimized buried layer 36 relative to the P-type well 26, if the shape of the optimized buried layer 36 is made smaller than that of the P-type well 26 by approximately 5 μ. , by subsequent out-diffusion of the optimized buried layer 36.
two structures are effectively aligned. The optimal force situation occurs when the optimized buried layer 36 extends exactly in the same space as the P-well 26, but in reality the optimized buried layer 36 is slightly smaller than the P-well, Although it does not appreciably affect the breakdown between sources 30, it still functions to suppress vPT.

Drain 32 seen in improved LDMO8 device 50
Although a concomitant slight degradation in breakdown voltage from to source 30 and an increase in vPT is not evident from the one-dimensional analysis,
This occurs due to the presence of a two-dimensional depression region (as shown by the dotted line) surrounding the P-type well 26. The structure of the improved LDMO8 device 50 differs from previously described structures in that the structure allows for latching of the depletion region as shown near the corners of the P-well 26, resulting in lower breakdown voltage and punch-through. The difference is that the voltage and voltage are simultaneously optimized. That is, JFET-type pinch-off is found at voltages below the avalanche voltage of the conventional LDMO3 device 40, which is greater than the longitudinal voltage found in the absence of the buried layer. This two-dimensional analysis takes into account the gradient doping that occurs when the optimized buried layer 36 tilts toward the epitaxial layer ↓4. Wider by 3 bits. The key to JFET pinch-off is to merge the depletion region before breakdown of the vertical device of FIG. improved LD
The MO8 device mark indicates a punch-through voltage of approximately 150v;
Also, the avalanche breakdown is not significantly reduced from the breakdown voltage of the conventional LDMO8 device 1o of FIG. 1, which exhibits a punch-through voltage of about 50V. This is comparable to the conventional LDMO8 device of FIG. 2, which exhibits an avalanche of approximately 190V.

4, another embodiment is shown utilizing an optimized buried layer 36 with an optional buried layer 38, an improved LDMO8 device ω. An optional buried layer 38 is disposed below and generally coextends with the drain 32 . Optional buried layer 38 is optimized buried layer 36
is formed similarly. Improved LDMO8 device (a)
utilizes the gap between the optimized buried layer 36 and the optional buried layer to control both vPT and avalanche breakdown.

The advantage of using an optimized buried layer 36 for the improved LDMO3 devices 50 and 60 is to control the breakdown voltage at maximum electric field and thus also the subsurface avalanche. This minimizes the injection of hot electrons into the oxide and also
The improved LDMO8 device 50 of FIGS. 3 and 4 reduces potential reliability problems encountered when the LDMO8 device is put into breakdown for extended periods of time.
and 60 are conveniently made using conventional linear bipolar sequences.

The foregoing description provides an improved LDMO8i arrangement and method, and integrated circuits made thereby, which can be readily incorporated into bipolar manufacturing processes. Furthermore, the principles of the present invention significantly increase the punch-through voltage while not producing any appreciable reduction in the breakdown voltage of the drain to source voltage of the device. Furthermore, the improved LDMO8 device and method, and the integrated circuits produced thereby, readily enable the application of such devices to high voltage applications.

While the principles of the invention have been described above with specific structure,
It is to be clearly understood that this description is given by way of example only and is not intended to limit the scope of the invention.

[Brief explanation of the drawing]

Figure 1 shows a prior art LDMO in which punch-through between the P-well and the substrate is a limiting factor for high voltage applications.
8 is a schematic cross-sectional view of the device, and FIG. 2 shows a conventional technology in which bunch-through between the P-type well and the substrate is suppressed by a buried layer, but the breakdown voltage of the drain to the source is significantly deteriorated. Figure 1 shows a schematic cross-sectional view of an LDMO3 device according to Figure 1, in which the breakdown voltage of the drain to source is significantly increased by using a buried layer extending co-extensive with the EL, as can be seen from the conventional device of Figure 1. FIG. 4 shows an LDMO8 device according to the invention that is not degraded as much as possible, and FIG. 3 shows another configuration of the LDMO8 device of FIG. 3 extending in the same space as the LDMO8 device shown in FIG. 10, 16... LDMO8 device, 12... substrate,
14...Epitaxial layer, 18...Isolation region, 2
0... Source electrode, 22... Drain electrode, 24...
...Gate electrode, 28...P region, 30... Source, 32... Drain, 34... Buried layer, 40...
・・Conventional LDMO8 device, 36 ・・Optimum buried layer,
Seki... Any embedded layer, 50, 60... Improved type L
DMO3 device. /'-16 -16 F'IC,2

Claims (3)

[Claims] (1) a semiconductor substrate of a first impurity type having a main surface, an overlay layer formed within the main surface of the substrate and an overlay of a second impurity type; and a semiconductor substrate of the first impurity type disposed within the overlay layer; , a first region forming a channel for the DMOS device; a second region of the second impurity type disposed within the first region and forming a source for the DMOS device; and a second region forming a source for the DMOS device; a third region disposed within the layer and laterally disposed from the first region and forming a drain for the OMO8 device; a gate electrode disposed on the overlay layer and the overlay layer in the main surface of the substrate, the gate electrode is not of the second impurity type, and is disposed below the first region; a buried layer extending generally co-spaced with the region;
metal fitting, whereby the buried layer greatly increases the bunch-through voltage between the first region and the substrate and causes a decrease in the breakdown voltage between the drain and the source. An integrated circuit comprising a DMOS device. (2) configuring a DMOS device and providing a semiconductor substrate showing a main surface of a first impurity type; forming a buried layer in the main surface of the substrate; coating the main surface of the substrate including the buried layer with the overlay layer of the second impurity type; disposing in the overlay layer a first region overlying and generally coextensive with the buried layer; a second region forming a secondary source of the OMO8 device; forming the drain of the reservoir of the 0MO8 device, and the second region being laterally displaced from the first region.
further arranging the second and third regions of an impurity type in the first region and the overlay layer, respectively; interposing a gate electrode between the source and the drain; covering a portion of a first region with the overlay layer, whereby the buried layer significantly increases the bunch-through voltage between the first region and the substrate; A method of constructing a DMO3 device, characterized in that it does not result in any appreciable reduction in the breakdown voltage between the source and the source. (3) providing a semiconductor substrate comprising a 0MO8 device and providing a major surface of a first impurity type; and a buried layer of a second impurity type occupying a predetermined region of the major surface of the substrate; forming the second layer on the main surface of the substrate including the buried layer;
disposing in the overlay layer a first region of the first impurity type, the first region covering the buried layer and extending generally in the same space as the buried layer; a second region forming a dead source of the DMOS device;
A third region forms the drain of the DMO3 device and connects the second and third regions of the second impurity type, which are laterally displaced from the first region, to the first region and the overlay, respectively. interposing a gate electrode between the source and the drain and covering a portion of the first region and the overlay layer; The DMOS device is made by a process that significantly increases the bunch-through voltage between the first region and the substrate, while not resulting in any obvious reduction in the breakdown voltage between the drain and the source. integrated circuit.