JPS59208870A - Manufacturing method of solid-state image sensor - Google Patents

Abstract

PURPOSE:To enable to reduce the cell size per division by perfectly eliminating the dispersion of the channel length of a transfer gate region due to the shortage in mask alignment accuracy by enabling to form the vertical register part and the photoelectric conversion part in self-alignment. CONSTITUTION:After phosphorus ion implantation with channel stop regions 24 and an Si dioxide film 34 remaining on the transfer gate region 20 as a mask, about 1,600Angstrom Si dioxide films 35 are formed by high temperature oxidizing treatment in an oxidizing atmosphere. Thereafter, the phosphorus ion-implanted in the former process is diffused to the depth of about 2mum by high temperature treatment, thus the N type layer serving as the buried channel of the vertical register 19 and the N type layer of the photoelectric conversion part 22 are formed at the same time. By this process, it follows that the vertical register 19 and the photoelectric conversion part 22 are formed in self-alignment, resulting in no dispersion of the channel length of the transfer gate region 20 due to the shortage in mask alignment accuracy.

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing a solid-state image sensor.

In recent years, with the rapid development of semiconductor and integrated circuit technology, the development of solid-state imaging devices has been strongly promoted. This solid-state image sensor is free from image distortion, afterimages, and burn-in, and is small, lightweight, and consumes low power, so it is being put into practical use as a replacement for image pickup tubes, mainly in home television cameras. However, in order to support high-definition telephony systems that will be put into practical use in the near future,
The number of pixels of about 500 x is still insufficient, and in order to reduce the size of TV camera optical systems and improve the yield of solid-state image sensors, it is necessary to further reduce the chip size from the current % inch system. . In order to achieve this increase in the number of pixels and reduction in chip size, in addition to using a reduction projection exposure device in one photolithography process,
The manufacturing process itself needs to be modified to be suitable for miniaturization.

FIG. 1 is a plan layout diagram for explaining an example of a solid-state image sensor. This solid-state image sensor is called an interline transfer type charge transfer image sensor, and includes a photoelectric conversion section 11 for accumulating signal charges according to the amount of incident light, and a photoelectric conversion section 11 that converts the signal charges accumulated in the photoelectric conversion section 11 in one horizontal line. A transfer gate region 12 for reading data every scanning period (field or frame), a vertical register 13 for vertically transferring the read signal charge for every horizontal scanning period (IH), and one end of each vertical register. It consists of a horizontal register 14 that is electrically coupled to transfer signal charges in the horizontal direction, and an output circuit 15 that sequentially converts the signal charges from the horizontal register 14 into voltage signals.

FIG. 2 is a sectional view taken along line AA' of the image sensor shown in FIG. Here, to simplify the explanation, the present image sensor is assumed to be an N-channel device. A vertical register charge transfer electrode 18 is provided on the main surface of the P-type substrate semiconductor 16 with an insulating layer 17 interposed therebetween. The vertical resistor 19 consists of a buried channel consisting of an N-type layer of conductivity type opposite to that of the substrate semiconductor. Further, a P-type layer 21 having the same conductivity type as the substrate semiconductor is provided on the surface of the transfer gate region 20. Further, the heavy transfer electrode 18 is arranged to cover the vertical register 19 and the transfer gate region 20. 22
2 is a photoelectric conversion section formed by forming a P-N junction with a substrate semiconductor, and the parts other than the photoelectric conversion section 22 are shielded from light by a metal layer path.

Further, reference numeral 24 denotes a channel stop region having a high substrate impurity concentration, which separates each photoelectric conversion section 22 and the vertical register 19.

Next, FIGS. 3 to 6 are diagrams for explaining the conventional process used to manufacture the solid-state image sensor shown in FIGS. 1 and 2, and are A-A in FIG. 'Cross-sectional views are shown for each major process.

First, as shown in FIG. 3, a silicon dioxide film of approximately 1600^ thickness was formed on the main surface of a 130^ P-type silicon substrate 16 by high-temperature oxidation treatment in an oxidizing atmosphere, and then a known photolithography technique was used. Then, the silicon dioxide film in the portion where the vertical register 19 will be formed is removed using a mask 25. Then, a mask 25 is formed. Next, using this mask 25, phosphorus is selectively implanted by ion implantation, and then high-temperature oxidation treatment is performed again in an oxidizing atmosphere to form a silicon dioxide film with a thickness of about 1600^ in the area. Afterwards, by high temperature treatment,
Phosphorus is diffused to a depth of about 2 μ2n to form a hemi-shaped layer that will become a buried channel of the vertical register 19.

Next, the silicon dioxide film 25 used as a mask for phosphorus implantation was removed using a hydrofluoric acid etching solution, and then the entire surface was thermally oxidized again.
A silicon dioxide film of approximately 500^ thickness is formed over the entire main surface. A silicon nitride film 26 of about 1100 λ is then deposited by a known method using silane and ammonia, and only the silicon nitride film on the surface forming the channel t-, y-p regions is removed by a known plasma etching method. Using this silicon nitride film 26 as a mask, boron ions are implanted to form a channel stop region 24. Thereafter, thermal oxidation is performed to form a silicon dioxide film 27 of about 800 OA on the surface of the channel stop region 24 not covered with the silicon nitride film 26 (FIG. 4).

Next, after removing the silicon nitride film 26 with an etching solution such as phosphoric acid, only the silicon dioxide film on the surface of the channel stop region 24 is left, and the rest is removed with a hydrofluoric acid-based etching solution. A silicon dioxide film of about 100 OA is formed. Then, using a known photolithographic technique, the area other than the area where the transfer gate region 20 will be formed is covered with a photoresist 29, and this photoresist 29 is masked and holons are ion-implanted through the silicon dioxide film 28 to form the transfer gate. P-type layer 2 controlling the threshold voltage of region 20
1 (Figure 5).

Next, the photoresist 2 used to form the P-type layer 21
9 is removed, and a polycrystalline silicon film of about 6,000 layers is deposited on the entire surface by thermal decomposition of silane, and then P-type impurities are diffused in order to make this polycrystalline silicon film conductive. Then, the polycrystalline silicon film in portions other than the charge transfer 14N and the pole 18 is removed using known photolithography and plasma etching. Next, using the polycrystalline silicon film that forms the charge transfer electrode 18 as a mask, the portions of the diary silicon film 28 that are not covered with the polycrystalline silicon film are removed using a hydrofluoric acid-based etching solution, and then etched again. Using this polycrystalline silicon film as a mask, phosphorus is selectively implanted to form an N-type layer of the photoelectric conversion section 22 (FIG. 6).

Next, a silicon dioxide film of about 75 OA is formed on the surfaces of the charge transfer electrode 18 and the photoelectric conversion section 22 by thermal oxidation, and then a linker glass film of about 11 μW is grown by vapor phase growth to form the insulating layer 17. Next, a known photo-etching technique is used to form a metal 1 for shielding parts other than the photoelectric conversion section 22 from light!
23 (Fig. 2).

According to such a conventional manufacturing method of a solid-state image sensor, first, an N-type layer is formed which will become the buried channel of the vertical register 19, and then this N-type layer is aligned and the transfer gate region 2 ( 1(7) The P-type layer 21 is formed, and then the N-type layer is layered again to form the N-type layer of the photoelectric conversion section 22. Therefore, the channel length of the transfer gate region 20 is vertical. ip', L/JIS 19 and the optical conversion section 22 depend largely on the accuracy of mask alignment.For example, the master channel length of the transfer gate area 20 is set to 35μ.
772. , mask's total height ±0.5μ777
Then, the finished channel length is 30~40μ
It will vary between mn. This 1 means that the threshold voltage of the transfer gate region 2 () varies from wafer to wafer (in the worst case, the two-dimensional effect causes the charge to pulsate on the open side 1) and does not operate as a transfer gate. This has been well thought out, and has been a significant obstacle to achieving a larger number of pixels and a smaller chip size for solid-state image sensors.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a 1^1 image sensor that eliminates the above-mentioned drawbacks and allows for a larger number of pixels and a smaller chip size.

According to the present invention, several photoelectric conversion parts are arranged in a matrix on a semiconductor substrate of a first conductivity type and are made of a second conductivity type opposite to the substrate, and the photoelectric conversion parts are arranged in a matrix on a semiconductor substrate of a first conductivity type. A shift register group consisting of a plurality of columns of charge transfer devices electrically separated from each other by a channel stop region between them and configured with the buried channels of the second conductivity type, and corresponding to the photoelectric conversion section along the column direction. In manufacturing a solid-state imaging device comprising a transfer gate region provided between the shift registers, the photoelectric conversion section and the shift register section are coated with a silicon nitride film, and then the transfer gate region is coated with a photoresist; forming the channel stop region using the silicon nitride film and the photoresist as a mask, removing the photo 1/cyst, forming a silicon dioxide film using the silicon nitride film as a mask, and removing the silicon nitride film; using the silicon dioxide film as a mask to simultaneously form the second conductivity type in the photo-electrolytic conversion section and the shift register section, and then removing the silicon dioxide film to form the transfer gate region. A method for manufacturing a solid-state image sensor with features can be obtained.

Next, embodiments of the present invention will be described using the drawings.

For ease of explanation, the embodiment of the present invention is an N-channel device.

7 to 11 show the embodiment of the present invention 1i511.
This figure is for clarity, and since the plan layout of the solid-state imaging device manufactured according to the present invention is the same as that in FIG. 1, the sectional view taken along the line AA' in FIG. 1 is shown to illustrate the main process.

Components that are the same as those in FIGS. 2 to 6 are designated by the same numbers.

First, as shown in FIG. 7, a silicon dioxide film 30 of about 160 OA was formed on the main surface of a 13 Ω P-type silicon substrate 16 by oxidation treatment at high temperature in an oxidizing atmosphere, and then silane and ammonia were added. A silicon nitride film 31 is deposited using known methods. Next, a photoresist 32 is coated on this silicon nitride film 31, and the silicon nitride film 31 in the portion where the channel stop region 24 and the transfer game HA region 20 are to be formed is removed using known photolithography and plasma etching. . Here, only the portion where the transfer gate region 20 will be formed is covered with a photoresist 33 using photolithography again, and using the photoresist 32 and the north as a mask, boron ions are implanted through the silicon dioxide film 30 to increase the substrate impurity concentration. A high channel stop region 24 is formed.

Next, after removing the photoresists 32 and 33 used as masks for forming the channel stop region 24, thermal oxidation is performed using the silicon nitride film 31 as a mask to form the area above the channel stop region 24 and the transfer gate region 20. A silicon dioxide film 34 of approximately 800 OA is formed (FIG. 8).

Next, after removing the silicon nitride film 31 with an etching solution such as phosphoric acid, only the silicon dioxide film 34 on the channel block area U and the transfer gate region 20 is left, and the rest is removed with a hydrofluoric acid-based etching solution. do. Next, using the silicon dioxide film 34 remaining on the channel stop region 24 and the transfer gate region 20 as a mask, phosphorus ions are implanted, and then high temperature oxidation treatment is performed in an oxidizing atmosphere to reduce the
A silicon dioxide film 35 of 0.00 mm is formed. After that, by high temperature treatment, the phosphorus ion-implanted in the previous step is diffused to a depth of approximately 2 μm, and an N-type layer that will become the buried channel of the vertical resistor 19 and an N-type layer of the photoelectric conversion section 22 are simultaneously formed. do. Through this process, the vertical register 19 and the photoelectric conversion section 22 are formed by a so-called self-line, and the channel length of the transfer gate region 20 is shortened due to the lack of mask alignment accuracy, which was a problem in the conventional manufacturing method. There will be no sticking (Figure 9).

Next, the area other than the transfer gate region 20 is covered with a photoresist 36 using photolithography, and the silicon dioxide film 34 on the transfer gate region 20 is removed using the photoresist 36 as a mask. Next, poron ions are implanted to form a P-type layer 21 that controls the threshold voltage of the transfer gate region 20 (FIG. 10).

Next, after removing the photoresist 36 used to form the transfer gate region 20, the silicon dioxide film 35 is removed using a hydrofluoric acid-based etching solution, and then thermal oxidation is performed to remove the silicon dioxide film 35.
A silicon dioxide film 37 of 00OA is formed. A polycrystalline silicon film of about 6000 nm is then deposited over the entire surface of the wafer by a known silane pyrolysis method, and then P-type impurities are diffused into the polycrystalline silicon film to make it conductive. Then, the polycrystalline silicon film in areas other than the charge transfer electrode 18 is removed using known photolithography and plasma etching. Next, after forming a silicon dioxide film of about 75 OA by thermal oxidation, a link glass film of about 1.1 μm was grown by vapor phase growth, and the silicon dioxide film 34.3
Together with 7, an insulating layer 17 is formed. Next, using a known photolithographic technique, parts other than the photoelectric conversion section 22 are covered with a metal layer 23 for shielding light (FIG. 11).

As is clear from the description of the embodiments above, according to the present invention, the vertical register section and photoelectric conversion section of a solid-state image sensor can be formed in a so-called self-line, so that mask lines, which have been a problem with conventional manufacturing methods, can be formed. There is no variation in the channel length of the transfer gate region due to insufficient metal alignment precision. Therefore, the cell size per pixel of the solid-state image sensor including the photoelectric conversion section, transfer gate region, and vertical register section can be reduced, and as a result, it is possible to increase the number of pixels and reduce the chip size. Thick.

[Brief explanation of the drawing]

Fig. 1 is a plan layout diagram of an example of an interline transfer type solid-state image sensor, and Fig. 2 is an A-
A cross-sectional view taken along line A', FIGS. 3 to 6 are cross-sectional views shown in the order of steps for explaining an example of a conventional manufacturing method, and FIGS. 7 to 11 are cross-sectional views for explaining the manufacturing method of the present invention. for,
It is sectional drawing shown in order of a process. DESCRIPTION OF SYMBOLS 11, 22... Photoelectric conversion part, 12, 20-- Transfer gate region, 13, 19... Vertical register, 14-
...Horizontal 1/transistor, 15...Output circuit, 16...Substrate semiconductor, 17...Insulating layer, 18...Passage transfer electrode, 23...Metal layer, 24...Channel stop region,
25, 27, 28, 30, 34, 35, 3
7...Second-level silicon film, 26, 31...Silicon nitride film, 29, 32, 33. 36...Photoresist. One Axis 11 Representative Patent Attorney Susumu Uchihara 1. )-1' 1st article 2nd article 2u 3rd figure 5s 1st/g 3

Claims (1)

[Claims] A plurality of photoelectric conversion parts made of a second conductivity type opposite to the substrate, arranged in an IJ wax pattern on a semiconductor substrate of a first conductivity type, and a channel stop region l between the photoelectric conversion parts. Therefore, the second
A solid-state imaging device comprising a shift register group consisting of a plurality of rows of charge transfer devices configured with buried channels of conductivity type, and a transfer gate region provided between the photoelectric conversion section and the corresponding shift register along the column direction. In manufacturing the device, after the photoelectric conversion section and the shift register section are covered with a silicon nitride film, the transfer gate region is covered with a photoresist 1-, and the channel stop region is formed using the silicon nitride film and the photoresist as a mask. forming a silicon dioxide film using the silicon nitride film as a mask after removing the photoresist, and forming a silicon dioxide film on the photoelectric conversion section and the shift register section using the silicon dioxide film as a mask after removing the silicon nitride film. A method of manufacturing a solid-state imaging device, characterized in that the second conductivity type is formed at the same time, and then the silicon dioxide film is removed to form the transfer gate region.