JPS5936266B2 - How to store kanji dot patterns in memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dot pattern memory storage method for improving the access speed of dot patterns of Chinese characters.

There are approximately 6000 types of kanji in C6226 established by JIS.
The code system is expressed in 2 bytes per character, the 1st byte is the ward, the 2nd byte is the dot, the ku is the 94th ward from the 1st ward, and the dot is the 94th point from the 1st point. and the codes are 21 to 7E (010, 00
01) to (111, 1110).

When outputting kanji as dot characters to a kanji printer, kanji display device, etc. using the dot matrix method, the address converted from the 2-byte code of the kanji is transferred from the storage device in which the dot pattern is stored (hereinafter referred to as memory). When accessed, it is taken out and passed to the print drive unit.

One factor in this character generation speed is the time required to calculate the address of the corresponding kanji in the dot pattern memory from the kanji code. In the conventional dot pattern memory, dot patterns are stored in the order of the Kanji code as a method for relatively easy conversion from the Kanji code to an address. In this case, the formula for calculating the start address in the dot pattern memory of the kanji code C1C2 (code for two wards of C1, code for two points of C2) is (C1 x 94 + C2 - n) x B.
・・・・・・・・・(Ha)

However, n is a constant, and B is the number of bytes that make up the dot pattern for one character (in the case of a 32 x 32 dot pattern, B = 128
, or B=36 for a 16×18 dot pattern). When calculating formula (1), multiplying B by the number in the box means that B is a power of 2 or 1 of a number that is a power of 2.
, or the sum of two terms (expressed as 128=27, 36=25+22, which has little effect on the character generation speed. However,
Regarding the multiplication of C1 and 94, if 94 is expressed as the sum of terms of powers of 2, then 94=26+24+23+22+
21, which is the sum of five terms, so if it is realized by software, the number of shift operations will be large and the character generation speed will be slow. Furthermore, if it is implemented using hardware, the number of elements will increase, making it difficult to make the character generating section smaller and lower in price. SUMMARY OF THE INVENTION Therefore, the present invention aims to improve the above-mentioned drawbacks of the prior art, and its purpose is to provide a method for storing Kanji dot patterns in memory, which speeds up the conversion of Kanji patterns into addresses in pattern memory from Kanji codes. Yes, the feature is that the kanji code is ku (C1) and dot (C2).
In a memory storage method for kanji dot patterns, in which a predetermined number of words for each kanji dot pattern are sequentially stored in memory, an empty area is created after the last point of each ward in the memory, and the empty area is The number A of points in each ward including the area is greater than the number A5 of points excluding vacant areas! , and when A and A5 are expressed as the sum of terms that are powers of 2, the number of vacant areas is determined such that the number of terms in A is smaller than the number of terms in A'. It's in the way patterns are stored in memory.

Preferably, when A'=94, the number of free areas is 2, and A-94+2=96. Figure 1 is the kanji code table used in the present invention, with the 95th and 96th points added to make one ward 96.
This is a dot.

FIG. 2 also shows a pattern memory map (B=36).
When dot patterns are stored in memory based on this code table, the formula for calculating the start address in the dot pattern memory of the kanji code ClC2 is \VllllVν
V4-1'o.

However, n' is a constant and B is the same as in equation (1). Here, for the multiplication of C1 and 96, 96::26+25
Therefore, the number of comparative shift calculations in equation (1) is reduced, and when experimented with software, the calculation time is approximately 2/
It can be shortened to 3. In FIGS. 1 and 2, points 95 and 96 (shaded areas in the figures) are empty spaces, and the existence of these empty spaces is one of the features of the present invention.

Figure 3 is a block configuration diagram when the calculations in the brackets of equation (1) are realized in hardware using the conventional kanji code table, and Figure 4 shows the block diagram of the block diagram using the kanji code table with 95 points and 96 points added. FIG. 2 is a block diagram showing the structure of a block when the calculations in the box (2) are realized by hardware.

In FIGS. 3 and 4, 1 indicates a 2-byte code of the input Chinese character, 2 indicates a shift register, 3 indicates an adder, and 4 indicates a subtracter. The part surrounded by the dotted line is C1×94+C2,
Or perform the calculation C1×96+C2. Compared to the conventional method, the method of the present invention requires fewer shift registers and has a smaller circuit configuration, and is expected to be smaller and lower in price.

Additionally, if the function shown in Figure 4 is implemented using software, the multiplication speed will be faster and the character generation speed will be improved.
It can be applied as a kanji dot pattern memory for medium-high speed printers and display devices. As explained above, the method of storing JISC6226 kanji dot patterns in memory according to the present invention enables faster conversion from codes to memory addresses than conventional methods, and can be used in a variety of smooth character output devices and display devices. It becomes possible to apply

Also, implementation using hardware has the advantage of reducing the number of elements, making it more compact and lower in price.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing kanji codes applied to the method of storing kanji dot patterns in memory according to the present invention, FIG. 2 is a diagram illustrating a pattern memory map according to the present invention, and FIG. A circuit that calculates
FIG. 4 is a circuit for calculating addresses of a pattern memory according to the present invention. 1; Kanji 2-byte code, 2; Shift register, 3;
Adder, 4; subtractor.

Claims (1)

[Claims] 1. A method for storing kanji dot patterns in memory, in which a kanji code is represented by two bytes consisting of a ward (C_1) and a dot (C_2), and the dot pattern of each kanji is sequentially stored in a memory in units of a predetermined number of words. , an empty area is created in the memory after the last point of each area, and the number A of points in each area including the empty area is a value close to A' that is larger than the number A' of points not including the empty area, and , A and A' as 2
A method for storing Kanji dot patterns in a memory, characterized in that the number of free areas is determined such that the number of terms of A is smaller than the number of terms of A' when expressed as the sum of terms of powers of . 2 A'=94 (=2^6+2^4+2^3+2^2+
2^1) and A=96 (=2^6+2^5).