JPS593949A - Master slice integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a master slice integrated circuit, and particularly to a high 1L integrated circuit.
The present invention relates to a gate array LSIr in which the threshold voltage of an input signal can be adjusted by selecting a combination of diodes for input buffer darts of sI.

(2) Background of the technology Generally speaking, in a Gustaslice LSI (Large Scale Integrated Circuit) that integrates a large number of basic f-) circuits such as TTL or ECL, the signals of each f-) circuit are connected to, for example, a ground line,
It may be input to other f-) circuits via power supply lines, input/output ports, ins, etc., or by coupling due to capacitance, and may adversely affect the operation of other dirt circuits. Therefore, it is necessary to reduce the crosstalk between the dirt circuits and the like as much as possible, and to prevent each circuit from being affected by noise.

(3) Conventional technology and problems Conventionally, gate array LSIs are equipped with multiple dirt circuits.
In order to reduce crosstalk between each dirt circuit, etc., the equipment has been carefully arranged for each gate circuit and input/output bin terminals, etc., and to reduce the impedance of each power line, ground line, etc. Efforts were made to make it thicker. However, recently, devices such as star slice f-) array LSI devices have been developed in which a large number of dirt circuits, such as 500 gates, are mounted on one semiconductor chip.

Since LSI devices have extremely high integration and high speed, crosstalk between each circuit is likely to occur, and because of the high speed, they are easily affected by noise. For example, input pin terminals are susceptible to noise from the power supply system. There was an inconvenience that it would malfunction if picked up. In particular, when the signals of many output pin terminals change simultaneously, the noise is quite large, and this noise is superimposed on the power supply line and ground line and is induced into the input pin terminal, reducing the operating margin of the input circuit. This had the disadvantage of having a negative impact.

(4) Purpose of the Invention The purpose of the present invention is to:
#) f-) Array LSI with a simple structure based on the concept of using a device that can adjust the threshold of an input signal for a specific input/four gate in a highly integrated and high speed gate array LSI device. The objective is to improve the noise margin of the device.

(5) Structure of the invention and its object is that, according to the invention, an array of basic cells with a plurality of circuit elements and a plurality of input and output buffer cells are provided, and only the wiring layer is changed according to the desired function. The present invention provides a master slice integrated circuit characterized in that a plurality of level shift elements for manually changing the threshold value of the buffer cell are formed in a pre-placed buffer cell. This is achieved by

(6) Examples of the Invention The present invention will be explained in detail below with reference to the drawings. For example, a master slice Good array LSI has a bulk in which a large number of basic cells are arranged in an array, and the wiring layers that connect within and between these basic cells are automatically designed using a computer or the like. This is a semi-custom IC that can be used to configure a wide variety of products in bulk.

FIG. 1(a) shows the configuration on an r-) array LSI'il chip, and FIG. 1(b) shows an enlarged view of a corner portion thereof. Such a gate array LSI is an internal cell]
an internal cell area 2 that constitutes a logic circuit and an inter-cell automatic wiring area (channel area) 2-1 for mutually automatic wiring between the array 1-1 and internal cells 1; ■I10 cell area 4 consisting of I10 cells 3 for 10 (input/output) and 7F, provided on the outside for the purpose of electrical interface between internal cell 1 and the outside of the IC chip; V formed around the chip. C power supply and ground wiring 6-1 and internal cell area 2 are connected to a linear ground line (power supply) 6-2, which extends vertically in the figure, and a linear ground line, which extends horizontally. It consists of a power wiring 6 consisting of a vcc power line 6-3, a power supply line f, a draw 4, and a signal line i4 connected to the cell 3. In addition, in FIG. 1(,), the power supply wiring @ 60 peripheral part 6-1, the ground line 6-2, and the V. . The illustration of the power supply line 6-3 is omitted for clarity of the drawing.

In general, a gate array consists of a first wiring layer that mainly forms wiring in the X direction, a second wiring layer that mainly forms wiring in the Y direction, and internal cells and cells that are connected by a peer hole, etc. that connects them. Connects between circuit elements. The internal cell area is provided in the center of the chip, and internal cell area 2 and z
An external cell region 4 is provided between the f. Further, the power supply wiring 6-1 is provided by the second wiring layer on the external cell region 4, and the thin power supply wiring 6-2, 6-3 from there to the internal cell region are respectively provided in the second wiring layer. It is formed in the first wiring layer. Therefore, the I10 cell region 4 is mainly limited by the shape of the surrounding power supply wiring 6-1.

The internal cell, I10 cell, is an assembly of circuit elements such as transistors, diodes, and resistive capacitors, and by connecting these circuit elements within the cell, a basic logic circuit can be constructed.

FIG. 2 shows a gate array LS according to an embodiment of the present invention.
An example of an input buffer used in an I device is shown. The input buffer dart shown in the figure is provided in the above-mentioned I10 cell, and the input terminal IN is connected to the input pin terminal of the nine-dimensional array LSI device, and the output terminal OU
T is configured in the internal cell, for example, Frizzo Flo'f
Alternatively, it is connected to an internal circuit such as a latch circuit. The input buffer in Figure 2 is a PNP type input transistor Q1, an NPN with a Schottky barrier diode)
It includes transistors Q2 and Q3, Schottky barrier diodes D1 and D2, a level shift element LS composed of, for example, a diode, and resistors R1 to R4.

9 in FIG. 2, when a daytime level signal is applied to the input terminal IN, the transistor Q1 is cut off, and a pace current flows from the power supply vc0 to the transistor Q2 via the resistor R1 and the level shift element LS. current, and transistor Q2 becomes conductive. Therefore, the transistor Q3 also becomes conductive and the voltage at the output terminal OUT becomes low level. Conversely, when a low level signal is input to the input terminal IN, the transistor Q1 becomes conductive and the emitter voltage of the transistor Q1 decreases, so that the transistor Q2
and Q3 are both non-conductive, and the constant voltage at the output terminal OUT becomes a high level. Incidentally, the YI7 and Maria diodes D1 and D2 are for clamping unnecessary noise components in the pace of the input signal IN and the output/nostar Q2.

By the way, when a normal diode is used as the level shift element LS in the input buffer shown in FIG. 2, the threshold value of the input signal at the input terminal IN is determined by the forward pressure of the diode and the transistor Q1. Assuming that the base-emitter voltages are approximately equal to 21, it becomes equal to the sum of the base-emitter voltages of transistors Q2 and Q3, which is 1.4 V. In the present invention, in addition to a normal diode, for example, a series circuit of a Schottky barrier diode and a resistor, a series circuit of a Schottky barrier diode, a Schottky barrier diode, and a conventional diode can be used as the level shift element. Preparing the circuit etc.?
r, s are formed on the chip, and by selecting and connecting all of the specified ones, the first one of the input signals is
The shift can be set up on the first shift of the loincloth.

However, instead of providing such threshold voltage variable means for all input buffers in the dirt array LSI device, in the present invention, the input terminal IN is connected directly to the external device via the input pin terminal of the LSI device. Connected to the circuit, and the output terminal OUT is the clock input terminal or reset of the internal circuit element.

The threshold a voltage variable means is provided only in the input puffer dart connected to the output signal input terminal or the control signal input terminal connected thereto. For example, as shown in FIG. 3, when the clock signal CLK is supplied to the clock terminal CK of the flip-flop 7 via the AND/DART 1, the clock signal CLK is supplied to the buffer r-) provided with a threshold voltage variable means. Supply through the circuit. As a result, the noise margin of the clock signal, which is the basis of the operation of the internal circuit, is increased, and the dirt array LSI device can operate accurately. In FIG. 3, the signal DT supplied to the other input terminal of the AND dart 8 is a data signal for opening and closing the AND gate.

FIG. 4 shows the structure of one diode for one level shift element. FIG. 4(,) is a plan view showing the structure of a diode formed on an LSI substrate, and FIG.
b) is a sectional view taken along line A-A in FIG. 4(a).

In these figures, 10 is, for example, a P-type substrate, 11 is an N-type epitaxial layer, and 12 is a P-type iso-diffusion layer. A P-type base diffusion layer 13, an N-type emitter diffusion Wt 14 formed on the P-type diffusion layer 13, and an N-type layer 15 are formed on the epitaxial layer 11. The diode as a level shift element is composed of a P-type base diffusion layer 13 and an N-type emitter diffusion layer 14, and a full-layer wiring 16 formed of aluminum or the like is provided in the h-, space diffusion layer 13, and emitter diffusion layer 14, respectively. is connected. Note that the N-type diffusion layer 15 for collector contact is short-circuited to the pace diffusion layer 13 by the metal wiring layer 16. Further, 17 is an insulating film, and 18 is a buried layer.

FIG. 5 shows the configuration of a level shift element used in an input buffer r-) in a goot array LSI device according to an embodiment of the present invention. The circuit shown in FIG. 5(a) is a series circuit of an ordinary diode and a Schottky barrier diode, and the circuit shown in FIG. 5(b) is a series circuit of a Schottky barrier diode and a resistor. Each of these level shift elements is formed in place of the level shift element LS in FIG. The threshold voltage can be changed by selecting the method of connecting the wiring layers. Alternatively, the threshold voltage can be controlled by forming each of these level shift elements and the diode element shown in FIG. 4 in parallel on the substrate, and selecting one of them by connecting them with a metal wiring layer. You can also do that.

Figures 5(c) and 5(d) are respectively shown in Figure 5(a).
) and C- in FIG. 5(b).
It is a sectional view seen from above the C line.

The level shift element shown in FIGS. 5(a) and 5(c) is a diode element having the same structure as that shown in FIG. A Schottky barrier diode is provided.

The level shift element shown in FIGS. 5(b) and 5(d) has a metal electrode 1 bonded on an epitaxial layer 11.
In addition to the Schottky barrier diode formed by 9, a resistor is formed by elongating the paste diffusion layer 13'.

(7) Effects of the Invention As described above, according to the present invention, the threshold voltage level for the input signal of the input buffer dart can be arbitrarily selected with an extremely simple structure, so that the input buffer is not easily affected by noise. It becomes possible to improve the noise margin by adjusting the threshold voltage of the terminal, and the reliability of the dirt array LSI device can be improved.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are plan views showing the structure of a dirt array LSI device according to an embodiment of the present invention;
・Figure 2 is a circuit diagram showing details of the input buffer gate used in the gate array LSI device in Figure 1. Figure 3 is the input circuit and internal circuit in the gate array LSI device in Figure 1. 4 and 5 are plan views showing an example of a level shift element used in an input buffer of a gate array LSI device according to an embodiment of the present invention. and a cross-sectional view. 1...Internal cell, ■-1...Array of internal cell 1,
2... Internal cell area, 2-1... Inter-cell automatic wiring area, 3... Input/output cell, 4... Input/output cell area, 5
...Pad, 6...Power wiring, 6-1...Ground wiring, 6-2...Brand line, '6-3...
Power line, 6-4...power pad, 7...flip-flop, 8...and? -1-110... Substrate, 11... Epitaxial layer, 12...
Isolation diffusion layer, 13... Base diffusion layer, 1
4... Emitter diffusion layer, 15... Collector diffusion layer,
16...Metal wiring layer, 17...Insulation layer, 18...
- Buried layer, 19...metal electrode. Patent applicant Fujitsu Ltd. Patent attorney Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Patent attorney Akiyuki Yamaguchi 5-4 5
5 Figure 3

Claims (1)

[Claims] 1. A master slice integrated circuit comprising an array of basic cells each having a plurality of circuit elements and a plurality of input and output buffer cells, in which only the wiring layer is changed according to a desired function. . A master slice integrated circuit, wherein a plurality of level shift elements for changing an input threshold value of the buffer cell are formed in the input buffer cell. 2. The dirt array LSI device according to claim 1, wherein the level shift element is a diode or a resistor.