JPS5943534A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5943534A JPS5943534A JP57154401A JP15440182A JPS5943534A JP S5943534 A JPS5943534 A JP S5943534A JP 57154401 A JP57154401 A JP 57154401A JP 15440182 A JP15440182 A JP 15440182A JP S5943534 A JPS5943534 A JP S5943534A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- fixed
- fin
- solder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32014—Structure relative to the bonding area, e.g. bond pad the layer connector being smaller than the bonding area, e.g. bond pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3205—Shape
- H01L2224/32057—Shape in side view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/83385—Shape, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
Description
この発明は製造コストの低減と信頼性向上をはかった半
導体装置１ｉの製造方法に関するものである。
従来、この七ｒ］の装置は、キャンタイプまたは樹脂封
止タイプのタイオード６ケを、個々に冷却フィンに融点
が約２４０°Ｃ程度の半田を用いて半田付は後、結線し
て、例えば自動車の三相ブリッジを形成していた。以下
さらに従来例を図面について説明する。
第１図は従来の三相タイオートノ゛リンジに用いられる
タイオー１′の冷却フィンへの取イ；Ｉ状態を示すもの
で、６ケのタイオード（し１示せ」゛）がそハぞ才１外
部リード１に固着さ第１、モールド樹脂２で樹脂成形さ
れた後、第２図に示イよ５ＶＣまず基板３に取り伺げら
ｔ］、その後半１■ろ５利４を用いThe present invention relates to a method of manufacturing a semiconductor device 1i that reduces manufacturing costs and improves reliability. Conventionally, this device has six can-type or resin-sealed diodes that are individually soldered to the cooling fins using solder with a melting point of about 240°C, and then connected, for example. It formed a three-phase bridge for automobiles. A conventional example will be further explained below with reference to the drawings. Figure 1 shows the installation of the diodes 1' to the cooling fins used in a conventional three-phase tie auto ring. The first one is fixed to the lead 1, and after being molded with mold resin 2, as shown in Figure 2, the 5VC is first placed on the board 3, and then the second half is used.
【冷却フィン５に取
り付けられている。
このよ５な従来の三相タイオードブリッジの組立方法は
、第２薗に示すタイオードを作る工程と、第１図に示ゴ
ー半田ろう旧４を介して、冷却フィン５ｖｃ半１−Ｔ】
付けする工程に分が第１ていた。
従って工数の増大により製造コストの削減が困ｌ１１１
６であるばかりでなく、半トロろう材４をま低融点の半
田を用いる必便があり、実動作時においての耐温度性や
熱ヒロワ性能が劣っていた。
さらには第２図に示すタイオードの形状からろても明ら
かなように、壬−ルド崩脂２と基板３は接着強度が弱く
、そのため耐引張性能等が不十分で、第１図の組立てを
自動的に行うに当り、細心の注意が必要であった。
この発明は、上記の点にかんがみなされたもので、補助
フィンを用い冷却フィンにしかにタイオードチップを半
田付は−するか、または補助フィンを介してタイオード
チップを冷却フィンに半田付けし、この半１１］を半ｌ
」融点３００℃以上の高温半Ｅ１３ろう材４・用い、−
挙に同時に半田付けするようにしたもので５製造工数の
削減と、製造コストの大幅な低減とができるほか、機構
の簡素化による重量軽減もできる半導体装置の製造方法
を提供するものである。以下この発明について説明する
。
第３図はこの発明の一実施例によりイＵられた半導体装
１４の部分断面図である。これらの図で、６は補助フィ
ンで、この補助フィン６に半導体チップ、例えばタイオ
ードチップＩを高融点半田ろう材８ａを介し【熱圧着に
より固定し、次にタイオードチップＩ上に高融点半田ろ
うＩ８ｂを介して外部リード１を熱圧着により固定し、
さらに補助フィン６を冷却フィン５に高融点゛￥〔（コ
ろ５利８ｃを介して熱圧着しでより固定し、その後、熱
処理炉に通して各、ｖ７＋融点半Ｈ１〕〕う拐８８〜８
ｃを同時に融着した後、モールド樹脂２によって樹脂成
形する。ここで用いられ１こ補助フ・イン６の詳細を第
５図に示す。
第４図はこの発明の他の実施例を示す半導体装置の部分
断面図でこの実施例は、第６図に示す補助フィン６ケ冷
却フイン５に固着（２１こ本のである。
第７図はこの発明を用いた三相ブリッジの２枚組の一方
の冷却フイ：１５とタイオードの取付状態を丞す正面図
である。
次に、この発明の製造工程につい゛Ｃ説明する。
（１） 補助フィン６を自動組立装置産ρ・−デツプ
する。
（２）高融点＝＋÷田ろう材８ａを補助フ・イン６に熱
圧着により固定する。
■ タイオードチップＩを高融点半田ろうｔ１８ａの上
に熱圧着する。
■ 晶融志士［■ろう利８ｂをタイオー トチツブＴ上
に熱圧着する。
■ 外部！Ｉ −１’ １を高融点半Ｅｔｌろう月８ｂ
上に熱圧着する。
■ サプラインに冷却フィン５をローデングする。
■ 高融点半田ろう利８ｃ′ｔ／冷却フィン５上に熱圧
着する。
■ 補助フィン６を高融点半田ろう月８ｃ上に位置決め
固定する。
■ 不活性雰囲気炉に通し高融点半田ろう材８ａ〜８Ｃ
を融着させる。
０ デスペンサーによりエポキシ樹脂２を注入する。
（１１）熱処理炉妬通しエポキシ樹脂２を硬化させる。
以上により、三相タイオー ドブリッジの一方の極性の
組立てが完了する。
同様にタイオードチップの極性の異ったもう一方の冷却
フィンを上記ラインに投入し、２ケをペアに組み合わせ
ると第１図に相当する三相タイオードブリッジが形成さ
れる。
なお、上記実施例においては、高融志士［■１ろ５月８
ａ〜８ｃｏ′）熱圧着による組立方法について示したが
、他に半田ペーストを用いる方法や、治具を川（ゴニ積
上げ方式でも同様に組立てできることは言うまでもない
。ま六−５上記実施例では自動車搭載用の三相プリクジ
に適用するものとして説明しム：が、こｔＩＷ限らず冷
却フィン５に直付けする他の個別半導体素子や、マルチ
チップ装置にも同様に適用できることは欄５までもない
。
以上説、明し１こよ５に、この発明は補助フィンを用い
るとともに、半導体デツプの固着と冷却フィンへの固着
を同時に行うよ５ＶｃＬｖ−のひ、補助フィンは’Ｉ’
に：、１ｆｉｌ）保時に発熱するｉイオー ドの放熱効
率の改善だけでフｘ ＜、崖導体ザソブを機械的外力力
ｒ）保ｄ侍することも主目的と１ろＬ二めに使用さ第１
るモールド樹脂の接７合力が、補助フィンを用いフｌい
場合に比較（−２て格段して向上するとともに、引はが
し力がかかった場合、従来構造であると、もろに半導体
チップに引張力がかかっていムニが、補則フィンの採用
により引張力の負担は、補助フィンと冷却フィン間の高
融点十口１ろ５Ｈにかかるようになる１こめ半導体千ツ
ブの（ｉ’ｅ壇が防げ、装置全体の機械的強度および信
テη性がバＬ、＜向−トする。また、半口〕ろ５月の融
点の上列により製品の動作時の信頼性向上と、長内命化
がｉｉ１能となり、また、補助フィンの効果で冷却効果
が向上し、ｆｕｌｌえげ同一電流定格においＣは、接合
部温度Ｔｊ を下げることができ、また、同一接合ｔ
・：ｌ（ｉ、１．λ度Ｔｊで使用時は直流定格を上げる
ことができるので、それによるコストタウン効果ま−（
，１よ品質、信頼性面での改善効果が著ｔ〜い半導体装
置がｆ！量られる利点がある。[It is attached to the cooling fin 5.] The assembly method of this conventional three-phase diode bridge consists of the process of making the diode shown in the second section, and the process of making the diode shown in FIG.
The attaching process took a few minutes. Therefore, it is difficult to reduce manufacturing costs due to the increase in man-hours111
In addition, it is necessary to use solder with a low melting point for the semi-solid solder material 4, and the temperature resistance and thermal filler performance during actual operation are inferior. Furthermore, as is clear from the shape of the diode shown in Fig. 2, the adhesive strength between the diode 2 and the substrate 3 is weak, and therefore the tensile resistance is insufficient, and the assembly shown in Fig. 1 is difficult. Great care was required when performing this automatically. This invention was made in view of the above points, and it is possible to solder the diode chip to the cooling fin only by using an auxiliary fin, or to solder the diode chip to the cooling fin through the auxiliary fin. , this half 11] is half l
” High-temperature semi-E13 brazing filler metal 4 with a melting point of 300°C or higher, used, -
The present invention provides a method for manufacturing a semiconductor device, in which the number of manufacturing steps can be reduced and the manufacturing cost can be significantly reduced by simultaneously performing soldering, and the weight can also be reduced by simplifying the mechanism. This invention will be explained below. FIG. 3 is a partial sectional view of a semiconductor device 14 manufactured according to an embodiment of the present invention. In these figures, reference numeral 6 denotes an auxiliary fin, to which a semiconductor chip, for example, a diode chip I, is fixed by thermocompression bonding via a high melting point solder filler metal 8a, and then a high melting point is applied onto the diode chip I. The external lead 1 is fixed by thermocompression bonding via solder solder I8b,
Furthermore, the auxiliary fins 6 are fixed to the cooling fins 5 by thermocompression bonding through the rollers 5 and 8c, and then passed through a heat treatment furnace to a temperature of V7 + melting point half H1]. 8
After fusing c at the same time, resin molding is performed using mold resin 2. The details of the single auxiliary fan 6 used here are shown in FIG. FIG. 4 is a partial sectional view of a semiconductor device showing another embodiment of the present invention. In this embodiment, six auxiliary fins are fixed to the cooling fins 5 shown in FIG. 6 (21 pieces). It is a front view showing the mounting state of one cooling pipe 15 and a diode of a two-piece set of three-phase bridge using this invention.Next, the manufacturing process of this invention will be explained. (1) Auxiliary The fin 6 is assembled using an automatic assembly machine. (2) The high melting point = + ÷ solder filler metal 8a is fixed to the auxiliary fin 6 by thermocompression bonding. ■ The diode chip I is bonded to the high melting point solder filler metal t18a. ■ Heat and press the wax 8b onto the top of the T. ■ External!
Heat and press on top. ■ Load the cooling fins 5 into the supply line. ■ High melting point solder solder 8 c't/thermo-compression bonded onto the cooling fins 5. ■ Position and fix the auxiliary fin 6 on the high melting point solder solder 8c. ■ High melting point solder filler metal 8a to 8C passed through an inert atmosphere furnace.
fuse. 0 Inject epoxy resin 2 using a dispenser. (11) Harden the epoxy resin 2 through a heat treatment furnace. This completes the assembly of one polarity of the three-phase diode bridge. Similarly, by inserting the other cooling fin of the diode chip with a different polarity into the above line and combining the two into a pair, a three-phase diode bridge corresponding to FIG. 1 is formed. In addition, in the above example,
a~8co') Although the assembly method using thermocompression bonding has been shown, it goes without saying that assembly can also be performed in the same way by using other methods such as using solder paste or by stacking jigs. This is explained as being applied to a three-phase pre-circuit for mounting; however, it does not go beyond column 5 to say that it can be similarly applied not only to IW but also to other individual semiconductor elements directly attached to the cooling fins 5 and multi-chip devices. In the above explanation, first and fifth, the present invention uses auxiliary fins and fixes the semiconductor depth and the cooling fins at the same time.
The main purpose is to protect the cliff conductor from mechanical external force (r), and the second use is to 1st
The resultant bonding force of the mold resin is significantly improved (-2) when using auxiliary fins (-2), and when peeling force is applied, the conventional structure will cause tensile force on the semiconductor chip. Due to the use of auxiliary fins, the burden of tensile force will be applied to the high melting point between the auxiliary fins and the cooling fins. , the mechanical strength and reliability of the entire device will be balanced.In addition, the higher melting point of the half-mouth filter will improve reliability during product operation and extend lifespan. In addition, the cooling effect is improved by the effect of the auxiliary fins, and the junction temperature Tj can be lowered at the same full current rating.
・:l(i, 1. When used at λ degree Tj, the DC rating can be increased, so the cost reduction effect is
, 1. Semiconductor devices with remarkable improvement effects in terms of quality and reliability are f! It has the advantage of being measured.
第１図は従来のモールド形三相タイオードブリッジのが
）親図、第２図は従来のモールド形タイオードの’Ａ（
ｅ４斜を兄１ン１、第３図、第４図はこの発明の実施例
により得られ１こｆ導体装置ｄの部分断面図、第５図、
第６図は第３図、第４図に用いらすｔ定補助フィンの斜
視図、第７図はこの発明を用いた三相グリッジの２枚組
の一力のター（−Ａ−ドの取付状態を示す正面図である
。
図中、１は外部リード、２はゴボギシ樹脂、６（′：ｌ
補助フィン、γはタイオードチーツブ、８ａ〜８ｃは高
Ｉ独点半田ろう材である。ｉＪ ｔ、、ｉ、図中の同−
符弓は同一まｒｃは相当部分を示１゜
代理人 葛 ！ｌＩｆ 信 −（外１名）第 １
図
第２図
？
第３図
第４図
手ｑゾ、：補正書 （自発）
１．事件の表示 持ＩＱ（Ｉ昭５７−１５４４０
１号２、発明の名（４、半導体装置の製造方法３、補正
を−４ると
代表者片山１−八部
４、代理人
５３補正の対象
明細−１の発明の詳細な説明の欄および図面の簡単な説
明の欄
６、補ｉＪＥの内容
（１） 明細書第２頁２行の［自動車のＪを、１゛自
動車用の」と補正する。
（２）同じく第５頁１３．１５行の「エポキシ樹脂２」
を、「モールド樹脂２」と補止する。
（３）同じく第８頁３行の「エポキシ樹脂２」を、「モ
ールＩ・樹脂２」と補１１′する。
以 １−Figure 1 is a parent diagram of a conventional molded three-phase diode bridge, and Figure 2 is a diagram of a conventional molded diode bridge.
3 and 4 are partial cross-sectional views of a conductor device d obtained by an embodiment of the present invention, and FIG.
Fig. 6 is a perspective view of the t-constant auxiliary fin used in Figs. It is a front view showing the installation state. In the figure, 1 is an external lead, 2 is a gobogishi resin, and 6 (':l
Auxiliary fins, γ are diode chips, and 8a to 8c are high I unique solder fillers. iJ t,, i, the same in the figure.
The archery is the same, or the rc shows a considerable part of the 1° agent! lIf Shin - (1 other person) 1st
Figure 2? Figure 3 Figure 4 Hand qzo: Amendment (spontaneous) 1. Incident display: IQ
1 No. 2, Title of the invention (4, Method for manufacturing a semiconductor device 3, Amendment -4, Representative Katayama 1-Yabe 4, Agent 53 Detailed description of the invention of the subject matter of the amendment -1) and Column 6 of brief explanation of drawings, contents of supplement iJE (1) In the second page, line 2 of the specification, [J for automobile is corrected to 1゛for automobile.'' (2) Similarly, page 5, 13.15 "Epoxy resin 2" in the row
is supplemented with "mold resin 2". (3) Similarly, ``Epoxy resin 2'' on page 8, line 3 is supplemented with ``Mall I Resin 2''(11'). Below 1-
Claims (1)
定し、半導体チップを前記補助フィンに高融点半Ｂ」ろ
う利を介して、または前記冷却フィンにじかに高融点半
田ろ５利を介して熱圧着により固定し、さらに前記半導
体チップに外部リードを高融点半田ろう利を介して熱圧
着により固定した後、前記それぞれの高融点半田ろう材
を同時に融着固定する工程と、前記外部リードおよび補
助フィンの一部分を露出せしめた状態で樹脂封止する工
程とから１９【ることを特徴とする半導体装置の製造方
法。[Claims] An auxiliary fin is fixed to the cooling fin through a high melting point solder solder, and a semiconductor chip is fixed to the auxiliary fin through a high melting point solder or directly to the cooling fin. A step of fixing the external leads to the semiconductor chip by thermocompression bonding via a filter, and then fixing the external leads to the semiconductor chip by thermocompression bonding via a high melting point solder solder, and then simultaneously fusing and fixing each of the high melting point solder fillers. 19. A method of manufacturing a semiconductor device, comprising the steps of: (19) sealing the external leads and auxiliary fins with a resin in a state in which a portion is exposed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154401A JPS5943534A (en) | 1982-09-02 | 1982-09-02 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57154401A JPS5943534A (en) | 1982-09-02 | 1982-09-02 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5943534A true JPS5943534A (en) | 1984-03-10 |
Family
ID=15583335
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57154401A Pending JPS5943534A (en) | 1982-09-02 | 1982-09-02 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5943534A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5068712A (en) * | 1988-09-20 | 1991-11-26 | Hitachi, Ltd. | Semiconductor device |
| JPH07252548A (en) * | 1994-03-11 | 1995-10-03 | Sumitomo Metal Mining Co Ltd | Method for recovering valuable metals from waste catalyst |
| US5863817A (en) * | 1988-09-20 | 1999-01-26 | Hitachi, Ltd. | Semiconductor device |
| US6242797B1 (en) * | 1997-05-19 | 2001-06-05 | Nec Corporation | Semiconductor device having pellet mounted on radiating plate thereof |
-
1982
- 1982-09-02 JP JP57154401A patent/JPS5943534A/en active Pending
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6072231A (en) * | 1988-03-20 | 2000-06-06 | Hitachi, Ltd. | Semiconductor device |
| US6130114A (en) * | 1988-03-20 | 2000-10-10 | Hitachi, Ltd. | Semiconductor device |
| US6081023A (en) * | 1988-03-20 | 2000-06-27 | Hitachi, Ltd. | Semiconductor device |
| US6100115A (en) * | 1988-09-20 | 2000-08-08 | Hitachi, Ltd. | Semiconductor device |
| US6124629A (en) * | 1988-09-20 | 2000-09-26 | Hitachi, Ltd. | Semiconductor device including a resin sealing member which exposes the rear surface of the sealed semiconductor chip |
| US5981315A (en) * | 1988-09-20 | 1999-11-09 | Hitachi, Ltd. | Semiconductor device |
| US6018191A (en) * | 1988-09-20 | 2000-01-25 | Hitachi, Ltd. | Semiconductor device |
| US6069029A (en) * | 1988-09-20 | 2000-05-30 | Hitachi, Ltd. | Semiconductor device chip on lead and lead on chip manufacturing |
| US5863817A (en) * | 1988-09-20 | 1999-01-26 | Hitachi, Ltd. | Semiconductor device |
| US6919622B2 (en) | 1988-09-20 | 2005-07-19 | Renesas Technology Corp. | Semiconductor device |
| US5068712A (en) * | 1988-09-20 | 1991-11-26 | Hitachi, Ltd. | Semiconductor device |
| US6100580A (en) * | 1988-09-20 | 2000-08-08 | Hitachi, Ltd. | Semiconductor device having all outer leads extending from one side of a resin member |
| US5914530A (en) * | 1988-09-20 | 1999-06-22 | Hitachi, Ltd. | Semiconductor device |
| US5358904A (en) * | 1988-09-20 | 1994-10-25 | Hitachi, Ltd. | Semiconductor device |
| US6720208B2 (en) | 1988-09-20 | 2004-04-13 | Renesas Technology Corporation | Semiconductor device |
| US6303982B2 (en) | 1988-09-20 | 2001-10-16 | Hitachi, Ltd. | Semiconductor device |
| US6326681B1 (en) | 1988-09-20 | 2001-12-04 | Hitachi, Ltd | Semiconductor device |
| US6531760B1 (en) | 1988-09-20 | 2003-03-11 | Gen Murakami | Semiconductor device |
| JPH07252548A (en) * | 1994-03-11 | 1995-10-03 | Sumitomo Metal Mining Co Ltd | Method for recovering valuable metals from waste catalyst |
| US6242797B1 (en) * | 1997-05-19 | 2001-06-05 | Nec Corporation | Semiconductor device having pellet mounted on radiating plate thereof |
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