JPS5943546A - Semiconductor ic device and its manufacture - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The division between the elements of the four-invention integrated circuit device (hereinafter referred to simply as IC)? Regarding fl technology, /
The present invention relates to a technique for isolating elements using a first groove formed in a semiconductor substrate.

As one of the isolation techniques between elements for the purpose of increasing the integration density of integrated circuit devices, narrow grooves are formed in a semicircular substrate, and insulating H such as polycrystalline silicon or StQ is injected into each groove. Methods of embedding aisle thinner areas and gaps are well known.

R11 groove-embedding isolation technology is used (in integrated circuit devices, in particular to concentrate wiring paths,
．． q Kyushuma, please minimize the parasitic damage that occurs between the wiring path extending into the semiconductor substrate and the semiconductor substrate located below in a certain area on the body. First, it may be necessary to extend the wiring route portion over a wide viewing/isolation area due to the misalignment. For example, if you want to clearly separate the element formation area and wiring path formation area on the semiconductor substrate for a large-scale Hayabusa fIN circuit device (LSI), it is necessary to create a parasitic container with the semiconductor substrate. In order to make the wiring path small, the width σ) is wide compared to the depth of the groove in the one stone part where the wiring path is concentrated. In the part where ηj gas separation between the elements can be achieved, the isolation region of the thin groove with a narrow width compared to the depth of the groove is formed into the shape fj'2 L. However, it is necessary to form an isolation region that is wider than the depth of the groove. When using separation technology to form wide grooves, the polycrystalline silicon or insulating material buried there will form a thick depression compared to that buried in the narrow grooves. Due to the fact that the isolation region 51' is planarized, the riverboat Vc has five drawbacks.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a falsification circuit device having a wide isolation region and a narrow isolation region, and its first rule.

According to the present invention, an isolation region is formed which is wider than its depth. Polycrystalline silicon I or absolute Hj to fill the groove by
31' planarization of the surface of l simplifies Ji, 2>. Warehouse invention a) - Examples! τ-e is bipolar type 1 (?V
1. The formation of a wide (isolation/-) John region is carried out by VU using f11 to form a trench for collector/contact separation which is required when forming a bipolar transistor. , “Beware.

Hereinafter, an embodiment in which the present invention is applied to a bipolar ICK using a bipolar transistor as a circuit element will be described.

Figure 1 is a structural diagram to which the present invention is applied to a bipolar transistor. In this figure, the polarity of the bipolar transistor is shown.
5 and wiring ports for commercial connections between elements, as shown in the diagram (Ig. 1), but it goes without saying that such poles and wiring will eventually be formed. FIG. 1 shows the cross-sectional structure of the substrate 71 (81 before pole and arrangement formation). On the upper surface of the Si substrate 7, there are isolating regions between elements. Toso Sai 1
An element forming area 9 is also provided surrounded by the area.

Isolation area 8 fills the groove S 10210
It is formed by i, and its depth is the depth that penetrates the N+ buried layer 11. These iso-17 regions 8 have a width of 1 to 15 μm for a depth of 25 to 4 μm.
As in n, there are depth vZ, ratio (-te + tr, j narrow (・81) and wide (・82) compared to the depth. iv, the central portion 82a of the wide Ai-7 region 82 is formed into a shallow trench with the same depth as the collector/contact isolation 12 in the element formation region 9, 1.=for example, 17zlli row depth. There is.

The soil F in the wide isolation area 82 is made of aluminum or the like, and a road rockwork (whether shown or not) is provided therein.

Wide isolation area 820 partial pressure, shallow bottom (
・To form the portion 82a and the portion 82b, as shown in FIG. mask pattern 14 and fire sharing skill 1
It's fine, it's a different kind of new), [it requires 2 masks], r°C.

After patterning the 840.S++, N4 film 16 on the upper surface of the Si substrate 7 by photoresist processing using both masks, patterning was performed to form a 1.7 SiQ, l
lq 15 od and / ma Y, J'j S iqN, membrane 1
By etching the Sl layer in two stages using 6 as a mask, a predetermined groove as shown in FIG. 3(A) can be obtained.

For etching of the PJ seal and Sl, reactive ion etching with a small side etch is used.

As shown in Figure 3(B), 5 lots of film 17 were formed on the 70th surface of the Si substrate.
A P1 layer 18 is provided as a Bouyannel stopper 7 by the material injection method, and is further used as a mask (
・After removing the S I M N4 film 16, the 81 substrate 7
5i0219'&deposited on the entire ten faces. This S+021
9 is meant to fill in all the gaps left in the previous edition, but
Search for grooves in the isolation area and the groove width is narrow (・
・From 2, Sin,] 9 Jlj・Hayashi I is for t′1゛II′Green SaiII′ of the collector contact separation part,
In other words, 1-2 μ! It's enough to make a sound. That...
・(I, in short, there is a resist at IC5 (・geS Q C
(Spin Men Glass) Apply 20 more and 1
child? , many, Surface Ding Jf by Svantha Eso Ching
(become)! vinegar.

Thereafter, as shown in FIG.
A Sl s N4 film 21 is formed. Then, the P7 base region z3 and the N+x to emitter region 24 are each formed by the first well-known implantation technique.

Although the figure does not show ℃, it is not possible to use old materials such as aluminum for the main region of the transistor.
・Don't install the wiring. The wide isolation area 820 is used as an oil path for wiring.

Like 1 so 10, in this example, Baibo-7
In an IC, in the isolation region j12 between garbage children, the width is wide (゛ is also σ) compared to the depth such that wiring paths are provided on 1,000 σ), and the bottom is shallow (. and depth (- part), and the depth of the shallow part (-) is the same as the collector/contact separation part in the resistor formation region. Wide, to isolation region Vr-, 1,000 grooves, fill in β'J edge +1 cliff 10 surface, thickness 1.c <result, -toga 1
, "<, Easily convert the surface to K17jil / 3r" 4 5 Excellent II! ) has 1. Moreover, this invention KJ: If the groove should be deepened, the insulation material σ) should be made deeper.
) 14 to 15 ``
II m K? l L, I p mPi! degree C),
(It should be possible to make it easier to manufacture from a negative point of view.)

Children's +! In the case of JK5, the insulating material of SiQ was formed in the groove part, but the polycrystalline material was pressed into the groove part. You can also use silicone wood.
Figure (A) (forming (
After that, silicon oxide anus (S iO,F
) 17 岑・Form Dyshi, this silicon acid II? ~Up(
A VC polycrystalline silicon film is then formed to fill the trench.

Furthermore, the present invention is not limited to element isolation of bipolar ICs ([11]), but MO8I() which uses a hL gate 70 field effect transistor (OSF) as a circuit element. : 5) It can also be applied as a separation technique. In this case, the present invention adopts a method of forming a 111 groove and burying an insulating material or polycrystalline silicon, thereby replacing the conventional 1.0 (" (+S) method. In comparison, the area occupied by the isolation area can be significantly reduced.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view showing an example of one length Ml'i of this FJ)J, Fig. 2 is a view showing a mask pattern used in device manufacturing, and Figs. 7. Si substrate, 8... Isolation region, 81
...Isolation area with a narrow width of 1-'C in depth, 82...Isolation area with a width of 11 cm in depth, 82; I...Shallow part of me, f(2b・
Searching for the bottom, part 9, 10...
5iot (insulating phase Fl), 12... Collector/contact separation part. Agent Ben-Konshi Bo [] Li Hee / J 1st
Figure ♂ [

Claims (1)

[Scope of Claims] 1. In a semi-isolated circuit device in which an insulating material or polycrystalline silicon source Jf41 is formed in a groove formed in a semiconductor substrate to serve as an isolation region between elements, these elements The isolation area between the two grooves is defined by the above-mentioned ``1 groove part having a wider width (- part) than the depth, and a narrower width (- part) than the wide (- part, and the said wide part 2. Maeichi: Semiconductor I] body'5 Circuit device f7. It has an Ibora transistor, and has a wide front Width (the shallow groove in the isolation region is ml of the collector contact of the bipolar transistor).
The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed at the same time as a groove portion for use.