JPS5957530A - Phase locked loop - Google Patents

Abstract

PURPOSE:To reduce remarkably a pull-in time to a normal phase, by selecting a timing signal closest to the normal phase and attaining the phase locking based on the result. CONSTITUTION:A clock forming circuit 7 forming an N-phase clock almost equal to an input signal in period and shifted in phase, a clock switching device 8 selecting a clock of a some phase from an output of the circuit 7, and a phase comparator circuit 9 comparing in phase between the clock selected at the switching device 8 and the input signal, are provided. When the phase lag or lead is discriminated from the result of comparison of the circuit 9, a corresponding ''0'' or ''1'' signal is given to the switching device 8 and a changing point detector 10. The switching device 8 receives these signals and switches the phase of clock from the circuit 7. When the changing point is detected at the detector 10, the switching of the phase is stopped and a clock having the phase closest to the normal phase is given to the phase comparator 2 via an AND gate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a phase-locked circuit, and more particularly to a phase-locked circuit for creating a timing signal phase-synchronized with an input data signal in a short time.

[Prior art]

Generally, in digital communication devices and magnetic storage devices, a phase-locked loop (DPLL) is used for the purpose of extracting a specific signal included in noise or other signals.
Phase Lock Loop) is widely used. This phase synchronization circuit has an oscillator 9 phase comparator, etc. as its main components, and detects, for example, the phase difference between an input signal and a timing signal, and based on this detection result, adjusts the timing signal to the input signal. It is configured to be synchronized with.

However, this type of phase synchronization circuit has the disadvantage that, since the amount of phase correction is small at the beginning of phase synchronization, it takes a long time to bring the phase into normal phase.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase synchronization circuit that eliminates the drawbacks of the prior art described above and can significantly shorten the time required to obtain a normal phase at the initial stage of phase synchronization.

[Summary of the invention]

To achieve this objective, the present invention selects and uses a plurality of N-phase timing signals having substantially the same period as the timing frequency of the input data signal and each having a different phase. First, select the timing signal that is closest to the normal phase first, and once it is selected.

A normal phase synchronization operation is performed using the timing signal of that phase as a reference, thereby significantly shortening the time required to obtain the normal phase.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. The figure is a circuit diagram showing a phase locked circuit according to an embodiment of the present invention.

In this figure, a data signal is input to terminal 1, and this data signal is applied to phase comparators 2 and 9. A clock that is the output of an AND gate 11, which will be described later, is input to the phase comparator 2, where the data signal and the clock are phase-compared. Then, a signal of 1'' or II OII is logically outputted to the up-down counter 3 in accordance with the delay or advance of the phase.
1 Counts up or down every time a n or It OII level signal is input, and outputs the count value.
? - When a flow or underflow is detected, a signal to that effect is output to the variable frequency divider circuit 5.

The variable frequency divider circuit 5 is manually supplied with a clock signal having a predetermined frequency, for example, approximately equal to M×LXN times the timing frequency of the human-powered data signal, from the oscillator 4, and when the detection signal is input, this clock signal is M−α, M
, M+α.

The fixed frequency divider/frequency circuit 6 divides the output signal of the variable frequency divider 5 into embryos, and outputs a clock signal approximately equal to N times the normal frequency to the N-phase lock generation circuit 7. This N-phase lock generation circuit 7 generates clock signals whose periods are approximately equal to the normal period and whose phases are shifted by 2πA, respectively, using the N-times clock signal.

The clock switch 8 selects a certain phase clock from among the N-phase clock signals created by the N-phase lock creation circuit 7. The output of this clock switch 8 is the phase comparator 9.
and is given to AND gate 11.

The phase comparator 9 compares the phase of the data signal that can be input from the input terminal 1 with a certain phase clock selected by the clock switch 8. As a result of this comparison, if a phase lag or lead is determined, the corresponding logical ``On'' or ``''
A signal of 1" is output and given to the clock switch 8 and the change point detector 10. Here, the clock switch 8
The phase of the clock from the N-phase lock generation circuit 7 is switched according to the logic "1" or "0" from the phase comparator 9. In other words, when the phase is "0", the phase is switched to the previous phase, When the phase is III, the phase is switched to the next phase, and this clock output is used for the phase comparison. At this time, there is always a point in time when there is a logical change from 0'' to I (111 and from 1'' to 0''). When this point is detected by the change point detector 10, the phase switching is stopped and at the same time -11. As a result, the AND gate 11 is opened and the clock of the predetermined phase is supplied to the regular phase comparator 2. Note that this clock is the clock of the previously selected phase. , the clock is close to the normal phase.

In this way, after the change point detector 10 detects the change point,
The phase synchronization is fixed to the clock of that phase, and the phase comparator 2 compares the clock of this phase with the input data signal. Phase synchronization is achieved by changing the frequency division ratio of the variable frequency divider circuit 50 by the output of the up-down/counter 3. As a result, the frequency division ratio is finally M+L+N-α.

Phase synchronization is achieved by shifting the phase of the comparison clock by changing it as M+L+N, M+L+N+α. Note that since α<(M+L+N), the amount of phase correction is usually small.

〔Effect of the invention〕

As explained above, according to the present invention, N
The timing signal closest to the normal phase is selected from among the timing signals, and phase synchronization is performed using this as a reference, so it takes less time to reach the normal phase during phase synchronization than with phase-locked circuits in the prior art. The time can be significantly reduced.

[Brief explanation of the drawing]

The attached figure is a circuit diagram showing a phase locked circuit according to an embodiment of the present invention. 2.9... Phase comparator, 3... Atsuzo down counter, 4... Oscillator, 5... Variable frequency divider circuit, 6...
Fixed frequency divider circuit, 7...N-phase lock creation circuit, 8...
Clock switching device, 10... changing point detector. Agent Patent Attorney Masami Akimoto

Claims (1)

[Claims] In a phase synchronization circuit that compares the phase of an input signal and a predetermined timing signal and synchronizes the timing signal with the input signal based on the result, a A clock generating means for generating a phase clock, a switching means for selecting a certain phase clock from the output of the clock generating means, and a phase comparison means for comparing the phase of the clock selected by the switching means with an input signal. The switching means is operated by the output of the phase comparison means to select a clock having a phase close to the normal phase, and thereafter a phase synchronization operation is performed using a timing signal of a predetermined phase as a reference. Phase synchronized circuit.