JPS5961917A - composite electronic components - Google Patents
composite electronic componentsInfo
- Publication number
- JPS5961917A JPS5961917A JP57173415A JP17341582A JPS5961917A JP S5961917 A JPS5961917 A JP S5961917A JP 57173415 A JP57173415 A JP 57173415A JP 17341582 A JP17341582 A JP 17341582A JP S5961917 A JPS5961917 A JP S5961917A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric constant
- composite electronic
- conductor
- attached
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
産業上の利用分野
本発明は積層コンデンサに゛１勺ｑ体千ノブを取イτ１
げだ超重＋１；！ｊの複合電子部品に関する。[Detailed Description of the Invention] Industrial Field of Application The present invention applies to multilayer capacitors.
Geda super heavy +1;! Regarding composite electronic components of J.
従来例の構成とその問題点
一般に積層コンデンサに半導体千ノブを組合せだ複合′
重子部品は公知であるがこの種のものはいずれも第１図
に示すように構成されている。Conventional configurations and their problems Generally, multilayer capacitors are combined with semiconductors.
Although weight components are well known, all of these types are constructed as shown in FIG.
第１図において、１は誘電率の１１・ｈいたとえばチタ
ン酸バリウム等の層であり、２Ｆｉす、に対向するよう
に」二層層１間に配置さｈ／こ積層コンデ°ノザを構成
する内部電極である。そして、３は層１と内部電極２と
で構成される積層コンデンサの外表向に形成されたＡ電
率の低いたとえばガラス等の層であり、この層３０表面
に各電極パターン４．６及び金げ層５を形成し、金屈層
５の表面に゛１′導体チノゾ７を装着するようにしてい
る。In Fig. 1, 1 is a layer made of barium titanate, for example, with a dielectric constant of 11 h, and is placed between two layers 1 so as to face 2Fi, which constitutes a laminated capacitor. This is an internal electrode. Reference numeral 3 denotes a layer made of glass or the like having a low A conductivity formed on the outer surface of the multilayer capacitor composed of the layer 1 and the internal electrodes 2. On the surface of this layer 30, each electrode pattern 4. A thin layer 5 is formed, and a ``1'' conductor chinozo 7 is attached to the surface of the metal layer 5.
尚８ｉｒｉ半導体デツプ７を各電極パターン４，６に接
続するソイヤーボンテイノグ、９は枠、１０は枠９内に
充填されたボノテイノグ用樹脂である。Note that 9 is a frame for connecting the 8iri semiconductor dip 7 to each electrode pattern 4 and 6, and 10 is a bonding resin filled in the frame 9.
第１図に示す従来の複合電子部品でも低誘電率の層３が
積層コンデンサの全表面に形成されており、この層３の
表面に各電極パターン４．６が形成されているだめ各電
極パターン４，６と積層コンデンサを構成する内部電極
２との間の浮遊容）１１゛を非常に小さくすることがで
き、この点でニー優れたものであるということができる
。しかし在から、低誘電率の層３が積層コンデンサの全
表面に形成されこの層３０表面に金肋層５を介して゛１
′導体−Ｔ−ノブ７が装着されている／こめ ｔ 導体
デツプ７の電極と（−記各電極パターン４，６の間に大
きな段；ｌｌ′が生じ、その分だけツイヤ−ボンティジ
グ用のワイヤー８として長いものを用いなければならず
、１″１．：Ｈｉ周波的に悪影響を１〕えると共にワイ
ヤーポンチインクそのものの信頼性も低下するという問
題があった。寸だ、低誘電率の層３が゛１４導体チップ
７を装着する部分に丑で形成されているだめ、１′３１
′１（体チップ７を含めた全体の高さが高くなり、そ第
１だけボッティジグ用樹脂を多く必要とし全体と１−て
薄型化か困備（になるという問題かぁ−）だ。In the conventional composite electronic component shown in FIG. 1, a low dielectric constant layer 3 is formed on the entire surface of the multilayer capacitor, and each electrode pattern 4.6 is formed on the surface of this layer 3. The floating capacitance (11) between 4 and 6 and the internal electrode 2 constituting the multilayer capacitor can be made extremely small, and in this respect it can be said to be excellent. However, from now on, a layer 3 with a low dielectric constant is formed on the entire surface of the multilayer capacitor, and a gold rib layer 5 is interposed on the surface of this layer 30.
'The conductor-T-knob 7 is attached/conductor t A large step is created between the electrodes of the conductor depth 7 and the electrode patterns 4 and 6, and the wire for the Tear-Bonti jig is formed by that amount. 8 had to be used, which had an adverse effect on the 1" 1.:Hi frequency and also reduced the reliability of the wire punch ink itself. 3 is made of ox in the part where the 14 conductor chip 7 is attached, so 1'31
1 (The overall height including the body tip 7 is high, and firstly, it requires a lot of resin for the botti jig, which makes it difficult to make it thinner as a whole.)
発明の目的
木兄［す１は以にのような従来の欠点を除去するもので
あり、１゛＾゛ｊ中な構成で、ワイヤボンティジグ用ワ
イヤーの長さを短かくでき、しかも全体として７ｉ、Ｉ
ＩＩξり化できる優れた複合電子部品をｌｉｊ供するも
のである。OBJECT OF THE INVENTION The present invention is intended to eliminate the following drawbacks of the conventional wire bonding jig. 7i, I
This provides an excellent composite electronic component that can be made into a multi-layered electronic component.
発明の構成
本発明は積層コンデンサの表面の半導体チップを装着す
る部分を除く部分に低誘電率の層を形成し、この層の１
７に各電極パターンを形成すると共に上記低誘電率の層
の形成されていない部分に゛Ｉ′導体デツプを装着する
ように構成したものである。Structure of the Invention The present invention forms a low dielectric constant layer on the surface of a multilayer capacitor except for the part where a semiconductor chip is mounted, and one layer of this layer is
Each electrode pattern is formed on the substrate 7, and an ``I'' conductor depth is attached to the portion where the low dielectric constant layer is not formed.
実施例の説明
第２図、第３図は本発明の複合電子部品の−′火施例を
示ずものであり、図中第１図と同一１テ１υを伺したも
のは第１図と同一のものを示している。DESCRIPTION OF EMBODIMENTS Figures 2 and 3 do not show examples of the composite electronic component of the present invention. It shows the same thing.
第２図、第３図において、第１図と異なる点に１、誘電
率の小さいたとえばガラス等の層３が゛１′導体千ノブ
７を装着する部分に形成されてち・らず、１４）０体−
１−ツブ７は積層コンデンサを構成する誘電率の大きい
たとえばヂタシ酸バリウム等の層１の表向に直接形成さ
れた金屈層５−にに装着さ）−しているということであ
る。In FIGS. 2 and 3, the difference from FIG. 1 is that 1, a layer 3 of a material such as glass having a low dielectric constant is formed in the part where the 14 conductor knob 7 is attached; )0 bodies-
The tube 7 is attached to the metal layer 5 formed directly on the surface of the layer 1 of a layer 1 having a high dielectric constant, such as barium ditase, constituting the multilayer capacitor.
したがって、上記実施例によれば゛ｊ″導体チップ７の
電極と各電極パターン４，６との間に牛じる段差が第１
図に示す従来のものに比し、誘電率の小さい層３の厚さ
分（通常０１ ｍｍ〜０．１５７７７ｊ７１稈度）だけ
小さくなり、ソイヤボシデイシグのだめのツイヤ−８も
それだけ短かくすることができるという利点をイ〕する
。すなわち、ソイヤボンテイノグのだめのツイヤ−８が
短かくなるととにより高周波的な性能が従来のものに比
して著しく向１−すると共にツイヤ−ポジティングその
ものの信頼性も向Ｊ二し、実用」二きわめてイ１刊であ
る。−まだ、−に記実施例によれば′″１イ導体チソグ
７を含む全体の高さを従来に比し誘電率の小さい層３の
厚さ分だけ１氏ぐすることができ、それだけボノテイノ
グ＋４１樹脂層１０を’Ａ！７１ ＜ Ｌ、全体を薄Ｉ
Ｗ化することができるという利点を有する。Therefore, according to the above embodiment, the first level difference between the electrode of the "j" conductor chip 7 and each electrode pattern 4, 6 is
Compared to the conventional one shown in the figure, it is smaller by the thickness of the layer 3 with a small dielectric constant (usually 01 mm to 0.15777j71 culm degree), and the diameter of the Soyaboshi Daisig no Twier 8 is also made shorter. It has the advantage of being able to In other words, by shortening the Twier 8 of the Soya Bonte Nog, the high frequency performance is significantly improved compared to the conventional one, and the reliability of the Twir Positioning itself is also improved, making it practical. ” This is by far the first edition. - Still, according to the embodiment described in -, the overall height including the conductor 7 can be increased by 1 by the thickness of the layer 3 having a lower dielectric constant than the conventional one, and the height of the conductor 7 can be increased by 1 by the thickness of the layer 3 having a small dielectric constant. +41 resin layer 10 'A!71 < L, the whole is thin I
It has the advantage that it can be made into W.
尚、実施例の」：うに金屈層５を積層コンデンサを構成
する誘電率の大きい層１０表面に直接形成ずノ′１ば、
この層５と積層コンデンサを構成する内部型４ｉ１２と
の間で比較的大きな静電容＠Ｃ１が発生ずるが」−記内
部電ＷＬ２の内上記金属層５に最も近い内部止枠２をア
ース電極として用いることに」：す、上記静電容吐Ｃ１
を上記金属層５に装着さノ１だ’ｌ’ ｊｉｂ休チ体プ
７の高周波バイ゛ノ々スコノデシ−リ′として作用さす
ることかでき、別に高周波バイパスコシ戸ンザを設けな
くても良いという利点をイ］する。In addition, in the example, if the unimetal bending layer 5 is not directly formed on the surface of the layer 10 with a high dielectric constant constituting the multilayer capacitor,
Although a relatively large capacitance @C1 is generated between this layer 5 and the internal mold 4i12 that constitutes the multilayer capacitor, the internal holding frame 2 closest to the metal layer 5 of the internal capacitor WL2 is used as the ground electrode. To use the above-mentioned capacitance discharge C1
is attached to the metal layer 5. It can act as a high frequency bypass switch for the jib rest block 7, and there is no need to provide a separate high frequency bypass switch. The advantage is that
発明の効果
本発明は−に記実ＩＩ（１誰りより明らかな」：うに積
層コンデンサの表面に半導体デツプを装着し ＞１′、
ｊｉｂｉ体千ノ体音ノブする部分以外の部分に、透電
率の小さい層を形成し、ここに各電極パターンを形成し
。Effects of the Invention The present invention is described in II.
A layer with low conductivity is formed in the area other than the area where the knob is to be used, and each electrode pattern is formed here.
これらの電極パターンと」−記−’ｌ／−３９体千ノブ
と全仏にワイヤーポジティングにより電気的に接続する
ように構成したものであり、ワイヤーポジティングのだ
めのワイヤーの長さを従来に比し著しく短かぐすること
かでき高周波的な特性改善と同＋１＋’ｉ、ワイヤーポ
ジティングそのものの信頼性をも名しく向トさせること
ができ、イノ１せて全体をン轡型化し、超重Ｊ１”］化
することができるという優れた４、１長をイｊする。These electrode patterns are configured to be electrically connected to the 39 body knobs and the whole French by wire positing, and the length of the wire for wire positing is the same as before. It is possible to significantly shorten the wire position compared to the previous model, improve high frequency characteristics, and improve the reliability of the wire positioning itself. J1"] has an excellent length of 4.1.
第１図は従来の複合電子部品の断側面図、第２図は本発
明の複合電子部品における一実施例の断Ｉ１１面図、第
３図は同要部の十面図である。
１・・−・誘電率の大きい層、２−一一一内部電極、３
・・−・誘電率の小さい層、４，６・・電極パターン、
６・・・・金属層、７・・・パ１′導体チップ、８−・
・−ソイλ′−・ｊ−ツノ−イノグ、９・・・にｉシ、
’ Ｏ・・ ボッティック月１ ＋’５ｉ １１旨。FIG. 1 is a cross-sectional side view of a conventional composite electronic component, FIG. 2 is a cross-section I11 view of an embodiment of the composite electronic component of the present invention, and FIG. 3 is a tenth view of the main parts. 1...layer with large dielectric constant, 2-111 internal electrode, 3
...layer with low dielectric constant, 4,6...electrode pattern,
6...Metal layer, 7...P1' conductor chip, 8-...
・-Soi λ'-・j-tsuno-inogu, 9...ni ishi,
'O... Bottic month 1 +'5i 11 effects.
Claims (1)
、この゛Ｉ′導体チップの装着部分を除く」二層積層コ
ンテンザの表面に誘電率の著しく小さい層を形成し、こ
の層の表面（（（上記半導体チップとｌｆｆ１Ｋ電気的
に接続される電極パターンを形成して成る複合電子部品
。A 1'1' conductor chip is attached to the surface of the multilayer capacitor, and a layer with a significantly low dielectric constant is formed on the surface of the 2-layer multilayer condenser except for the part where the I' conductor chip is attached, and the surface of this layer is (((A composite electronic component formed by forming an electrode pattern that is electrically connected to the semiconductor chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57173415A JPS5961917A (en) | 1982-10-01 | 1982-10-01 | composite electronic components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57173415A JPS5961917A (en) | 1982-10-01 | 1982-10-01 | composite electronic components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5961917A true JPS5961917A (en) | 1984-04-09 |
| JPH0125218B2 JPH0125218B2 (en) | 1989-05-16 |
Family
ID=15960010
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57173415A Granted JPS5961917A (en) | 1982-10-01 | 1982-10-01 | composite electronic components |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5961917A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012182486A (en) * | 2005-06-02 | 2012-09-20 | Koninkl Philips Electronics Nv | Led assembly and module |
| JP2013179261A (en) * | 2012-01-31 | 2013-09-09 | Aisin Aw Co Ltd | Switching element unit |
| WO2014021112A1 (en) * | 2012-07-31 | 2014-02-06 | アイシン・エィ・ダブリュ株式会社 | Switching element unit |
-
1982
- 1982-10-01 JP JP57173415A patent/JPS5961917A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012182486A (en) * | 2005-06-02 | 2012-09-20 | Koninkl Philips Electronics Nv | Led assembly and module |
| JP2013179261A (en) * | 2012-01-31 | 2013-09-09 | Aisin Aw Co Ltd | Switching element unit |
| CN104160501A (en) * | 2012-01-31 | 2014-11-19 | 爱信艾达株式会社 | Switching element unit |
| US9177948B2 (en) | 2012-01-31 | 2015-11-03 | Aisin Aw Co., Ltd. | Switching element unit |
| WO2014021112A1 (en) * | 2012-07-31 | 2014-02-06 | アイシン・エィ・ダブリュ株式会社 | Switching element unit |
| JP2014029944A (en) * | 2012-07-31 | 2014-02-13 | Aisin Aw Co Ltd | Switching element unit |
| CN104335307A (en) * | 2012-07-31 | 2015-02-04 | 爱信艾达株式会社 | Switching element unit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0125218B2 (en) | 1989-05-16 |
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