JPS5968974A - MIS semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an improvement in the gate structure of a semiconductor device having both P-channel and N-channel MOS transistors.

Conventional Structures and Problems Semiconductor devices are becoming increasingly denser, that is, more miniaturized, and various problems have become apparent. One of the problems is that in conventionally used polycrystalline Si gates, the resistance of polycrystalline Si, which is the gate material, is high, which causes wiring delays with respect to miniaturization. This wiring delay has been improved by replacing polycrystalline Si as the gate material with a refractory metal or refractory metal silicide having lower resistance, or a two-layer structure of these and polycrystalline Si.

On the other hand, in semiconductor devices having both P-channel and N-channel MOS transistors, short channel effects and bunch-through phenomena, in which miniaturization directly affects the characteristics of each transistor, have become problems. These problems will first be described with respect to semiconductor devices with n-diffused polycrystalline Si gates, which are currently mainly used. Current P channel source.

Drain diffusion is formed by B ion implantation and heat treatment. The diffusion depth of the P layer due to B is:
Compared to the diffusion depth of N layer by N channel person S, B
It becomes deep because of its large diffusion coefficient.

Generally, the deeper the diffusion depth, the greater the spread of the depletion layer from the diffusion layer. However, as the channel length becomes shorter, a short channel effect occurs in which the threshold voltage decreases, or a punch-through phenomenon occurs in which the depletion layer on the drain side connects with the depletion layer on the source side, making it impossible to control the current with the gate voltage. It becomes easier. At present, the above-mentioned effects and phenomena of the P channel are more noticeable than those of the N channel, and are causing problems.

Several methods can be considered to solve this problem, but a common method for both methods is to increase the impurity concentration of the substrate. However, from the point of view of controlling the threshold voltage, it is not possible to simply increase the substrate concentration, and it is not possible to greatly change the impurity concentration in the channel region.

However, for the P channel, increasing the work function of the gate material allows the threshold voltage to be controlled and the impurity concentration of the substrate to be increased.

Next, a semiconductor device using Mo5iz as a gate material for the purpose of reducing the wiring delay mentioned above will be described. Mo
Si2 has a work function larger by about 0.56 V than N-diffused polycrystalline Si. Therefore, for N-channel transistors, the threshold voltage is about 0.6 V higher, and for P-channel transistors, it is about o, e> V lower. Although these threshold voltages need to be adjusted, the P channel has a favorable tendency as described above because the work function of the gate material is large. However, for N-channels, adjusting the threshold voltage essentially lowers the impurity concentration of the substrate, which tends to increase the short channel effect and punch-through phenomenon.

As mentioned above, N-diffused polycrystalline Si
When using MoSi2 as the gate material, the P channel side is disadvantageous against short channel effects and punch-through phenomena, whereas when using a gate material such as MoSi2, which has a larger work function than N+ diffused polycrystalline Si. The N-channel side is at a disadvantage.

Purpose of the Invention The present invention takes into consideration the above-mentioned problems, and aims to provide a high-density, high-speed semiconductor device that reduces short channel effects and punch-through phenomena in response to miniaturization of elements. .

Structure of the Invention The present invention has a gate structure of one layer or multiple layers, and the layer in contact with the gate insulating film is N in a P-channel transistor.
Diffused polycrystalline Si is a high-melting point metal or high-melting point metal silicide with a higher work function than N-diffused polycrystalline Si.In N-channel transistors, use of N-diffused polycrystalline Si makes it easy to apply to manufacturing processes and improves semiconductor device performance. The purpose is to improve performance in accordance with the above objectives.

The explanatory diagram of the embodiment is an embodiment of the present invention, and the P well type CMO3LSI P
A cross-sectional view of a channel transistor and an N-channel transistor 2 after the lease and drain diffusion steps are shown, respectively.

This example will be explained step by step below. First, a P-well diffusion layer 4 is formed on an N-type substrate 3, and then a field oxide film 6 is formed. Next, ion implantation for threshold voltage control is performed to form a gate oxide film 6. The above steps are the same as the normal manufacturing process of 0MO8LSI. Next, a polycrystalline S1 film is formed on the entire surface of the substrate by the CVD method, and N is diffused.
An i-layer 7 is formed. Next, by using a photomask for forming the P-well 4, the polycrystalline Si on the P-well 4 is removed.
The polycrystalline S1 layer in the P channel trough 2 41 portion is removed by plasma of CF4+02 gas, leaving the resist only on the layer 7.

After removing the resist, the refractory metal or refractory metal silicide layer of the film JF9E200OA, for example, is deposited by sputtering or electron beam evaporation.
An oSi2 layer 8 is formed.

In the above steps, N+ diffused polycrystalline S is formed on the P well 4.
Two-layer structure of 1 and MoSi2, MoS on other substrates
A single layer structure of i2 is formed. (At this time, if photomasks are used separately for P and N, each will have a single layer structure of MoSi2 and crystal $1.) Next, a gate pattern is formed with a resist, and a MoSi2 layer 8 and a polycrystalline Si layer are formed. 7 is simultaneously etched with CF4+02 gas plasma. Further, when the source and drain diffusion layers 9 of the P-channel transistor and the source and drain diffusion layers 10 of the N-channel transistor are formed, the state shown in FIG. 1 is obtained.

To complete the 0MO3LSI, use the normal 0MO3LS after this.
Similar to the manufacturing process of I, insulating film formation, contact hole formation,
Next is aluminum wiring formation and passivation film formation.

According to the above embodiment, the gate of the P-channel transistor has a single-layer structure of MoSi2, and the gate of the N-channel transistor has a two-layer structure of MoSi2 and polycrystalline Si. For the N channel, it is determined by MoSi2, and for the N channel, it is determined by N+ diffused polycrystalline Si.

In this embodiment, the thickness of the polycrystalline Si layer 7 is sufficient as long as the work function is preserved, and experiments conducted by the present inventors have shown that as many as 600 people are sufficient. Also MoS
The film thickness of i2 can be changed depending on the operating speed requirements of the LSI. In terms of resistance value, 1000A is sufficient. In addition, in this example, M is used as a high melting point metal or a high melting point metal silicide having a larger work function than the N diffused polycrystalline S1.
oSi2 was used, but in addition to this, “+ WI WSi2
A similar effect can be obtained by using . At this time, Mo+
In the case of W, the resistance is sufficiently low even if the film thickness is reduced to 60 OA, making it suitable for future high-density and high-integration devices.

Effects of the Invention As described above, the present invention provides a method for setting the work function of the gate of an MIS transistor in the P channel using a refractory metal or refractory metal silicide having a higher work function than N diffused polycrystalline Si. By setting the channels with N-diffused polycrystalline Si, it is possible to improve the substrate concentration of each channel in a favorable direction and reduce the short channel effect and punch-through phenomenon during miniaturization. . Furthermore, it goes without saying that by using a high melting point metal or a high melting point metal silicide as a gate material, wiring delays can be reduced and the speed of the semiconductor device can be increased.

[Brief explanation of the drawing]

The figure shows a P-well type 0NO3LS according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view of both the P-channel and N-channel transistors of I after the source and drain diffusion steps. 1...P channel transistor, 2...
・N-channel + channel transistor, 3... Semiconductor substrate, 7...
. . . N-diffused polycrystalline Si layer, 8 . . . Refractory metal or refractory metal silicide layer. Name of agent: Patent attorney Toshio Nakao and 1 other person1
month 2

Claims (2)

[Claims] (1) Both P-channel and N-channel MIS transistors are provided on a semiconductor substrate, and the gate structure has a single-layer or multi-layer structure, and the layer in contact with the gate insulating film of this structure is the P-channel transistor. A MIS semiconductor device characterized in that the N-diffused polycrystalline silicon is used as a refractory metal or a refractory metal silicide having a higher work relationship than N-diffused polycrystalline silicon in the N-channel transistor. (2) The MIS semiconductor device according to claim 1, characterized in that a refractory metal or a refractory metal silicide is laminated on N-diffused polycrystalline silicon.