JPS5972243A - Digital data muting circuit - Google Patents

Abstract

PURPOSE:To mute digital data by opening and closing a gate means interposed in a data bus by the output of a means for detecting input data being within a specific range including zero. CONSTITUTION:The gate means 2 which controls the data bus 1 into a disconnection or connection state is connected in the middle of the data bus 1. The detecting means 3 is connected to the input-side data bus 1 and detects the input data entering the specific range including zero to generate an output throughout the period from when the input data enters said specific range firstly after a muting signal is generated and supplied to when the input data enters the specific range firstly after the muting signal is ceased. The gate means 2 receives the output of the detecting means 43 to cut off the data bus 1, and outputs zero data.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital data mute circuit used in digital audio systems and the like.

2. Description of the Related Art A playback device that plays back audio signals through analog signal processing includes an analog signal mute circuit. Furthermore, in the analog signal domain of the digital audio system, the conventional analog signal mute circuit described above can be used. However, there was no mute circuit in the digital data area.

The present invention provides a digital data muting circuit that does not require switching means or analog switches in the middle of a signal line, which are required in conventional analog signal muting circuits, and enables reliable, high-speed muting without generating noise. The purpose is to

Hereinafter, the present invention will be described with reference to examples.

FIG. 1 is a block diagram showing one embodiment of the present invention.

1 is a data bus. Connected to the data bus is a date means 2 which controls the data bus 1 to be substantially cut off or connected by an external signal, and outputs data when the input data is in the 0'' state as output data during the cut off state.

3 is connected to all or part of the input side data bus 1 of the gate means 2, so that only the input data or a predetermined bit in the input data is input, and the input data or a predetermined bit between 'O'' is connected. When the input data first enters the predetermined range after the muting signal is generated and the muting signal is supplied, the input data is input for the first time after the muting signal disappears. It is a detection means that generates an output for a period until the time when the detection means enters the predetermined range.

The output of the detection means 3 is supplied to the r-t means 2 to substantially cut off the data bus.

When the muting signal is not supplied, the detection means 3 does not generate any output. Therefore, the dart means 2 controls the data bus 1 to be substantially connected. As a result, the input data passes through the gate means 2 and is output as output data.

On the other hand, if a muting signal is generated, the input data will first be 0" after the muting signal is generated.
When the data enters a predetermined range between the two, the detection means 3 generates an output, the dart means 2 receives the output from the detection means 3, the data bus 1 is cut off, and the input data is output as output data. First, the date means 2 outputs data when the input data is '0' as output data.

Also, when the muting signal disappears, the input data is +tO7 for the first time since the muting signal disappears.
1, the output from the detection means 3 disappears, and the date means 2 substantially brings the data bus 1 into a connected state. 'Therefore, from the time the input data first falls within the predetermined range after the muting signal is generated, until the input data first falls within the predetermined range after the muting signal disappears, the output data is the value when the input data is 0''.As a result, when muting the input data, the output data does not suddenly become 0, but from the moment the input data falls within the predetermined range. Since the output data is in the 11011 state, it is possible to prevent the occurrence of shock noise that would occur if the output data were suddenly changed to the "'0#" state due to the generation of the muting signal.

The same holds true even when the mute operation is canceled.

On the other hand, since the signals handled in the digital audio system are alternating current signals such as music signals, the O level always completely crosses. When such a signal is converted into digital data, it cannot be said that input data in which each bit of the input data is all 0 exists for quantization. However, there is always data having a value near '0', and as described above, there is input data where the input data falls within a predetermined range between 0'.

In addition, detection of input data within a predetermined range surrounding °°0'' differs depending on the code form of the input data.
” bit configuration is also similar.

Next, a specific example will be explained.

FIG. 2 is a block diagram showing a specific example of one embodiment of the present invention, in which the complement of a negative number ft2 (2'+1 complete
nt) is shown as an example.

In this specific example, it is assumed that the input data has an 8-bit configuration.

The dart means 2 has 81 AND/GO signals into which signals of each bit of input data are respectively input.2. It consists of ~2-7.

The detection means 3 has an AND/DART 4 which receives the upper 5 bits of the input data, inverters 5 to 9 which invert the upper 5 bits of the input data, and receives the output signals of the inverters 5 to 9. do and c-)10
, a flip-flop 12 which receives the output signal of the AND-DART 4 and the output signal of the AND-DART 10, and a flip-flop 7'12 which selectively receives the output signal of the OR-DART 11 by being switched by a muting signal.
7' and a changeover switch means 13 leading to the reset terminal. Flip 70 Tsubu 12 Q
The output is each and goo constituting dart means 2) 2
．． It is supplied to ~2-7.

The flip-frog 12 is initially set to the set side when the power is turned on. Therefore, the darts of AND darts 2-o to 2-7 are set to the open state, and the input data is outputted as output 0 data via AND darts 2-1-2- to 2-7.

Next, when a muting signal is generated, the changeover switch means 13 is switched from the state shown in FIG. ooooo
When the voltage falls within the range from "ooxxx" to "11111 XXX", the output signal of the OR gate 11 becomes a high potential output υ, and the flip-flop 12 is reset.

As a result, AND gates 2-o to 2-7 close their darts. As a result, the data bus 1 becomes substantially disconnected, and the output data becomes "'ooooooooo", that is, the input data is 0, and the ε NEET operation is performed.Next, the muting signal disappears, the changeover switch means 13 returns to the state shown in FIG.
The flip-flop 12 is set on standby with the output signal. Then the input data is "'oooooxxx"
If it falls within the range of ~”IIIIIIXXX”, the oracle 1
1 output signal is a high potential output, flip-flop 1
2 is set. As a result, AND gate 2- to 2-7
opens its r-). Therefore, the data bus 1 is substantially connected, and the input data is outputted as output data, and the mute operation is canceled.

In the above specific example, the upper 5 bits of the input data are detected, but this can be done by determining the number of bits corresponding to a predetermined range between "0" of the input data. It may be set within a range that does not cause noise when canceling. Also, if the predetermined range surrounding Pa0'' is taken out more than necessary.

There is a possibility that the time from when the muting signal is generated until the muting operation is performed and the time from when the muting signal disappears until the muting operation is canceled becomes longer. For this reason, it is desirable to set the predetermined range as wide as possible within a range in which noise does not occur in the output. Further, the dart means 2 is the AND gate 2-o of the above specific example.
2-7 may be replaced with a latch or flip-flop with a clear function.

Next, when the code form of the input data is simple/4 binary, if the detection means 3 detects that the input data of a predetermined number of high-order bits excluding code bits are °'0''. good.

In addition, when the code form of the input data is Offsera)/S inary, the intermediate value indicates 'o''e, so if the detection means 3 detects that the input data falls within a predetermined range between the intermediate values. In this case, the gate means 2 may be forcibly set to the intermediate value of all output data during the mute operation.

FIG. 3 is a block diagram showing an example of the dating means 2 in the case of offset binary.

In this case, the gate means 2 is a sol-up resistor in place of the AND dart 2- to which the input data of the most significant bit of the dart means 2 applied in the two's complement form shown in FIG. A high potential signal supplied via the detection means 3
ANDf-)Ll which receives as input the output signal of , that is, the signal obtained by inverting the Q output of the flip-flop 12 by the inverter 2-2.

, the signal of the most significant bit of the input data and the AND gate 2. 2.1 to which the output signal of o is supplied.
Use. .

According to the r-) means 2 shown in FIG. 3, during the ε neat operation, the y-toe of the AND dart 2-1o is opened, and the output signal of the AND dart L1o becomes a high potential.
And darts 2-o to 2-6 have their dates closed. As a result, the output data is '' during mute operation.
10000000" and "O"ee output in the case of offset binary.

Also, when the mute operation is canceled,
-) Llo (r-) is in the closed state, and the unpickets 2- to 2-6 are in the open state, so the input data is output as output data, and the data Bus 1 becomes substantially connected.

As explained above, according to the present invention, if it is detected that the input data on the data bus is within the predetermined range between 0, then after the neeting signal is generated, the input data is first detected to be within the predetermined range. a detecting means that generates an output for a period of time from when the input data first enters the predetermined range after the extinguishment of the neat signal; Controlled by the output of the detection means, the data bus is substantially cut off while the output of the detection means is being generated, and the data when the input data is in the O state is outputted, and the data bus is controlled by the output of the detection means during the period when the output is not generated. Since the present invention includes dart means for substantially connecting the mute operation, noise is not generated when the mute operation is started and when the mute operation is canceled. Furthermore, since the i-NEET operation is performed in the digital signal domain, it can be performed at high speed and accuracy.

Furthermore, there is no need to provide in the signal line a switch means, an analog switch, etc., which are connected in the middle of the signal line, which is required in the analog signal mute circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a specific example to which an embodiment of the present invention is applied. FIG. 3 is a block diagram showing an example of the gate means when the data is in an offset/guidary format. DESCRIPTION OF SYMBOLS 1... Data bus, 2... Dart means, 3... Detection means, 2-o to 2-7 + 2-1°, 4 and 10
... Ampiquet 9-to, 2-11 and 11...
Or dirt, 12...flip 70 horns, work 3...
Changeover switch means. Patent Applicant Trio Co., Ltd. Representative Patent Attorney Nobuo Sunako Figure 1 Figure 2 Figure Micody 4”°I Hatake No.

Claims (1)

[Claims] After detecting that the input data on the data bus is within a predetermined range between O and generating a muting signal,
a detection means for generating an output during a period from when the input data first enters the predetermined range to when the input data first enters the predetermined range after the muting signal disappears; Connected to the middle of the bus,
The data bus when the output of the detection means is not being generated is substantially cut off, the data when the input data is in the O state is output, and the data bus when the output of the detection means is not being generated is substantially connected. ) means.