JPS5979495A - Shift circuit - Google Patents

Abstract

PURPOSE:To eliminate the shift control using two complements and to attain a simple and high-speed shift control by performing a shift control at a right shift by an inverter using a complement of 1 of shift number N and supplying a lacking bit from another shift register. CONSTITUTION:For the right shift control, the complement of 1 of the shift number N is obtained from the inverter 6. In case the shift number is supplied with the complement of 1, the shift number is less by 1 compared with a case where the complement +1 of the complement of 2 of -N=N. This inconvenience is solved by adding a left shift of a bit through a shift circuit 7. That is, the complement of 1 of shift number N is obtained by the inverter 6 in a right shift mode and applied to the shift circuits 2 and 3 with the same bit allotment as a conventional circuit. The output of the circuit 3 is equal to the data that is shifted less by a bit than the normal shift. Therefore the signal R is turned genuine to have a left shift further by a bit through a shift circuit 7. Thus a normal shift result is obtained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a shift circuit used in digital data processing equipment, and particularly to a shift circuit for shifting an arbitrary number of shifts during one cycle without having a latch circuit. Regarding the so-called barrel shifter.

[Technical background of the invention]

Figure 1 shows an example of the conventional (1) configuration.
) is a 64-bit data selector with logical shift,
It corresponds to shift modes such as arithmetic shift and rotate shift, and selects 32-bit data D, etc. (2) is 0
．． It is a 16.32.48-bit shift circuit and has a left rotation shift function. This shift circuit (2) is actually made up of a data selector.

(3) is 0. ], . . . This is a left shift circuit that operates in a shift mode in units of 15 bits. This circuit is also composed of a data selector and outputs a 32-bit result. The number of shifts in shift circuit 12) and shift circuit (3) is given by N,
The data is applied to shift circuits (2) and (3) via a data filler (4). (5) is an adder for generating a shift number when performing a right shift, and calculates the two's complement of the shift number N. The shift number N is composed of 6 bits and indicates a shift of 0 to 31 bits.

Next, the operation of the conventional circuit shown in FIG. 1 will be explained.

First, in the case of left logical shift, data selector +11 selects the set of 1, 01 [7, shift circuit (2
) to 57, '/7 number Nld (I) ＊＊＊＊＊')2
(* may be either 1o'' or '1'), the upper 2 bits are sent to the shift circuit (2) and the lower 4 bits are sent to the shift circuit (3) via the data selector (4). Control.The upper 2 bits of the shift number N are 0 when it is 'oo'.
Bit, '01' R16 hit, '10' time 3
2 bits, 'II' has a weight of 48 pits. The lower 4 bits still have a weight of 0 to 15 bits. Therefore, in the shift circuit (2), since the most significant bit of the shift number N is 0', data rotated and shifted to the left by 0 or 16 bits is selected and sent to the shift circuit (3). The shift circuit (3) shifts the remaining 0 to 15 bits to the left and outputs the data. The same goes for left arithmetic shifts.

However, in the case of left arithmetic shift, the sign bit is D. is controlled so that it remains, but since it has no direct relation to the present invention, its explanation will be omitted. For left rotation shift, data selector (1)
[D3. The other operations for selecting the set of ~31 + Do ~31J are the left logical shift and rotation described above, so I can save I.
Add l+75.

Next, the right shift will be explained. The operation of the data selector (1) corresponding to right shift mode is r with right arithmetic shift.
It is the same as the left shift except that the combination of "Do~, I, S" is selected. Here, S is the sign bit D of data D
is expanded to 32 bits, and the shift number N is
First, it is converted into a two's complement number by an adder (5). That is 6
The value of 4-N is selected by the data selector (4) and applied to the shift circuit (2) and the straddle (3) in the same manner as above. For example, when shifting 5 bits to the right, the shift number N=(000101)2 is converted to (111011)2 by the adder (5) and output from the data selector (4). The shift circuit (
2) generates the result of 48-bit left rotation shift and outputs it to the shift circuit (3). In parts 1 and 2, the shift circuit (3) shifts from the lower 4 bits (''1011'') to the left 11 bits.
Bit shift is performed to generate the final result, but this result is 5 bits to the right.
Equivalent to bit shift.

[Problems with background technology]

In the above conventional technology, the two's complement of the shift number N must be found in the right shift, and the time required for this cannot be ignored, and the performance of the entire data processing device will not be affected. It had some drawbacks.

[Purpose of the invention]

SUMMARY OF THE INVENTION In order to overcome the above-mentioned drawbacks, it is an object of the present invention to provide a shift circuit that does not require shift control using two's complement numbers and is capable of high-speed and simple shift control.

[Summary of the invention]

In the present invention, shift control when shifting to the right is performed by an inverter using the 1's complement of the shift number N, and the missing 1 bit is added to another shift register to obtain a normal shift result. It is.

[Embodiments of the invention]

FIG. 2 is a diagram showing an embodiment of the present invention. In this figure, the same parts as in FIG. 1 are given the same numbers. To explain the newly added part, ((i) f
l Inverter that inverts each bit of shift number N, (7)
is a left shift circuit for 0" or "1" bits, and the signal R indicating right shift is true ("only when there is one")
This is a circuit that performs 1#1#bitsoft.

That is, when shifting to the left, R is set to false CO, and the shift circuit (power) does not perform a shift operation. Also, this shift circuit (power) is composed of a data selector like the other shift circuits +21, and has a 32-bit output. do.

Next, the operation shown in FIG. 2 will be explained. First, when shifting to the left, the shift number N is the same as the data selector (4) as in the conventional example.
is applied to shift circuits (2) and (3).

Also, the signal is set to false, and the shift circuit outputs the human power as it is without performing a shift operation. At this time, the data selector (1) and the shift circuit (2).

(3) performs the same operation as in FIG.

Next, the shift system b111 at the time of right shift obtains the ``1'' complement (N) of the shift number N from the inverter (6). ′
If the shift number is given as a 1''s complement, it is a 2's complement (-N
=N+1), but this disadvantage is solved by adding a 1-bit left shift using the shift circuit (i.e., right shift lH).
j: The complement of ``1#'' of the shift number N is obtained by the inverter (6), and is given to the shift circuit +21, (31) via the data selector (4) with the same bit assignment as the conventional circuit. ) output is 1 less than regular shift
Since the data has been shifted by a smaller number of bits, by making the signal R true, the shift circuit (power) further softens the data by one bit to the left to obtain a normal shift result.

〔Effect of the invention〕

The present invention is as described above, and since the operation by the adder is not required when shifting to the right, the shift is increased in speed by the difference between the operation time of the shift circuit (power and the adder (5)). Generally, the operating time of the data selector forming the shift circuit I'flJ is several times shorter than that of the adder, so the effect of the configuration of the present invention is large.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the configuration of a conventional shift circuit, and FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. 1: Data selector 2: Shift circuit 3: Shift circuit 4: Data set / Lid, 6: Inverter, 71-bit shift shift, It: Signal indicating right shift. Agent Patent Attorney Inoue - Rikitsutsu 1 Figure 2

Claims (1)

[Claims] n+] means for calculating the 1's complement ppq of the shift number N consisting of hits (n: positive number); means for selecting the shift numbers N and N; or 1-bit shifting means 7, and the ot or 1-bit shifting means inputs 2-bit data by shifting 1 bit in response to the selection of the shift number N, and inputs 2-bit data from 0 to 2 only in one direction. - A shift circuit characterized in that when shifting by 1 bit, a shift is performed in both left and right directions to obtain a shift result of 2° bit length.