JPS60164269A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS60164269A JPS60164269A JP59019782A JP1978284A JPS60164269A JP S60164269 A JPS60164269 A JP S60164269A JP 59019782 A JP59019782 A JP 59019782A JP 1978284 A JP1978284 A JP 1978284A JP S60164269 A JPS60164269 A JP S60164269A
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- voltage
- transistor
- integrated circuit
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/316—Testing of analog circuits
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は集積回路内部の電圧をモニタするのに適した半
導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device suitable for monitoring voltage inside an integrated circuit.
集積回路内部の電圧をモニタするには、内部ノードに直
接パッドを取り付けることが考えられる。しかしこれで
は、この/4’ツドに測定器を当てたとき、測定器のも
つloPF以上のキャノ臂シタンスが、集積回路内部ノ
ードに付加してしま9ことになる。そのためその内部メ
ートの信号遅延が極端に大きくなってしまい、正確な測
定が不可能になるという不都合がある。通常の内部ノー
ドのキャノ臂シタンスは数10 fFだからである。そ
のため第1図のようなトランジスタ1段が使われるわけ
である。図中1は集積回路、2はその内部節点、3はM
OS トランジスタ、4はノ4ツド、5は電圧測定用針
、6はノード、7は抵抗である。このものは、パッド4
に測定器のもつ10 PF以上のキャパシタンスが付加
されても、内部ノード2にはトランジスタ3のf−)容
量しか接続されていないため、内部ノードの信号遅延が
測定することによって極端に変化してしまうことはない
。To monitor voltages inside an integrated circuit, it is possible to attach pads directly to internal nodes. However, in this case, when a measuring instrument is applied to this /4' node, a capacitance greater than the loPF of the measuring instrument is added to the internal nodes of the integrated circuit. Therefore, the signal delay of the internal mate becomes extremely large, making accurate measurement impossible. This is because the canonical capacitance of a normal internal node is several tens of fF. Therefore, one stage of transistors as shown in Figure 1 is used. In the figure, 1 is an integrated circuit, 2 is its internal node, and 3 is M
OS transistor, 4 is a node, 5 is a voltage measuring needle, 6 is a node, and 7 is a resistor. This one is pad 4
Even if a capacitance of 10 PF or more of the measuring instrument is added to the internal node 2, only the f-) capacitance of the transistor 3 is connected to the internal node 2, so the signal delay at the internal node will change drastically due to the measurement. It never gets put away.
モニタ用のトランジスタ3を使って内部ノード5の電圧
を測定する時は、ノクツド4に針5を接触させ、それと
電源の間に抵抗7をつなぎ、ノード6の電圧を測定する
。しかしノード6の電圧はノード5の電圧と等しくない
ため、ノード2の内部電圧はノード6の電圧からトラン
ジスタ3の特性を加味して逆算しなければならず、大変
わずられしかった。またトランジスタ3の特性そのもの
は測定できないので、別の場所につくった別のトランジ
スタの特性からトランジスタ3の特性を推定するので、
不正確さもあった。これは場所が離れていると、トラン
ジスタのしきい値電圧や移動度等にばらつきがあるから
である。When measuring the voltage at the internal node 5 using the monitor transistor 3, the needle 5 is brought into contact with the node 4, the resistor 7 is connected between it and the power supply, and the voltage at the node 6 is measured. However, since the voltage at node 6 is not equal to the voltage at node 5, the internal voltage at node 2 must be calculated backwards from the voltage at node 6 by taking into account the characteristics of transistor 3, which is very troublesome. Also, since the characteristics of transistor 3 itself cannot be measured, the characteristics of transistor 3 are estimated from the characteristics of another transistor made in a different location.
There were also inaccuracies. This is because if the locations are far apart, there will be variations in the threshold voltage, mobility, etc. of the transistors.
本発明は上記実情に鑑みてなされたもので、従来複雑か
つ不正確であった集積回路の内部電圧を容易かつ正確な
らしめる半導体装置を提供しようとするものである。The present invention has been made in view of the above-mentioned circumstances, and it is an object of the present invention to provide a semiconductor device that allows the internal voltage of an integrated circuit, which has conventionally been complicated and inaccurate, to be easily and accurately determined.
本発明は、マイナス入力と出力を結線した差動増幅器に
よってゲルテージ7オロワ(電圧追随回路)を構成し1
1.この出力を金属パッドに接続することを特徴とし、
これによって従来と違ってトランジスタの較正をしたり
することなく、容易に集積回路の内部電圧が測定できる
ようにしたものである。In the present invention, a Gertage 7 Olower (voltage tracking circuit) is configured by a differential amplifier with a negative input and an output connected.
1. The feature is that this output is connected to a metal pad,
This makes it possible to easily measure the internal voltage of an integrated circuit without having to calibrate the transistors unlike in the past.
以下図面を参照して本発明の一実施例ya−説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第2図は同実施例の構成図であるが、これは第1図のも
のと対応させた場合の例であるから、対応個所には同一
符号を付して説明を省略し1特徴とする点を説明する。FIG. 2 is a configuration diagram of the same embodiment, but since this is an example in which it corresponds to that in FIG. Explain the point.
図示される如く差動増幅器8のプラス入力は集積回路1
の内部ノード2と接続し、マイナス入力は出力と接続し
、この出力は、集積回路1を構成するチッグの金属ノ4
ツド4に接続されている。図中9はノ4ツド4の電圧を
検出するための測定器である。As shown in the figure, the positive input of the differential amplifier 8 is connected to the integrated circuit 1.
The negative input is connected to the internal node 2 of the integrated circuit 1, and the negative input is connected to the output, which is connected to the internal node 2 of the chip
Connected to Tudo 4. In the figure, numeral 9 is a measuring device for detecting the voltage of the node 4.
ここで差動増幅器8の増幅度をAとし、入力。Here, the amplification degree of the differential amplifier 8 is set to A, and the input voltage is set to A.
出力電圧をそれぞれvin 、 VoutとするとA
(Min −Vout ) = Vout ”= (1
)となる。(2)式において増幅度Aを充分大きくする
と、 Vout = Vinとなり、出力電圧V ou
tをモニタすれば入力電圧Vinと等しいことがわかる
。この回路はぎルテージ7オロワという。即ち従来必要
であったトランジスタの較正に関する手間やトランジス
タ特性の推定による測定結果の不正確さがなくなった。If the output voltages are vin and Vout, respectively, A
(Min−Vout)=Vout”=(1
). If the amplification degree A is made sufficiently large in equation (2), Vout = Vin, and the output voltage V ou
By monitoring t, it can be seen that it is equal to the input voltage Vin. This circuit is called Giltage 7 Orowa. That is, the trouble associated with transistor calibration and the inaccuracy of measurement results due to estimation of transistor characteristics, which were conventionally necessary, are eliminated.
第3肉は差動増幅器を用いた?ルテージ7オロワの例で
ある。この例では駆動トランジスタはNチャネル型、負
荷はPチャネル型の構成となっているが、逆に駆動トラ
ンジスタなPチャネル型、負荷なNチャネル型とした構
成も考えられる。トランジスタ10〜13で構成される
第1段目の差動増幅器と、トランジスタ14〜17で構
成される第2段目の差動増幅器が直列接続されている。Did the third meat use a differential amplifier? This is an example of Lutege 7 Orowa. In this example, the drive transistor is an N-channel type and the load is a P-channel type, but conversely, a configuration in which the drive transistor is a P-channel type and the load is an N-channel type is also conceivable. A first stage differential amplifier made up of transistors 10-13 and a second stage differential amplifier made up of transistors 14-17 are connected in series.
負荷トランジスタ70.11のダートは共通接続され、
その電位は負荷トランジスタ11のドレインと同じにな
っており、カレントミラー型となっている。カレントミ
ラー型の増幅度は太きく(2)式のAを大きくするのに
役立っている。fl、7’42段直列接続しないと充分
な増幅度Aがかせげない1.2段の差動増幅器を使うも
う1つの理由は、充分な駆動能力を得るためであり、測
定器系の大きな容量(例えば10PF )を迅速に駆動
するために、最終段トランジスタ16.17は大きなチ
ャネル幅を持つ必要があるが、このような大きなトラン
ジスタを内部ノードに直接接続すると、やはり内部回路
へのしよう乱が大きい。第3図(b)中に記載の分数は
W/L (Wはチャネル幅、Lはチャネル長)である。The darts of the load transistors 70.11 are connected in common,
Its potential is the same as that of the drain of the load transistor 11, and is of a current mirror type. The amplification degree of the current mirror type is large and is useful for increasing A in equation (2). fl, 7' 42 stages must be connected in series to obtain sufficient amplification A. Another reason for using a 1.2-stage differential amplifier is to obtain sufficient drive capability, and to avoid the large capacitance of the measuring instrument system. (for example, 10PF), the final stage transistors 16 and 17 need to have a large channel width, but if such a large transistor is connected directly to an internal node, it will still cause disturbance to the internal circuit. big. The fraction shown in FIG. 3(b) is W/L (W is the channel width and L is the channel length).
第3図(b)のトランジスタI8のように、駆動用トラ
ンジスタ16.17に直列に電流制限用の素子を入れて
もよい。ここではトランジスタ18で電流制限している
が、抵抗でもよい。本回路のDC(直流)及びAC(交
流)実測特性をそれぞれ第4図、第5図に示す。DC、
AC共に入力電圧−vinと出力電圧V outは等し
い。A current limiting element may be inserted in series with the driving transistors 16 and 17, like the transistor I8 in FIG. 3(b). Here, the current is limited by the transistor 18, but a resistor may also be used. The measured DC (direct current) and AC (alternating current) characteristics of this circuit are shown in FIGS. 4 and 5, respectively. DC,
For both AC, the input voltage -vin and the output voltage Vout are equal.
第6図は本発明の変形例である。ここでは2段目の差動
増幅器にはカレントミラーな使わず、単なる負荷を有す
る(独立負荷型)差動増幅器にしている。カレントミラ
ー皇だと出力は、Pチャネル型トランジスタのしきい値
電圧\VTHPたけ電源電圧VDDから下がった電圧ま
でしか上がらないが、第6図の構成ではもつとVDD近
くまで上がるものである。FIG. 6 shows a modification of the invention. Here, a current mirror is not used for the second-stage differential amplifier, but a differential amplifier with a simple load (independent load type) is used. In the case of a current mirror, the output increases only to a voltage lower than the threshold voltage \VTHP of the P-channel transistor and the power supply voltage VDD, but in the configuration shown in FIG. 6, the output increases to nearly VDD.
なお本発明は上記説明のみに限られず種々の応用が可能
である。例えば金属パッド4は製造段階で使用し、製品
になるときは、パッド上に保ifをかぶせてしまっても
よい。また集積回路電源の低消費電力化を図るため、別
に29ツドを設け、前記差動増幅器の電源が、集積回路
本体で使用されている電源とは独立して外部から供給す
るようにしてもよい。Note that the present invention is not limited to the above explanation, and can be applied in various ways. For example, the metal pad 4 may be used in the manufacturing stage, and when the product is manufactured, a protective layer may be placed over the pad. Further, in order to reduce the power consumption of the integrated circuit power supply, a separate power supply may be provided, and the power supply for the differential amplifier may be supplied from the outside independently of the power supply used in the integrated circuit main body. .
以上説明した如く本発明によれば、従来に比較シそニタ
トランジスタの較正がいらス、簡便かつ正確な内部電圧
測定が可能である。また差動増幅器2段構成としたため
、測定装置によるしよう乱を内部に持ち込むことなく内
部電圧を測定できるものである。As explained above, according to the present invention, it is possible to easily and accurately measure the internal voltage without having to calibrate the comparison sensor transistor in the past. Furthermore, since it has a two-stage differential amplifier configuration, it is possible to measure the internal voltage without introducing disturbances caused by the measuring device inside.
第1図は従来の内部電圧モニタ回路を示す構成図、第2
図は本発明の一実施例の構成図、第3図(alはそのデ
ルテージフオロワ回路の構成図、同図(b)は同図(a
)の具体的回路図、第4図(alはDC実測特性の測定
回路図、同図(blないしくdlはその実測特性図、第
5図はAC実測特性図、第6図は第3図(bJの変形例
を示す回路図である。
1・・・集積回路、2・°°内部ノード、4・・・]臂
ラッド8・・・差wJ増幅器。
第1図
7
第3ry1
(a)
(b)
第5図
ACCharacteristics of Volt
age FollowerVoc [v)
第6鼎
DDvDDFigure 1 is a configuration diagram showing a conventional internal voltage monitor circuit;
The figure is a block diagram of an embodiment of the present invention, FIG.
), Figure 4 (al is the measurement circuit diagram of the DC actual measurement characteristics, the same figure (bl or dl is the actual measurement characteristic diagram, Figure 5 is the AC actual measurement characteristic diagram, Figure 6 is Figure 3) (It is a circuit diagram showing a modification of bJ. 1... Integrated circuit, 2.°° internal node, 4...] Arm rad 8... Difference wJ amplifier. Fig. 1 7 3rdry1 (a) (b) Figure 5 ACCharacteristics of Volt
age FollowerVoc [v] 6th Ding DDvDD
Claims (1)
イナス入力は出力と接続された差動増幅器を有し、その
出力にパッド状の金属を配置したことを特徴とする半導
体装置。 (2)前記差動増幅器は2段のカレントミラー型増幅器
であることを特徴とする特許請求の範囲第1項に記載の
半導体装置。 (3) 前記差動増幅器の第1段目をカレントミラー型
差動増幅器で構成すると共に第2段目を独立負荷型の差
動増幅器で構成し、これら第1段目と第2段目の差動増
幅器を直列接続したことを特徴とする特許請求の範囲第
1項に記載の半導体装置。 (4)前記差動増幅器の電源が、前記集積回路で使用さ
れている電源とは独立して外部から供給されることを特
徴とする特許請求の範囲第1項に記載の半導体装置。[Claims] +1) A semiconductor characterized in that it has a differential amplifier whose glass input is connected to an internal node of an integrated circuit and whose negative input is connected to an output, and a pad-like metal is arranged at the output of the differential amplifier. Device. (2) The semiconductor device according to claim 1, wherein the differential amplifier is a two-stage current mirror type amplifier. (3) The first stage of the differential amplifier is composed of a current mirror type differential amplifier, and the second stage is composed of an independent load type differential amplifier. The semiconductor device according to claim 1, characterized in that differential amplifiers are connected in series. (4) The semiconductor device according to claim 1, wherein a power source for the differential amplifier is supplied from outside independently of a power source used in the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59019782A JPS60164269A (en) | 1984-02-06 | 1984-02-06 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59019782A JPS60164269A (en) | 1984-02-06 | 1984-02-06 | semiconductor equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60164269A true JPS60164269A (en) | 1985-08-27 |
| JPH0452905B2 JPH0452905B2 (en) | 1992-08-25 |
Family
ID=12008893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59019782A Granted JPS60164269A (en) | 1984-02-06 | 1984-02-06 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60164269A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197581A (en) * | 1984-10-19 | 1986-05-16 | Fujitsu Ltd | Logic integrated circuits and logic integrated circuit systems |
| JPS6276802A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | inverting amplifier |
| JPH0552780U (en) * | 1991-12-20 | 1993-07-13 | 横河電機株式会社 | IC tester |
| JPH08166429A (en) * | 1994-12-15 | 1996-06-25 | Advantest Corp | Driver circuit |
| KR100292702B1 (en) * | 1997-08-12 | 2001-06-15 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor integrated circuit device capable of externally monitoring internal voltage |
-
1984
- 1984-02-06 JP JP59019782A patent/JPS60164269A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6197581A (en) * | 1984-10-19 | 1986-05-16 | Fujitsu Ltd | Logic integrated circuits and logic integrated circuit systems |
| JPS6276802A (en) * | 1985-09-30 | 1987-04-08 | Toshiba Corp | inverting amplifier |
| JPH0552780U (en) * | 1991-12-20 | 1993-07-13 | 横河電機株式会社 | IC tester |
| JPH08166429A (en) * | 1994-12-15 | 1996-06-25 | Advantest Corp | Driver circuit |
| KR100292702B1 (en) * | 1997-08-12 | 2001-06-15 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor integrated circuit device capable of externally monitoring internal voltage |
| US6339357B1 (en) | 1997-08-12 | 2002-01-15 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device capable of externally monitoring internal voltage |
| US6486731B2 (en) | 1997-08-12 | 2002-11-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device capable of externally monitoring internal voltage |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0452905B2 (en) | 1992-08-25 |
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