JPS603714B2 - variable length shift register - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a variable length shift register in which the number of bits can be changed arbitrarily.

Such variable length shift registers are increasingly needed in the field of data processing technology.

For example, in a facsimile system, image information is handled line by line, but if the number of bits of image information per line is changed, a shift register and a variable length shift register are required for storing the image information. Conventionally, such variable length shift registers have been constructed by connecting several fixed length shift registers in series and selecting an output point.

To explain an example in FIG. 1, 11, 12, 13,
1 4 are 160 bits, 160 bits, 704 bits respectively
This is a 320-bit shift register, which are connected in series. Input data is input to the shift register 1 at the beginning, and this input data is shifted one bit at a time toward the output end of the shift register 14 at the rear end every time a clock arrives. The gate circuit 15 switches each shift register 11, 12, 13 according to the bit number switching signal.
, 14 is selected. The output of this gate circuit 15 becomes the output of the variable length shift register. In this example, by selecting the gate circuit 15, the number of bits in the variable length shift register can be switched between 160 pits, 320 bits, 1024 bits, and 1344 bits. As is clear from the above explanation,
In the conventional configuration, the number of bits can be changed in stages, but 1
It is practically impossible to change continuously bit by bit.

Further, the number of bits obtained is determined by the number of bits of the shift register to be combined, and cannot be easily changed.
Moreover, commercially available shift registers are limited to a few types of bit numbers, and it is difficult to obtain an arbitrary number of bits. The present invention was made in view of the above-mentioned problems, and its purpose is to provide a variable length shift register in which the number of bits can be arbitrarily changed in units of one bit.

Therefore, the characteristics of the variable length shift register of this invention are as follows.
The random access memory IJ' is configured by combining a variable N-ary counter as an address counter. below,
The invention will now be described in detail with reference to the accompanying drawings. FIG. 2 is a block diagram showing the basic configuration of a variable length shift register according to the present invention, and FIG. 3 is a time chart of the same.
In FIG. 2, a random access memory 21 is, for example, a 1.times.M bit randomly accessible semiconductor memory, and includes an address decoder.

22 is a variable N-ary counter, the modulo of which, ie, N (<M), is arbitrarily set by the N control signal.

This counter 22 counts clock pulses (see FIG. 3) that are synchronized with input data to the memory 21, and the counted value is supplied to the memory 21 as an address signal. A timing generation circuit 23 generates a read/write timing signal (see FIG. 3) based on the clock pulse and supplies it to the memory 21. Next, the operation will be explained with reference to FIG.

When the count value of the counter 22 is (N-1) and the first clock pulse is counted, the counter 22 is cleared and the address (0) of the memory 21 is designated. Since the read/write timing signal output from the timing generation circuit 23 is at the "0" level immediately after the clock pulse, the contents of the address (0) of the memory 21 are first read out and sent out as output data, and then read/written. When the input timing signal rises to the "1" level n, the input data do is written to the address (0) of the memory 21. Similar operations are repeated each time a clock pulse arrives. When the (N+1)th clock pulse arrives, the counter 22 is cleared, the address (0) of the memory 21 is selected, its contents, that is, the data are also retrieved, and then the input data dN is written. When the (N+2)th clock pulse arrives, data d, is read from address (1) of the memory 21, and new input data dN+, is input to the address (1).
1). In this way, this variable length shift register functions as an N-bit serial input/serial output shift register, and the number of bits can be changed arbitrarily by changing the modulo N of the variable N-shaped counter 22.

Note that the memory 21 is not limited to the 1×M bit configuration;
It goes without saying that a configuration of M bits (x bits x M addresses) may also be used.

As described above, according to the present invention, it is possible to realize a variable length shift register in which the number of bits can be changed arbitrarily. The effect is significant.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an example of a conventional variable length shift register, Fig. 2 is a block diagram showing the basic configuration of a variable length shift register according to the present invention, and Fig. 3 is a variable length shift register shown in Fig. 2. FIG. 2 is a time chart for explaining the operation of FIG. 21...Random access memory, 22...Variable N
Advance counter, 23...timing generation circuit. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. A random access memory, a variable N-ary counter that counts clock pulses synchronized with the input data of the memory, and a circuit that generates a read/write timing signal for the memory in synchronization with the clock, and /
A variable length shift register configured to read the contents of an address corresponding to the count value of the counter of the memory in accordance with a write timing signal, and then write the input data to the address.