JPS6073766A - Inter-cpu information exchange device - Google Patents

Abstract

PURPOSE:To attain efficient information exchange between CPUs by writing information in a two-port memory of a receiving side CPU by the originating side CPU and also writing its header record in the special address area of the two-port memory. CONSTITUTION:First, a CPU1 at the originating side writes a information data 5a except a header record in the area 6a of a two-port memory 6, then writes the header record 5b in the area 6b. A CPU2 at the receiving side is provided with an interrupt generation circuit 9 which gives an interrupt signal INT to a processor in the CPU2 after receiving a detection signal of an address decoder 8 which detects that the header record storage area 6b of the two-port memory 6 is accessed from the side of a system bus 3. Therefore, when the CPU1 writes the header record 5b in the area 6b, the interrupt signal INT automatically occurs and the CPU2, upon receiving the signal, fetches information 5a and 5b in the two-port memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information exchange device for exchanging information between OPUs in a multi-OPU system in which a plurality of opties (central processing units) are connected via a common system bus.

Several methods are conventionally known as means for exchanging information using 0PUISQ in a multi-OPU system. The concepts of eight typical conventional methods are illustrated in FIGS. 1A, 1B, and 1O.

9A shows that 0PTT/ on the sending side writes data j to a predetermined area of the system memory connected to system bus 3, and 0PUJ on the receiving side retrieves data S by scanning this area. This is a method that involves In this method, seven specific lags are used for sending and receiving data, so this is called a flag scanning method.

In the above flag scanning method, the receiving side CPU, 2
A major drawback is the use of the system bus 3 to handle the system data session that scanned the flag. If this usage #I4 degree is high, the efficiency of the entire system will be significantly reduced.

FIG. 2B shows a method in which two memory ports in the CPUJ on the receiving side are used as the information transmission area.

2 boat memory B is accessed directly from the OPU and the internal processor of 2 without going through the system bus 3.

It is accessed via the system bus 3 from other OPUs. As with the previous method, 7 lags are used for data exchange, and the data written by OPU/ to 2-board memory B is
is scanned and imported by 0PU2 through internal processing.

This method is called a 2-boat memory flag scanning method.

The above-mentioned two-boat memory flag scanning method is superior to the previous method in that it does not use 0PU2 or system bus 3t for data reception. However, these two methods have the same thing in common.

Since the OPU λ on the receiving side detects the data S to be received by constantly scanning the upper 1 flag, much of the capability of the OPU 2 is depleted due to this scanning process.

Therefore, there is a problem that the ability of 0A U2 cannot be fully utilized for other processing.

In the same figure (0), after OPU/ commits data j to 2-vote memory 4 in 0PU2, a specific device 10 register 7
In this method, an interrupt signal INT is given to 0PU2 by accessing the 0PU2. In response to this interrupt signal NT, 0PU2 takes in data j. This method is called an interrupt method.

In the above-mentioned interrupt method, in addition to the process of setting data in memory B, the process of generating an interrupt signal is added to the OPU/ on the originating side, so the processing efficiency decreases accordingly. Further, an interrupt circuit (register 7) is required on either the transmitting side or the receiving side OPH.

This invention was made in view of the nine conventional problems mentioned above, and its purpose is to improve the CPU speed in a multi-OPU system.
It is an object of the present invention to provide an information exchange device in which both the transmitting side and the receiving side can efficiently process the exchange of data between U's.

In order to achieve the above object, the present invention provides O
The PU writes information data to the 2-boat memory in the receiving side CPU, and then writes the header record of the information to a predetermined address area of the 2-boat memory, and the receiving side OPH writes the information data to the above specified address. The present invention is characterized in that it includes a circuit that detects that there is an operation to write a header record and generates an interrupt signal.

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows an information exchange device according to the invention. Here, 2-board memory 6 in OPU 2 on the receiving side
is used for data exchange. The two-board memory j includes an area 6a for storing substantial information data excluding header records among the information to be transmitted, and a header record storage area 6 at a specific address for storing the header records.
b is assigned. The header record is a heading portion of transmission information that includes information such as the number of information data and the station number of the originating OPU.

When transmitting information, OPU/ on the transmitting side first writes information data ja excluding the hander record into area jaK1j of 2-boat memory B, and then writes header record jb to area ≦b of 2-boat memory B.

OPUλ on the receiving side has 2-board memory 6 to 7 L/
An interrupt generation circuit 9 is provided which receives a detection signal from an address decoder for detecting that the storage area 6b is accessed from the system bus 3 and supplies an interrupt signal INT to the processor in the OPU 2. ing.

As a friend, OPU/ writes a header record j to area ab.
1), a 5-interrupt signal NT is automatically generated, and in response to this, the OPU inputs information ja and jb in the 2-board memory 6.

In this device, the memory map seen from the system bus 31iIII is shown in FIG. As shown in the figure, there are two boat memories 4 in 0PUJ in a series of memory spaces, and this part is divided into the above-mentioned information data storage area 6a and header record storage area 6b. When an OPU other than OPU 2 on system bus 3 accesses the header record storage area Al), OPU automatically
pUJK interrupt occurs.

As explained above in detail, in the device of the present invention, the receiving gill OP U does not use the system bus for data reception and transmission, and also performs constant data monitoring processing like the aforementioned 7-lag process. There is no need to carry out the data fetching process, and data fetching processing is performed only after receiving one interrupt. In addition, the transmitting OPU simply writes the information to be transmitted into the two-board memory by distinguishing the header record from other information data, and automatically interrupts the receiving OPH without performing any other additional processing. is applied. In other words, both the transmitting side and the receiving side can process data exchange extremely efficiently, thereby improving the performance of the entire system.

[Brief explanation of the drawing]

FIG. 1 (M) CB) (0) is an explanatory diagram of eight typical conventional information exchange systems, FIG. 2 is an explanatory diagram of an information exchange device according to an embodiment of the present invention, and FIG. 2 is a memory map of the device shown in FIG. 2 as seen from the system bus side. /... Sending side 0a ■,, 2... Receiving side OPU, j.
...System bus, ja...information data, jb...
Helladare;l-)”, ≦...2 boat memory, ≦b・
...Header record storage area, l...Address decoder, ? ...Interrupt generation circuit. Figure 2 Figure 3

Claims (1)

[Claims] (1) In the case where information is exchanged between opties using two-board memory, the receiving side OPH has an information data storage area for storing information data from the sending side OPU, and a header record storage area whose address is specified in advance. , an address decoder that detects when the receiving OPU accesses this header record storage area and outputs a detection signal, and an interrupt generation circuit that provides an interrupt signal to the receiving OPU (based on the detection signal). An information exchange device between OPUs, characterized in that: