JPS6079452A - Address assignment system for module - Google Patents

Abstract

PURPOSE:To realize a flexible address assignment system for modules by providing a holding means for module addresses including individual addresses, common addresses, and group addresses. CONSTITUTION:Plural modules 2a-2g each have plural addresses and are connected to a switch line 3, selection line 4, and data bus 5 common to a bus control part 1. Plural addresses are formed of addresses characteristic to the respective modules as shown by switching 1, addresses common to all the modules as shown by switching 2, and addresses which are common, group by group, as shown by switching N as one example. The respective modules 2a-2g receive addresses specified by their incorporated reception parts selectively under the control of the bus control part 1. Consequently, all the modules are accessed at a time, module by module, or group by group to improve the operativity.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to an addressing method for each module in a system having a plurality of monoles.

(Prior Art) Generally, in a system having a plurality of modules and transferring data between the modules via a common path, each module has an address for data transfer. Conventionally, there is a method of assigning addresses by assigning different individual numbers to each module. This method had the disadvantage that in order to pass the same data to a plurality of monoyls, each module number was set in sequence and the data was passed sequentially with one module as a unit, resulting in a long data transfer time.

One way to solve the above drawback is to assign a common number to multiple modules as a group, select each module at the same time using the common number, and pass data with the same content at the same time, but this method is The combination of modules and module groups was fixed, and the system had the disadvantage of lacking flexibility.

(Object of the Invention) The present invention has been made in view of the above points, and its object is to provide a flexible and improved monoyl addressing system.

(Structure of the Invention) In order to achieve the above object, the present invention includes a module address holding means for holding a plurality of module addresses in each monoyl, and a module address holding means that selectively outputs one of the plurality of module addresses to address the own monoyl. The monophonic address is designated singly or as a group by one of the plurality of monol addresses, which will be described in detail below.

(Example) FIG. 1 shows a diagram of the module according to the present invention,
FIG. 2 shows a system configuration diagram. In FIGS. 1 and 2, 1 is a bus control unit, and 2, 2a, 2b.

...2g is the module, 3 is the switching line, 4 is the selection line, 5
is a data bus, 6 is a data receiving section, 7 is a comparator, 8 is a multiplexer, and 9 is a module address holding means, which may be fixed by a short line or semi-fixed by a Dizzo switch, or may be set externally by a program. It's okay.

In the system configured as shown in FIG. 2, the signal control section 1 determines which module is given permission to use the various signal lines 3, 4.5. Each module 2a in FIG.
The numbers in 2b, . . . 2g indicate the address of the module, and the highest digits 1, 2, . ...7
indicates one state on the switching line 3 (abbreviated as switching 1), followed by the numbers 1, 1 . ...1 indicates another state on the switching line 3 (abbreviated as switching 2), and the lowest number 3゛, 3,
4, 4, 5, 5.

5 indicates another state on the switching line 3 (abbreviated as switching N). Each monoyl 2a, 2b shown in FIG.

...2g details are shown in Figure 1. The address of the module is determined by selecting one of the module address holding means using an externally applied signal line 3 and a multiplexer 8, as shown in FIG. Now, taking module 2g as an example, if it is set to the switching 1 state by the switching line 3, the module address will be the individual address "7", and if it is set to the switching 2 state, it will be the address "1"' common to all seven modules. Therefore, if the switching state is N, the group address of module group 2e+2f+2g is l15.
becomes. Other monoyl addresses will be easily understood from the above explanation and FIG. 2.

Furthermore, in order to select the module having the address determined in the above manner, the comparator 7 is externally connected via the selection line 4.
comparator 7 by inputting the address of the monoyl to
When the two inputs (module address signals) match, the module is selected, and the data on the data bus 5 is latched, for example, in the data receiving section 6.

In the above explanation, the module address switching instruction is generally given by an external path control unit via the switching line 3 according to the bus status and communication status, but it may also be specified by the sending mono, or it can be specified by a predetermined condition. It may also be specified internally.

(Effects of the Invention) As described above in detail, the present invention has a module address holding means including individual addresses, common addresses, and group addresses, and selects one of these addresses as necessary to store the own module. By using addresses, each module can be specified as an individual address, a common address, or a group address. Depending on the system status and the purpose of data transfer, the same module can be accessed individually or as a member of a group. This has the advantage of increasing the flexibility of the system since it can be accessed as a member of another group.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of monoyl, and FIG. 2 is a system configuration diagram. l... Lotus system ml part, 212 a 1-2g...
Module, 3... Switching line, 4... Selection line, 5...
・Data bus, 6...Data receiving section, 7...Comparator,
8...Multiplexer, 9...Mononyl address holding means. Patent applicant Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] In a module addressing method in a system having a plurality of monoyls, each of the plurality of modules has a monoyl address holding means for holding a plurality of module addresses, and a monoyl address holding means for selectively outputting one of the plurality of module addresses. 1. A method for assigning addresses to a module, characterized in that the address of the module is designated by one of the plurality of module addresses singly or as a group, comprising means for selecting the address of the module itself.