JPS61131297A - Mask ROM - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a mask ROM (Mask Read O
nlyMemory), and is particularly used for static type CMOS mask ROM.

[Technical background of the invention and its problems]

In general, mask ROMs are roughly classified into asynchronous (static) type and synchronous (dynamic) type depending on their circuit type. In other words, the asynchronous method accepts input signals at any time and outputs data without requiring an external control signal. The synchronous method receives signals and outputs data.

The asynchronous method described above is easier to use than the synchronous method because it does not require an external control signal and there is no need to consider its timing.

FIG. 9 shows a circuit configuration of a conventionally used asynchronous type mask ROM. FIG. 10 shows an example of a part of the pattern configuration. In FIG. 9, TD is a depletion type N-channel type load MOS transistor, TINITN21TN31... is an enhancement type N-channel type MO8 transistor as a memory cell, and 11 is the transistor T to which the input signal IN is supplied.
A decoder that selectively drives n1+TN2+TN3+..., 12 is the MO8 transistor TN 1 r T
N2 + TN 3 H... is a sense amplifier that amplifies the potential of a data line commonly connected to obtain read data OUT.

In the above configuration, data programming is performed using MOS transistors TN 1* TN 2+ TN
3 Depending on whether or not *... is formed. In FIG. 9, the transistor T2 indicated by a broken line is not formed.

Next, the operation will be explained. When the input signal IN is supplied to the decoder 11, the signal lines P 1 r P2 rp3 .
One of them is selected and becomes high (“H”) level,
All others are at low ("L") level. One MOS as a memory cell is connected by the above "H" level signal line.
A transistor is selected. Now, assuming that MOS transistor TN1 is selected, this transistor T
N1 is turned on and the potential of the data line Dl decreases. By amplifying this potential drop on the data line with the sense amplifier 12, the read data OUT (“0”)
get.

On the other hand, if MOS transistor 2 (this MOS transistor T2 is not formed) is selected, the data a D 1 is held at a potential that has been converted by the load MO8 transistor TD, so this potential is amplified by the sense amplifier f12. The read data OUT ('1'') is obtained.

When programming the above data, whether or not to form the MOS transistors TN 1 e TN 21 TN3 + . . . is determined by the sources of the MOS transistors as shown in FIG.

Determined depending on whether or not to form a drain region. 1st
0, parts corresponding to the circuits in FIG. 9 are given the same reference numerals, and the data lines D110. , . . . are formed of aluminum layers, and the signal lines Pl + Px r
P3+... is formed by a polysilicon layer.

Note that 13 is a diffusion region, and 141 to 144 are contact portions between the aluminum layer and the diffusion layer.

However, in the above configuration, a DC through current flows even during standby, so there is a drawback that current consumption increases.

As an asynchronous type mask ROM that can eliminate these drawbacks and reduce current consumption, the
There is an MO8 type circuit. This circuit replaces the load MOS transistor TD in FIG. 9 with signal lines P, %
It is provided by connecting P-channel type MOS transistors TP1 to TPn in series, whose conduction is controlled by the potential of Pn, and an example of the main turn configuration is shown in FIG.

Programming of the above mask ROM is performed using P as a load.
This is done by injecting impurities into the dirt regions of the channel type MO3 transistors 'rp1-Jrpn to achieve desorption, and by forming corresponding N-channel type MOS transistors 'rN1-+N for driving.

In the above configuration, the input signal I is input to the decoder 11.
N is supplied, signal line P1 is at “H” level, and all others are @
When the level becomes L#, the MOS transistor TP1 is turned off, TNl is turned on, and the potential of the data line Dl is lowered.

By amplifying the potential of this data line Dl by a sense amplifier 7°12), read data OUT (“0”) is obtained. On the other hand, signal line P2 is at °H" level, and all others are at "L" level.
``If the level is reached, MOS Transosmas P2
Since it is a depletion type, it is in the on state, and since the MOS transistor N2 is not formed, the data line DI is turned on from the power supply VDD via the MOS transistors TP1 to TPn. Therefore, this potential is amplified by the sense amplifiers f12-10 to obtain the readout output OUT ("1").

With this CMOS configuration, a through current flows only in a transient state, so no current flows during standby, and current consumption can be significantly reduced. However, since the structure is complementary, the area occupied by the 2'1' tangents is large. In addition, since multiple stages of P-channel MOS transistors are connected in series as a load, the current drive capability is significantly reduced, and the time taken to charge the data line Dl to the power supply VDD level is longer than the time it takes to discharge the data line Dl to the ground (Vs s ) level. The downside is that it takes a very long time to upload and slows down access time.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide an excellent mask ROM in which no standby current flows, the area occupied by the pattern can be reduced, and the delay in access time is small.

[Summary of the Invention] That is, in order to achieve the above object, the present invention deprograms data by connecting the source of a MOS transistor as a memory cell to the power supply VDD or VSB. Since it does not use a load transistor, the current consumption during standby can be reduced, and since the circuit is not configured in a complementary type, the A? The area occupied by the turn can also be reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. The bus lines B1yB2+ in FIG.
) Run master group Trij (1""J 12 + "'
The drains of r mXj==J l 2+ ``','') are connected for each row. Above MO8) Run master group T
The sources of rij are respectively connected to the power supply VDD or VSB depending on the information to be stored, and the r-ts are connected to signal lines p and -Pn for each column. These signal lines P1 to Pn
is supplied with the output of the decoder (full decoder) 11 to which the input signal IN is supplied, one selected signal line is set to the VDD level, and all others are set to the VSS level.

Further, the bus lines B1+B2*... are provided with level compensation circuits 121, 172 formed by connecting inverter circuits 16□, 162 and a resistor R so as to provide positive feedback.
, . . . are provided respectively, and these level compensation circuits 1
71,172. Output signal 0UT1 rO via...
UT 2 r... is obtained.

Next, the operation in the above configuration will be explained. now,
The signal line Pl is selected by the output of the decoder 11 and VD
Assuming that the D level and the other signal lines P2 to Pn are all at the VB8 level, the MOS transistors Tr11 and Tr21 +-s whose darts are connected to the signal line Pl are
While Trml is in the on state, all MOS transistors in other columns are in the off state.

Therefore, bus line B is at V811 level, and B2 is at VD
DL/ Becomes a bell. At this time, bus line B2 C+
To be more precise, the potential is lowered by the threshold voltage Vt hN of the N-channel MOS transistor Tr21, and becomes "vDD".
−VthN”=13−. At this level, the through current of the next stage CMO8r-to is increased, so the level is set by the level compensation circuit 172. Then, the output signal OUT of the VSS level from the level compensation circuit 171 is 17
2, an output signal OUT at the VDD level is obtained.

On the other hand, when the signal line Pz is selected by the decoder 1, the MOS transistor r12+Tr 22 is not turned on, the bus line B1 is at the VDD level, and the bus line B2 is at the MOS level. The above MOS transistor Tr12
The drop in the level of the bus line Bl due to the threshold voltage VthN is compensated by the level compensation circuit 17□, and the output signal OUT is at the VDD level, and the output signal OUT
s level tonal. Hereinafter, in the same manner, memory cell array 1
The stored information is read from 5.

FIG. 2 shows another example of the structure of the level compensation circuit, in which the level compensation circuits 171 and 1 in FIG.
72+... is the power supply vDD # Vl! 8, while the level of pass line 1← decreases by the threshold tolerance voltage VthN of the MOS transistor as a memory cell only on the power supply VDD side. Level compensation is performed only on the VDD side. That is, the input terminal of an inverter circuit 1 (10) is connected to the bus line B, and a resistor R1 (10 and a P-channel MOS) run master T is connected between the input terminal of the inverter circuit 1 (10) and the power supply VDD.
r1oo are connected in series. Then, by the output of the inverter circuit lθθ, the run master Tr1 (j5MO8) is activated.
This inverter circuit 1 (1
Obtain the output signal OUT from 0. According to the configuration as shown in FIG. 1, the access time can be faster than that shown in FIG. FIG. 3 shows cases in which the level compensation circuits 171*172r, etc. in the circuit shown in FIG. The graph collectively shows the temporal changes in the charging potential of the bus line (dotted chain line). Here, tl is the charging start time, and tz is the discharging start time. Note that the level compensation circuits 171, 17□ in FIG.

. . . and the resistor R of the level compensation circuit 17 in FIG.
The resistance value of R1 (10) may be OΩ, and this resistance value may be set according to the circuit characteristics.

According to such a configuration, since no element is in an on state during standby, the constant current consumption during standby is about the same as leakage current, and can be suppressed to an extremely low value. Furthermore, unlike the circuit shown in FIG. 11, there is no need to provide a multi-stage MOS (MOS) run master as a load. There is no increase in turn area. Furthermore, since it is an asynchronous method, it does not require a complicated control circuit, can be easily integrated into an LSI, and can be applied to various systems.

4 to 7 respectively show examples of pattern configurations of memory cells in the circuit shown in FIG. 1. FIG. 4 shows two cases in which the source of a MOS transistor r41 as a memory cell is connected to the power supply vDD or VSS (programming) using a diffusion layer.
It consists of 4 turns. The source of the MOS run master Tr12 in FIG.
The source of the S7 source transistor Tr15 is connected to the power supply VSB line via the diffusion layer 182 and the contact portion 192. Here, a region 2o1 is surrounded by a broken line without forming a diffusion layer 181 and 182.

20, if a diffusion layer is formed by ion implantation, for example,
The source of MOS transistor Tr12 is connected to power supply VI! 8
The source of Tr13 can be connected to the power supply vDD line, respectively. Note that the power supply VDD line +Vl1g line and the bus line Bl are each formed of an aluminum layer, and the signal lines P1 to P4 are formed of a polysilicon layer.

FIG. 5 shows another example of the pattern configuration.
In order to further increase the density of the pattern shown in the figure, contact portions "1e192" are formed diagonally with respect to each line.

In the figure, parts corresponding to those in FIG. 4 are given the same reference numerals.

-17= FIG. 6 shows yet another example of pattern configuration, in which programming is performed depending on whether or not a contact portion is formed. In other words, the source region of the MOS transistor Tr12 is connected to the power supply V by the diffusion layer 211.
It extends below the DD and VEIS lines, and is connected to the VDD line by a contact portion 191. Further, the source region of the Mos transistor mass r13 is extended to below the power supply VDD line and the VSS line by the diffusion layer 212, and the source region of the Mos transistor mass r13 is extended to below the power supply VDD line and the VSS line by the contact portion 192.
Connected to 8 lines. In addition, the contact part 19□,
Area 221.222FC surrounded by broken lines without 19□
If the contact part is formed, the MOS transistor Tr1
The source of Tr 2 is connected to the power supply vss line, and the source of Tr 13 is connected to the power supply VDD line.

FIG. 7 shows another pattern configuration example, in which the power supply VD
Programming is performed using an aluminum layer forming the D line and the power supply VSg line. The source of the MOS transistor Tr12 in FIG.
It is connected to the power supply VDD line through the diffusion layer 2, the contact portion 231, and the aluminum layer 241, respectively. Further, the source of the M)S transistor Tr13 is connected to the diffusion layer 212° contact portion 234 and the aluminum layer 242.
are connected to the power supply VS8 line through respectively. Here, if we form an aluminum layer in the region 251 and 252 shown by the broken line without forming the aluminum Wl"l r 2", the MOS
Transosmas R12 source is power supply V81! The source of Tr13 can be connected to the power supply VDD line.

Note that the pattern configuration is not limited to the above-mentioned one, but can be modified in various ways, and may be a pattern using multilayer wiring.

FIG. 8 shows another embodiment of the present invention. In the circuit of FIG. 1, the bus lines B1pB2+...
level compensation circuit 171.

172,... and output signal on'r 1 x
0UT2/... are obtained in parallel, but the information of only a predetermined memory cell is read out.

In the figure, the same components as those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. That is, the lot lines Blt B2 t B3+ . The select circuit 26 has one end connected to the bus lines B1, B2 . B3. ...
N-channel type select MOS transistors Ts1+Ts2+Ts++・ whose other ends are connected to
..., these MOS transistors Ts1+T
The darts of B 2 *TS3+"' are respectively connected to select lines LH* B2 , B3 y . . . to which select signals S1 r B21 Ss+ . . . are supplied.

The above select signal sl, 52Is3. . . ., only the selected item is at VDD level, and all others are at VBS level. Therefore, the select signal Sl.

M for selection selected by S2+83+...
Only the OS transistor is turned on. As a result, a bus line is selected, and the information read from the memory cell array 15 is output to the selected bus line via the level compensation circuit 17.

According to such a configuration, only information stored in a predetermined memory cell (MOS transistor) Trlj in the memory cell array 15 can be read out.

In each of the above embodiments, the polarity of the MOS transistor as a memory cell is N-channel type, but it goes without saying that it may be P-channel type.

〔Effect of the invention〕

As explained above, according to the present invention, the standby current does not flow, the area occupied by the main turn can be reduced, and the access time delay is also reduced.
is obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the structure of a mask ROM according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing another example of the structure of the level compensation circuit in the circuit of FIG. 1, and FIG. 1
Figures 4 to 7 are diagrams for explaining the operation of the level compensation circuit in the circuit of Figure 2 and Figures 4 to 7 respectively explain the /'e turn configuration and programming method of the memory cell in the circuit of Figure 1. FIG. 8 is a circuit diagram for explaining another embodiment of the present invention, and FIG. 9 and FIG. 12 are diagrams for explaining a conventional mask ROM, respectively. IN...Input signal, 11...Decoder (full decoder), Tru~Tr...MOS transistor group,
P□~Pn...Signal line, B11B2#...Bus line, 171.172. ...Level compensation circuit, VDD#Vllll+...power supply, 26...select circuit. Applicant's agent Patent attorney Takehiko Suzue
Ward ○ j CL CL CL
CL Figure 11 VDD JP-A IIUGI-131297 (10) Figure 12

Claims (15)

[Claims] (1) A full decoder to which an input signal is supplied, a plurality of signal lines to which the output of this full decoder is supplied, and memory cells arranged in a matrix and having gates connected to the plurality of signal lines in each column. a plurality of bus lines to which one end of the MOS transistor groups is connected for each row, and a level compensation circuit for compensating the potentials of these bus lines to obtain an output signal. A mask ROM characterized in that data is programmed depending on whether the other end of the group is connected to one or the other of a power supply. (2) The full decoder sets only the selected signal line to one level of the power supply, and sets all other signal lines to the other level of the power supply. mask ROM. (3) The level compensation circuit includes a first inverter circuit whose input terminal is connected to the bus line, a second inverter circuit whose input terminal is connected to the output terminal of the first inverter circuit, and a second inverter circuit whose input terminal is connected to the output terminal of the first inverter circuit. 2 the output end of the inverter circuit and the first
and a resistor connected between the input terminals of the inverter circuit, and the mask R according to claim 1, wherein the mask R receives an output signal from the output terminal of the first inverter circuit.
OM. (4) The level compensation circuit includes an inverter circuit whose input end is connected to the bus line, and an MO whose one end is connected to one of the power supplies and whose conduction is controlled by the output of the inverter circuit.
The MOS transistor includes an M transistor as the memory cell, and a resistor connected between the other end of the MOS transistor and an input terminal of the inverter circuit.
2. The mask ROM according to claim 1, wherein the OS transistor is of a conductivity type opposite to that of the OS transistor, and an output signal is obtained from an output terminal of the inverter circuit. (5) The mask ROM according to claim 1, wherein the data is programmed using a diffusion layer. (6) The mask ROM according to claim 1, wherein the data is programmed depending on whether contact is made or not. (7) The mask ROM according to claim 1, wherein the data is programmed using a metal layer. (8) A full decoder to which an input signal is supplied, a plurality of signal lines to which the output of this full decoder is supplied, and memory cells arranged in a matrix and having gates connected to the plurality of signal lines in each column. a group of MOS transistors, a plurality of bus lines to which one end of the MOS transistor groups is connected for each row, a select circuit that selects one of the plurality of bus lines based on a select signal, and a select circuit that selects one of the plurality of bus lines based on a select signal; and a level compensation circuit for compensating the potential of the bus line selected by the circuit to obtain an output signal from the selected memory cell, and the other end of the MOS transistor group is connected to one side of the power supply or the other side of the power supply. A mask ROM characterized in that data can be programmed depending on whether the data is programmed or not. (9) The full decoder sets only the selected signal line to one level of the power supply, and sets all other signal lines to the other level of the power supply. mask ROM. (10) The level compensation circuit includes a first inverter circuit whose input terminal is connected to the bus line, a second inverter circuit whose input terminal is connected to the output terminal of the first inverter circuit, and a second inverter circuit whose input terminal is connected to the output terminal of the first inverter circuit. Claim 8, comprising a resistor connected between the output terminal of the two inverter circuits and the input terminal of the first inverter circuit, and an output signal is obtained from the output terminal of the first inverter circuit. Mask ROM described. (11) The level compensation circuit includes an inverter circuit whose input end is connected to the bus line, and an M whose one end is connected to one of the power supplies and whose conduction is controlled by the output of the inverter circuit.
The MOS transistor includes an OS transistor and a resistor connected between the other end of the MOS transistor and the input terminal of the inverter circuit, the MOS transistor being of a conductivity type opposite to that of the MOS transistor serving as the memory cell, and 9. The mask ROM according to claim 8, wherein an output signal is obtained from an output terminal. (12) The mask ROM according to claim 8, wherein the data is programmed using a diffusion layer. (13) The mask ROM according to claim 8, wherein the data is programmed depending on whether contact is made or not. (14) The mask ROM according to claim 8, wherein the data is programmed using a metal layer. (15) The select circuit is an MO that is provided corresponding to each of the plurality of bus lines and whose conduction is controlled by a select signal.
Claim 8, wherein the MOS transistors are composed of S transistors, one end of which is connected to the bus line, and the other end of which is commonly connected and connected to the input end of the level compensation circuit. Mask ROM.