JPS6116615A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To put a clock and a data signal completely in phase with each other even when a flip-flop which responds to a frequency nearly as high as the frequency of the clock signal is used by providing a delay circuit which cancels the propagation delay time between the toggle signal input and Q output of the flip-flop. CONSTITUTION:The propagation delay; time 11 between the toggle signa input and Q output of the D type flip-flop 3 needs only to be equal to the delay time 14 of the delay circuit 12, so the absolute delay time of the flip-flop 3 needs not be reduced. Therefore, a flip-flop 3 which only responds to the frequency of the clock signal 3 is usable as the flip-flop 3 and, specially, a high-speed flip-flop is not required. When the D type flip-flop 3 and delay circuit 12 are integrated on the same substrate, characteristics of the elements are uniform, so relatively the same delay time is obtained, thereby suppressing the phase shift between the clock signal 7 and data signal 6 even in case of a change in operation environment condition.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase synchronization circuit for synchronizing a reference clock signal and a data signal input later than the reference clock signal.

(Conventional technology) Conventionally, there has been a device of this type as shown in FIG.

In the figure, 3 is a D type flip-flop, 8.9
1 is a toggle signal input terminal and a data signal input terminal, 10 is a data signal output terminal, and 4.5 is a buffer gate.

1 and 2 are data signal inputs, clock signal inputs, and 6.
7 are a data signal and a clock signal respectively outputted via buffer gates 4.5.

Further, FIG. 2 shows the timing of each part of this circuit.

In the figure, 1) is the propagation delay time between the flip-flop 30 toggle signal input terminal 8 and the Q output terminal 10;
is the propagation delay time between the input and output of the buffer gate 4.5.

Next, the operation will be explained.

The clock signal 2 is input to the toggle signal input terminal 8 of the D-type flip-flop 3, and the data signal 1, which is input later than this, is input to the data input terminal 9 of the D-type flip-flop 3. The clock signal output signal is output with a delay of an input-output propagation delay time 13 of the buffer gate 5 with respect to the clock signal input 2. On the other hand, the data output 6 is delayed by the sum of the propagation delay time 1) between the toggle signal input of the D type flip-flop 3 and the Q output and the buffer 1 gate 40 input car output propagation delay time 13 when the clock input 2 is used as a reference. is output.

Here, the input-output propagation delay times 13 of the buffer gates 4 and 5 are considered to be the same. As a result, the data signal output 6 is not perfectly synchronized with respect to the clock signal output, but only by the propagation delay time 1) between the toggle signal input and the Q output of the D-type flip-flop 7. The phase will shift. Therefore, for 20 cycles of the clock signal, the propagation delay time 1) between the toggle signal input of the D-type flip-flop 30 and the Q output must be negligible. Flops were required to be extremely fast.

For example, if the frequency of the clock signal 2 is 100 MHz, the D type flip-flop 3 should originally have a frequency of 100 MHz.
It should be fine to use something that responds to MHz, but in order to suppress the propagation delay time 1) to a negligible level with respect to the period (10 nS) of the clock signal 2, a D-type flip-flop 3 with a frequency response one order of magnitude higher (IGHz) is used. had to use.

[Summary of the invention]

The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and by providing a delay circuit that cancels out the propagation delay time between the toggle signal input and the Q output of the flip-flop, the clock signal can be reduced. It is an object of the present invention to provide a phase synchronization circuit that can synchronize the phases of a clock signal and a data signal more completely even when using a flip-flop that responds to a frequency similar to that of the present invention.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows the configuration of a phase locked circuit according to an embodiment of the present invention, and in the figure, the same reference numerals as in FIG. 1 indicate the same parts. The circuit of this embodiment has a delay circuit 12 added to the conventional circuit of 1W, and this delay circuit 12 is provided between the toggle input terminal 8 of the D-type flip-flop 3 and the input of the buffer gate 5. , has a delay time equal to the propagation delay time between the toggle input terminal 8 and the Q output 1o of the D-type flimbu flop 3.

Further, FIG. 4 shows timing waveforms of various parts of the circuit of FIG. 3, and in the figure, 14 is the delay time of the output clock signal 7 by the delay circuit 12.

Here, a specific example of the configuration of the apparatus of this embodiment is shown in FIG.

Here, the present invention is particularly effective when the frequency of the clock signal 2 is high, so it is possible to use ECL (HIIIitter Co., Ltd.), which is the fastest among the currently commonly used logic circuits.
Logic (upled Logic) circuit is used as a specific example.

FIG. 5 shows the D-type flip-flop 3 and delay circuit 12 shown in FIG. 3 developed into a concrete circuit.

This D-type flip-flop 3 is based on a standard series gate master-slave system, and the mating type is also commonly used at present. On the other hand, delay circuit 1
2 is constructed in the same series gate circuit format as the D-type flip-flop 3 so that its propagation delay time 14 is the same as the propagation delay time 1) between the toggle input 8 and the output 10 of the D-type flip-flop 30. It is.

In FIG. 5, 15 is a power supply (Vcc) supply terminal, and 9 is data (D) of the D type flip-flop 3.

5) Input terminal, 10 is its data output (Q, Q) terminal, 8 is toggle (T, T) input terminal, 16 is delay circuit 12
These are the output (TD, TD) terminals. Further, 23 is a constant current source, 24 is a resistor, 21.22 is a first and second differential transistor, and 17.20 is a third transistor whose common emitter is connected to the collector of the transistor 21. The collectors of the fourth differential transistors 18 and 18 are connected to the output terminal 16, and inverted and non-inverted delayed signals are output, respectively.

The bases of transistors 17 and 19 are biased to the "H" level, and the bases of the transistors 18 and 20 are biased to the "L" level. The clock signal 8 input to the bases of the transistors 21 and 22 selectively turns on either the transistors 21 or 22, and selects either the transistors 17 and 20 or the combination of transistors 18 and 19. The state of the output 16 is determined by this.

Note that the above D type flip-flop 3. Delay circuit 12
The series gate circuit format means that the transistors 17 to 20 and the transistors 21 and 22 are connected in series.

Next, the effects will be explained.

In this embodiment, the propagation delay time 1) between the toggle signal input of the D-type flip-flop 3 and the Q output, and the delay circuit 1
Since it is sufficient that the delay time 14 in the flip-flop 2 has the same value, there is no need to reduce the absolute delay time of the flip-flop 3. Therefore, a flip-flop 3 that responds to the frequency of the clock signal 2 can be used, and a particularly high-speed flip-flop is not required.
In the case of a flip-flop of the rCoup'ledLogic type, the effect of reducing power consumption is significant.

Furthermore, when the D-type flip-flop 3 and the delay circuit 12 are integrated on the same substrate, the characteristics of the elements are the same, so relatively the same delay time can be obtained. etc.), the effect is that the phase shift between the clock signal 7 and the data signal 6 can be suppressed.

〔Effect of the invention〕

As described above, according to the phase locked circuit according to the present invention,
Since we have provided a delay circuit that cancels out the propagation delay time between the toggle signal input and the Q output of the flip-flop, when using a flip-flop that responds to approximately the same frequency as the clock signal, the clock signal and data This has the effect of being able to synchronize the phase with the signal more completely.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a conventional phase-locked circuit, FIG. 2 is a waveform diagram of each part of FIG. 1, FIG. 3 is a circuit diagram of a phase-locked circuit according to an embodiment of the present invention, and FIG. FIG. 5 is a diagram showing a specific configuration of the circuit shown in FIG. 3. FIG. 3...D type flip-flop, 12...Delay circuit, 21.22...1st. a second differential transistor;
17.20...3rd. fourth differential transistor, 18
．． 19...5th. Sixth differential transistor, 23...
・Constant current source, 24...resistance.

Claims (3)

[Claims] (1) A circuit for synchronizing a reference clock signal with a data signal that is input with a delay with respect to the reference clock signal, in which the reference clock signal is input to the toggle signal input, and the data signal is input to the data signal input. and a delay circuit that delays the reference clock signal by a time equal to the propagation delay time between the toggle signal input and the data output of the flip-flop. (2) The phase synchronized circuit according to claim 1, wherein the delay circuit is of the same series gate type as the flip-flop. (3) Claim 1, characterized in that the flip-flop and the delay circuit are formed on the same semiconductor substrate.
The phase locked circuit according to item 1 or 2.