JPS61160166A - Deciding device for storage error - Google Patents

Abstract

PURPOSE:To restrict a trouble position by detecting coincidence among a register means, an error detecting means and a processor number and registering the coincidence in another register means. CONSTITUTION:The output of the 1st register means 2 is inputted to the error detecting means to detect the error. An error detecting signal is inputted to a register control means 4 and the 2nd register means 5. In this case, the means 4 controls so that the initially generated error contents are held in the means 5. The error contents stored in the means 5 and the output of the means 3 are inputted to the 1st coincidence detecting means 6 to detect whether the error contents are the same as that generated and registered in the 1st time or not. On the other hand, the 2nd coincidence detecting means 7 detects whether the processor number at that time is the same as that stored in the means 5 or not. If the contents of both the errors are the same and the processor numbers are different each other, the status is registered in the 3rd register means 8. When the data are registered in the means 8, it is decided that the failure is generated after a selecting means 1.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a storage error determination device connected to a plurality of processors, and more particularly to a circuit configuration for distinguishing between a fault inside a storage device and a fault in each processor.

(Prior Art) Conventionally, this type of storage error determination device has adopted a configuration as shown in FIG. 2, for example. In FIG. 2, the outputs of interface signal lines 11.2 of processors 0 and 1 (not shown) are connected to error detection means S, and the error contents detected by error detection means 3 are stored in second register means. 5. At this time, the processor number on the signal line 13 is stored in the second register means 5. The processor number corresponding to the error content is held in the second register means 5.

The output of the error detection means 3 is input to the register control means 4, which controls whether the second register means 6 is in the set state or in the hold state depending on the past error detection state. The output of the second register means 6 controlled in this way is sent to signal lines 21 and 22. These outputs register the contents of a single error occurrence, such as the first error content or the last error content.

(Problem to be Solved by the Invention) Therefore, it is clear that an error occurs when accessing from processor 0 or processor 1, but it is not clear whether an error also occurs when accessing from either processor 0 or processor 1. can be known within a certain short period of time. Therefore, when performing dynamic configuration control or maintenance, it is difficult to isolate and determine whether the failure occurred before the selection means 1 or after the selection means 1. There was a point.

An object of the present invention is to eliminate the above-mentioned drawbacks by comparing and registering the output of the second register means in which the error contents are registered with the error contents that have occurred since then, and to It is an object of the present invention to provide a storage error determination device configured to be able to easily distinguish between a previous failure and a failure subsequent to the selection means 1.

(Means for Solving the Problems) A storage error determination device according to the present invention includes a selection means, a first
register means, error detection means, second register means, register control means, first coincidence detection means,
The device is configured to include second coincidence detection means and third register means.

The selection means is connected to the plurality of processors and is for selecting one of the plurality of processors.

The first register means is for temporarily storing the output of the selection means.

The error detection means is for detecting an error included in the data stored in the first register means.

The second register means is for storing the output of the error detection means and a processor number given from the outside as a set.

The register control means is for controlling the contents of the second register means according to past error conditions detected by the error detection means.

The coincidence detection means of Ml is for determining whether the content of the second register means is the content of the error that occurred and was registered for the first time, based on the output of the second register means and the output of the error detection means. belongs to.

The second coincidence detection means is for determining whether the processor number is the program number stored in the second register means.

The third register means is for determining, based on the outputs of the first and second coincidence detecting means and the output of the register control means, whether or not the error content has occurred after the selection means. be.

(Example) Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a storage error determination device according to the present invention. In Figure 81, processor 0
a selection means 1 connected to the interface signal line 11 of the processor 1 and an interface signal line 12 of the processor 1; a first register means 2 connected to the selection means 1; and an error detection device connected to the first register means 2. means 3, register control means 4 connected to the error detection means 3, second register means 6 connected to the error detection means 3, the register control means 4 and the signal line 13 representing the processor number; means 5 as well as second register means 5
a first coincidence detection means 6 connected to the processor number output signal line 1s and a second coincidence detection means 7 connected to the second register means 5, a register control means 4 and the first and second It consists of a third register means 8 connected to the coincidence detecting means 6 and 7, an AND gate 9, and an inverter 10.

In FIG. 1, interface signal lines 11 and 12 of processor 0 or processor 1 are input to selection means 1, and a predetermined interface signal is selected and input, and is held in first register means 2. The output of the first register means 2 is input to the error detection means 5 to detect errors.

The error detection signal output from the error detection means 3 is inputted to the register control means 4 and the second register means SK. It is now assumed that the register control means 4 performs control so that the content of the first error that occurs is held in the second register means 6. If error detection has never been performed, the contents of the error detected by the error detection means 3 and sent to the second register means 5 and the processor number at the time the error was detected are stored. . Thereafter, even if an error is detected by the error detection means 3, it is not stored in the second register means 5. However, are the error contents stored in the second register means 6 and the output of the error detection means 3 the same as the error contents inputted to the first coincidence detection means 6 and registered as the first occurrence? Know whether or not.

On the other hand, the second coincidence detection means 7 determines whether the processor number at that time is the same as the processor number stored in the second register means 5. At this time, if the error contents are the same but the processor numbers are different, this fact is registered in the third register means 8.

With the above configuration, if there is a registration in the register means 8 of tt and ga, it is known that the failure occurred after the selection means 5, so it is easy to stop using the storage device and modify it. Become.

(Effects of the Invention) As explained above, the present invention detects a match between a register means for storing the output of a processor, an error detection means, and a processor number and registers it in another register means. This has the effect of limiting failure locations and optimizing error handling.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a storage error determination device according to the present invention. FIG. 2 is a block diagram showing an example of a storage error determination device according to the prior art. 1... - Selection means 2.5.8 - aa register means 3... Error detection means 4... Register control means 6, γ... Coincidence detection means

Claims (1)

[Claims] a selection means connected to a plurality of processors for selecting one of the plurality of processors; a first register means for temporarily storing an output of the selection means; and the first register. an error detection means for detecting an error included in data stored in the means; a second register means for storing a set of the output of the error detection means and a processor number given from the outside; register control means for controlling the contents of the second register means according to a past error state detected by the error detection means; and an output of the second register means and an output of the error detection means. , first coincidence detection means for determining whether the contents of the second register means are the contents of an error that occurred and was registered for the first time; and the processor number is the second register means. a second coincidence detection means for determining whether the program number is a program number stored in the program number, and the contents of the error based on the outputs of the first and second coincidence detection means and the output of the register control means. and third register means for determining whether the error has occurred after the selection means.