JPS61174821A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To eliminate errors even if a multiplying circuit is used in a multilevel logic system, by outputting the multiplication result of the multiplying circuit, which consists of MOSFETs and floating switches and is operated in the current mode, as currents indicating a carrier C and a product P. CONSTITUTION:The first current distributing circuit 120 generates (r-1)-number of currents having a value equal to the first input current which indicates one value (x) to be multiplied [(r) is a radix), and floating switches 51a-51c are connected to the output side. The second current distributing circuit 53 generates (r-1)-number of currents having a value equal to the second input current which indicates the other value (y) to be multiplied. Current sources 50a-50c generate currents indicating plural thresholds, and these currents are compared with the current outputted from the second current distributing circuit to control turning-on/off of floating switches. Values (x) and (y) outputted from nodes are divided by (r) in a dividing circuit to generate currents indicating the carrier and the product.

Description

DETAILED DESCRIPTION OF THE INVENTION Summary of the Invention A multiplier circuit configured using MOS FETs and floating switches and operating in current mode.
The multiplication result xy of the two variables X and y is expressed as a carry C and a product P, and a current representing these carries C and P is output.

Table of contents (1) Background of the invention (1, 1) Technical field (1, 21 Prior art (2) Outline of the invention (2, 1) Purpose of the invention (2, 2) Structure and effects of the invention (3) Examples Explanation (3,1) Grandito switch and floating switch
Switch (3, 2) Floating threshold switching circuit (3, 3) Quantization circuit (34) Division circuit (3, 5) Multiplication circuit (1) Background of the invention (1, 1) Technical field This invention relates to a multiplication circuit that is a basic circuit in multi-value logic circuit systems, analog circuit systems, etc.

(1, 2) Prior art] Research into multi-value logic and its arithmetic circuits is actively being conducted to supplement or overcome some of the limitations of binary logic, which is the basis of many digital circuit systems including computers. It is being done. Binary logic handles two values, O and 1, and the signals used in binary logic circuit systems take two levels corresponding to these two values, whereas multi-value logic handles three or more values. Signals used in multivalued logic circuit systems have three or more levels.

Multivalued logic (circuit system) is binary logic (circuit system)
It is said to have the following advantages compared to

1) It is possible to describe an uncertain state between O and 1 (for example, in the case of three values).

2) The wiring area and the number of bins on the IC board can be reduced, and the effective degree of integration can be increased. For example, in the case of 64 values, a wiring area of 1/6 of that of a binary logic circuit is sufficient.

3) Since the realization of a 10-value machine makes it possible to use the same logic as humans, the encoder and decoder required for a binary machine are no longer necessary.

By the way, apart from the perspective of binary and multi-value, from the perspective of circuit modes used in information processing systems,
Conventional circuit systems can be classified into two categories. One is a voltage mode circuit system, where information is represented by the magnitude and polarity of a signal voltage. Most conventional binary digital circuits are of this voltage mode, and some voltage mode multi-value logic circuits have also been reported. The other is a current mode circuit system, where information is represented by the magnitude and direction of a signal current.

For example, the 121 circuit belongs to this category of current mode circuits, and has features such as low supply voltage, small delay time/power product, high density integration, and suitability for VLSI. The application of the 121 circuit to a multivalued logic system has also been reported. For example, T,Tich Dao,
”Threshold12L and Its
Application to Binary
Sya+metric functions an
d Hultivalued Logic”,
IEEE Journal of 5olid-3t
ate C1rcuits.

vol, 5c-12, No, 5.463-472 (1
October 977): T.

Tich Dao, Edward J, HacCI
to uskey and lewis.

Ru5se++, “Hultivalued
Integrated Injection L
ogic”, IEEE-Dingrans, comp
ut,, vo +, C-26, No, 12. I)l
), 1233-1241 (December 1977).

However, since the 121 circuit is constructed with bipolar transistors, it is inevitable that the multiple output current mirrors used in this circuit will produce errors.
This error is particularly significant when one or more collectors of this multi-output current mirror become saturated. Therefore, although there is no particular problem when applying a 12L circuit to a binary logic circuit system, it is extremely difficult to use a 121 circuit in a multi-value logic system, especially a multi-value logic circuit system with 10 or more values. . Furthermore, the switching circuit used in the 12L circuit that has already been reported includes a grounded switch, which consumes power regardless of whether the switch is on or off. The disadvantage is that a diode is required to prevent backflow when connected.

(2) Summary of the Invention ('2.1) Purpose of the Invention This invention is intended to enable the realization of a multi-value logic circuit system with 10 or more values without error even when used for a multi-value logic circuit system. In addition, the present invention provides a multiplication circuit as a basic circuit for realizing a multivalued logic circuit system or an analog circuit system that overcomes the drawbacks of a grounded switch by using a floating switch.

(2,2) Structure and Effect of the Invention The division circuit according to the present invention is capable of handling one of the values to be multiplied by
a first current distribution circuit consisting of a MOS FET that generates (r-1) currents equal to the first input current representing the radix minus 1; connected floating switches, a node connecting the output sides of these floating switches to each other, a value equal to the second input current representing the other value y to be multiplied, minus 1 by the base (r -1>
a second current distribution circuit consisting of a MOS FET that generates currents, a current source that generates currents each representing a plurality of threshold values, and a current output from the second current distribution circuit and an output from the above current source. a current comparison circuit that controls the corresponding floating switches on and off according to the comparison results, and the x-y value output from the node. The present invention is characterized in that it includes a division circuit that generates currents representing carry and product by dividing the current represented by a base number r.

With this configuration, the input current is a current representing two variables The function of outputting is achieved in current mode.

The multiplier circuit according to the present invention has advantages such as low power consumption because it uses a 70-ting switch, and no need for a diode to prevent backflow in parallel connection. Furthermore, since it is constructed using MOS FETs, there are almost no errors, and it is possible to easily create even a multivalued logic circuit with 10 or more values. Furthermore, since the multiplier circuit according to the present invention operates in current mode, addition and subtraction can be achieved by simply connecting the lines through which the currents to be added and subtracted flow, as in the above-mentioned nodes, and the configuration is It becomes simple.

Of course, it goes without saying that the division circuit according to the present invention can be applied not only to multivalued logic operations but also to circuit systems for analog operations.

(3) Description of the embodiment (3, 11 grandate switch and 70-ting switch)
Switches In circuit systems that operate in either current mode or voltage mode, the switches used in these circuit systems can be divided into two types depending on their connection form. These are the grandito switch and the 70-ting switch. A grounded switch and a 70-ting switch in a current mode circuit system are shown in FIGS. 1A and 1B, respectively.

In Figure 1 (A), a node (5) is provided on the line connecting the current source (2) of current J and the output terminal (4), and this node (5) connects to the ground (or power terminal). A switch (1G) is connected between the two. This is the grandito switch.

The switch (1G) is turned on and off by a control signal output from the control signal generation circuit (3). Switch (1G
) is on, the current J output from the current source (2) flows to ground through the switch (1G) as shown by the chain line, so the output current I at the output terminal (4).

becomes O. When the switch (1G) is turned off, the output current of the current source (2) appears as it is at the output terminal (4), so the output current I. becomes J.

In FIG. 1(B), the switch (1F) is a current source (
2) and the output terminal (4). This switch (1F) is called a floating switch because it is floating from ground. When the switch (1F) is on, the output current J of the current source (2) is this switch (1F).
The output current I appears at the output terminal (4) through F)
. becomes J. When the switch (1F) is turned off, the output current of the current source (2) is cut off by this switch (1F), so the output current I. becomes 0.

Compared to a circuit using a floating switch,
Circuits using grounded switches have two major drawbacks.

One drawback is that circuits containing grounded switches
Power is always consumed regardless of whether the switch is on or off. In FIG. 1(A), the switch (
1G) is on, the current J is this switch (1G)
When off, the current J flows to ground through the output current I. bawl. On the other hand, in the circuit including the floating switch shown in FIG. 1(B), the switch (1F
) is on, the current J is the output current I. However, when the switch (1F) is off, no current flows anywhere and no power is consumed.

Another disadvantage of circuits containing grounded switches is most apparent when such circuits are connected in parallel. In FIG. 2, the circuit shown in FIG.
(shown as (gl) and (g2) in FIG. 2) are connected in parallel, and their output terminals are connected at a node (6) and connected to an output terminal (7). One circuit (Ql) is provided with a grandito switch (1G), and the other circuit (g2) is provided with a grandito switch (2G).

Switch (1G) of circuit (gl) is off, circuit (g2)
Consider the state where the switch (2G) is on. In this case, the output current of the circuit (gl) is ■. 1 becomes J, and the output current I of the circuit (g2). 2 is 0. circuit (gl)
The output current i01 does not flow from the node (6) to the output terminal (7), and most of it flows from the node (6) and (5) to the switch (2G) which is on, as shown by the chain line I8.
) and flows to ground.

Therefore, the output current I flows out of terminal (7). teeth,
It is not equal to (Io1+■o2). I.

In order to set = (Io1+Io2), add a chain line (
As shown in 8), it is necessary to provide a backflow prevention diode on the output side of each circuit (gl) (a2).

On the other hand, even if two circuits including floating switches as shown in Figure 1 (B) are connected in parallel, the above-mentioned problem will not occur, and there will be no backflow prevention on the output side. There is no need to connect a diode.

The circuit containing the floating switch is grounded.
A floating switch is employed in the present invention because it has the above-mentioned advantages over a circuit including a switch.

The floating switch can be constructed by a bipolar transistor or a MO8 FET (field effect transistor).

While a certain amount of power is required to control bipolar transistors on and off, MO
Controlling the SFET requires almost no power. From this point of view, it can be said that MOSFETs are better as floating switches.

(3,2) Floating Threshold Switching Circuit FIG. 3 shows an example of a 70-ting threshold switching circuit. The floating switch (1F) is an N-channel MO8 type FET (N-MO
S FET) is used, its drain is connected to the current source (2), its source is connected to the output terminal (4), and the substrate is grounded. Also this MOS
A control voltage output from a control signal generation circuit (3) is applied to the gate of the FET.

The control signal generation circuit (3) is a current comparison circuit, and
It consists of a current mirror (11) made of a channel MO8 type FET (P-MOS FE) and a current mirror (12) made of an N-MOS FET. The current mirror illustrated here is equivalent to a current mirror constructed by two MOS FETs whose gates are connected to each other and whose gates are connected to the drain of one FET. be. Of course, two FETs can be easily integrated and fabricated on one substrate with a common source and gate. Current mirror (
11), when a discharge current (current in the direction of flowing out) 11 is given to its gate by the input terminal (13),
It acts to discharge the same value of current 11 from the output side drain. When the current mirror (12) is given a sinking current (current in the flowing direction) I2 to its gate by the input terminal (14), it acts to sink the same value of current I2 to its output drain.

The source of the current mirror (11) is connected to the positive power supply +Vo, and the source of the current mirror (12) is grounded. The output side drains of these two current mirrors (11H12) are connected to each other by a node (15), and this node (
15) is connected to the gate of the MOS FET constituting the floating switch (1F).

Now, when the current I2 is larger than the current I2, the current mirror (11) is turned on, and the current mirror (12) sinks and generates the output current I2. Therefore, the node (15
) becomes a high level (approximately equal to the power supply voltage +VD). This high level voltage
Since the voltage is applied to the gate of the N-MOS FET constituting the switch (1F), this FET is turned on. Therefore, the current J of the current source (2) is the output current l. It flows out from the terminal (4) as.

On the other hand, when the current (1) is smaller than the current I2, the current mirror (12) is turned on, and the current mirror (11) generates the source output current (1). Therefore, the node (1
Since the potential of 5) becomes low level (mostly OV), the FET of the 70-ting switch (1F) remains off. Output current I. is O.

When the current I is fixed as a constant value and the current 11 is varied, if the current I exceeds the current I2, the floating switch (1F) is turned on and the output current I becomes the value of J. When the current ■1 becomes smaller than the current I2, the floating switch (1F) turns off and the output current I
becomes O. In the circuit of FIG. 3, the output type yLt0 changes to J according to the value of the current 11 with the current I2 as the threshold value.
It is converted into two levels: and O. Furthermore, a floating switch is used in the circuit of FIG. Therefore,
This kind of circuit is called [floating threshold]
It is called a switching circuit.

When considering that the current 11 is fixed as a constant value and the current I2 is changed, the current 1 becomes the threshold value.

Furthermore, the circuit of FIG. 3 has an interesting feature. That is, the signal for controlling the floating switch (1F) on and off is a "voltage" signal (voltage mode) (potential of the node (15)). On the other hand, the signal switched by the floating switch (1F) (signal flowing through the floating switch) is a "current"
signal (current mode). A circuit that operates in a combination of voltage mode and current mode in this manner will be referred to as a "hybrid mode circuit." Such a hybrid mode circuit can have a circuit that operates in voltage mode as a control circuit, and it is also possible to connect a circuit that operates in current mode to these circuits as a controlled circuit and a control circuit. , has extremely high versatility and a wide range of applications.

Incidentally, the signals compared by the control signal generation circuit (current comparison circuit) (3) are in current mode. Therefore, this third
It can be said that the circuit shown in the figure performs current/voltage/current mode conversion.

FIG. 4 shows a model of a floating threshold switching circuit.

Figure 4 (A>) shows the current mirror (11) and its input terminal (13) in Figure 3 as a current source (21), and the current mirror (12) and its input terminal (14) as a current source (21).
2) respectively. Current comparison circuit (
3) can generally be characterized as two non-linear current sources connected in series and driven by a constant supply voltage.

FIG. 4(B) shows a circuit in which a P-MOS FET is used as a floating switch (1F). This FET has its source connected to a current source (2) and its drain connected to an output terminal (4).

Further, the substrate of this FET is connected to the power supply voltage +■o. In this circuit, when 11<I2 and the potential at the node (15) becomes low level, the FET
(Floating switch (IF)) is turned on,
Output current I. J is obtained as Also, 11>I,,
When the potential at the node (15) becomes high level, FE
T is turned off and the output current is ■.

becomes O.

Dumpling circuits and division circuits that apply a 70-ting threshold switching circuit will be described below, and then the multiplication circuit of the present invention will be described.

(3,3) Dumpling circuit Dumpling circuit (quant
izer) (or analog/multi-value conversion circuit) is defined as follows.

Here, 1 is O or a positive integer, i.e. 0≦i≦r-1 ±0.5 in (i-0,5)≦x<(i+0.5) of equation (1) is an integer to be quantized Of course, any value less than 1 can be used instead of this value of 0.5.

An example of a quantization circuit when r=4 is shown in FIG.

Three current sources (52
a) (52b) (52c) are provided, these G, 17
0-ting switch (51a) (51b) (51C
) (70-ting switch (1F) in Figure 4 (B)
(corresponding to) at a node (57), and an output terminal (54) is connected to this node (57).

The input (variable) X to be lumped is the input terminal (56)
is given as a sink input current representing this value X. The input terminal (56) is connected to the gate of a three-output current mirror (or current distribution circuit) (53). From the three output drains of the three-output current mirror (53)
Three sink output currents with values of are output.

The drain for one output of the 3-output current mirror (53) is 0
．． A current source (50a) that provides a sinking input current with a value of 5
is connected at the node (55a), and this node (5
5a) is connected to the gate of the floating switch (51a). Part of the 3-output current mirror (53),
The current source (50a) and the node (55a) correspond to the above-mentioned control signal generation circuit (3), and the node (55a) corresponds to the node (15). Therefore, when 0.5≦X, the potential at the node (15) becomes low level,
The floating switch (51a) is turned on.

Similarly, part of the three-output current mirror (53), a current source (sob) providing a sinking input current of 1.5, a node (
ssb) and the floating switch (51b) constitute a 70-ting threshold switching circuit, and when 1.5≦X, the switch (51b)
turns on.

Furthermore, a part of the 3-output current mirror (53), a current source (50c) that provides a sinking input current of 2.5, and a node (
55c) and the floating switch (51C) constitute a floating threshold switching circuit, and when 2.5≦X, the switch (51c)
turns on.

Therefore, when X<O,S, all floating switches (51a) to (51c) are off and the output current at the output terminal (54) is O. 0.5≦X<
In the case of 1.5, only the switch (51a) is turned on, and the output current represents a value of 1. 1.5≦x<2.5
In this case, the switches (51a) and (51b) are turned on, so two currents with a value of 1 are coupled at the node (57), and the output current has a value of 2.

When 2.5≦X, all switches (51a) to (
51C) is turned on, the output current is 3.

FIG. 7 shows the input/output characteristics of the quantization circuit in the case of r=4.

The three current sources (528)-(52C) can be replaced with a three-output current mirror (59) as shown in FIG. A source input current having a value of 1 is applied to the input terminal (58).

If you want to increase the value of the radix r, you can further increase the number of combination circuits consisting of a current source with a value of 1 and a floating threshold switching circuit, and connect the output side to the node (57). It's easy to understand that it's good.

(3, 4) Division circuit The division circuit (divide) in r-value logic with r as the base
The operation of er) is given by the following equation.

Quotient: Q = i
・(2-1) Remainder (res 1due): R3(
x+r-B, o) modV...(2-2) However, r>i≧0 (i is a positive integer) i-y-o, s≦r-B, o+x <(i+1)◆V-0 , 5 where (x+r-8,) is the dividend and y is the divisor n. Nod is the modulo (HO
dUIO). Bio represents a borrow from the higher digit. Also, the value is 0.
5 is the noise margin taken into consideration in the multivalued logic circuit. Set this to 1 when considering noise margin.
Can be any value less than or equal to

Equations (2-11 and (2-2)) can be expressed more specifically in the case of r=4 as follows.

If (x+r-Bio) < (V -0,5), then (V
−0,5)≦(x+r−Jo)<V, then y≦(X +
If r-B in) <(2"y' 0.5) (2y-0,5) ≦ (x+r-BH,) < 2y then 2y ≦ (x+r - Bin) < (3y -0,5)
In the case of (3V-0,5)≦(x+r-B,o)<3y In the case of 3y≦(x+r-87n) FIG. 8 shows an example of a division circuit in the case of r-4. This circuit is constructed by a combination of the above-described quantization circuit and floating threshold switching circuit.

Therefore, parts corresponding to each component of the quantization circuit shown in FIG. 5 are given the same reference numerals. however,
The floating switches (51a) to (51c) are composed of P-MOS FETs in FIG.
In FIG. 8, it is composed of N-MOS FETs. Therefore, the direction of the current in the current comparator circuit that generates control signals for controlling these floating switches is also reversed between FIG. 5 and FIG. 8. A high output Q appears at the output terminal (54) of the hanging circuit.

One input (variable) X is given to the input terminal (106X) as a sink input current. This terminal (106x)
Since is connected to the current mirror (103), a sink output current of the value of X is obtained from the current mirror (103). The current mirror (103) can be omitted by changing the direction of the current X input to the terminal (106x).

An input current representing the borrow power Jo (takes a value of 0.1 or 2 when r=4) is applied from the input terminal (106B) to the four-output current mirror (102). The four output drains (equal to the radix r) of the four-output current mirror (102) are connected to each other and to the output side of the current mirror (103) by a node (112).

Therefore, the node (112) has a four-output current mirror (
102) provides input for discharging the value of ``Bin''.

Addition of (x+rzBin) is performed at the node (112). This becomes the dividend. Dividend (X+r-3
The source input current representing , , ) is a four-output current mirror (
110). 3 of 4 output current mirrors (110)
The two output drains form part of the quantization circuit. That is, it corresponds to the current mirror (53) in FIG. Another output drain of the four-output current mirror (110) is connected to the output terminal (108) of the remainder R via a diode (107). The diode (107) is connected in a forward direction to the current discharged from this output train.

An input (variable) y representing a divisor is given as a sink input current to a nine-output current mirror (104) via an input terminal (106y). One output drain of the nine-output current mirror (104) is connected to one output drain of the four-output current mirror (110) at a node (105a). This node (105a) is the node (10
9a) to the gate of the floating switch (51a). Node point (105a) and (109
a) corresponds to the node (55a) in FIG. Node point (
105a) is connected to a current source (100a) which provides a sink input current with a value of 0.5. This current source (1
00a) and a node (105
The combination with the drain for one output of the nine-output current mirror (104) connected through the current source (50a) in FIG.
). At the node (105a), (x+r-J
o) sink current from the current mirror (110), 0.
A sink input current of 5 is provided from a current source (100a), and a source input current of y is provided from a current mirror (104).

The other two output drains of the 9-output current mirror (104) are connected to each other and connected to the 4-output drain through a node (105b).
It is connected to the other output drain of the output current mirror (110). A source input current having a value of 2y is applied to the node (105b) by a current mirror (104). A current source (100b) is connected to the node (105b).
(current value 0.5) is connected, and the node (
109b) via the floating switch (51b
) are connected. This is the current source (50b) in Figure 5.
and corresponds to the node (55b).

Similarly, the other three output drains of the nine-output current mirror (104) are connected to each other and at the node (105).
c) to the drain of yet another output of the four-output current mirror (110). Node point (10
5c) is given a source input current with a value of 3y by a current mirror (104). A current source (100C) (current value 0.5) is connected to the node (105c), and a floating switch (51c) is connected via the node (109c). This is the fifth
This corresponds to the current m (50c) and the node (55c) in the figure.

The remaining three output drains of the 9-output current mirror (104) are each connected to a 70-ting switch (101a).
(101b) (101c) through the diode (107
) (7) Node points (111a) (111b) on the 7/-t' side
) (111C). These 70-
Switching switch (101a) (101b) (101
c) are node points (109a) (109b) (109c)
(i.e. node points (105a) (105b) (105C
)) is controlled to be turned on or off by the potential.

Since the signal that controls the floating switch is in voltage mode, it can be shared among multiple floating switches such that the potential at the node (55a) controls the two floating switches (51a) and (101a) at the same time. It should also be noted that it is possible to

In the case of (x + r −B, o) < (y −0, 5), (formula f2-3)), that is, (X+r−Bin
10.5)<y, all nodes (105a
) to (105c) are at a low level, and all floating switches (51a) to (51c) and (101a) to (101c) are in an off state.

Therefore, the high output Q is O. Also, the remainder output terminal (
108), the output current of the current mirror (110) appears as is, so the residual output R is (X+r・B in)
becomes.

(y-0,5)≦(x+r-Bin)<y+7)
In the case (Equation 2-41), that is, y≦(X+r−Bi
.

+ 0.5) < (y+ 0.5) (<2y), only the potential at the node (105a) becomes high level, and the floating switches (51a) and (1
01a) is turned on. Therefore, the output terminal of the quotient Q (
54), a source output current having a value of 1 appears. 70
When the switching switch (101a) is turned on, a source input current of the value y is given to the node (111a), so at the node (111a) ((x+r
-J,)-1/) is performed.

Although the result of this subtraction is negative, this reverse current is blocked by the diode (107), so the residual output R at the terminal (108) becomes O.

y≦(x+r−Jo)<(2y−0,5)(th (2−
5), that is, (y<) (y+ 0.5)≦(
Even when X+r-Bio+015)<2y, only the potential at the node (105a) becomes high level, and 70-
The switching switch (51a) (101a) is turned on. The high output Q has a value of 1. Also, the node (llll
Since the subtraction result (x+r-3in-y) in a) is not negative, the current representing this subtraction result flows through the diode (
107) and is outputted as a residual output R to an output terminal (108).

As the value of (x+rzJ,) increases, the potentials of the nodes (105b) (105C) become high level one after another, and the floating switches (51b) (101b
), (51c), and (101c) are turned on in sequence.

As a result, it is easy to understand that a high output Q and a residual output R as expressed by equations (2-6) to (2-9) are obtained.

FIG. 9 shows the input/output characteristics of the circuit shown in FIG. 8 when r=4 and y=2, that is, the relationship between the input (x+r-87n) and the outputs R and Q. In this graph,
Borrow manpower Jn is limited to 0 and 1.

The divider circuit in FIG. 8 consists of a multi-output current mirror (102) (
104) The number of output drains in (110), the number of current sources and floating switches in the quantization circuit, and the floating switches (101a) to (101C
) and the number of nodes (111a) to (111c), etc., it goes without saying that the present invention can be applied to multivalued logic of any base r. Current source (100a) ~ (100C)
A desired noise margin can be set by arbitrarily setting the noise margin (value of 0, 5) expressed by the output current value.

If the noise margin is brought as close as possible to O, the circuit shown in FIG. 8 will become a divider circuit for analog calculations.

(3,5) Multiplication circuit Multiplication circuit (multiplication circuit) in r-value logic with r as the radix
The operation of plier) is given by the following equation.

Carry: C= i ・(3
-1)ut Product: P= (x fist V) Nod r...(3-2) However, r>i≧O (i is a positive integer) i-r≦x-y≦(i+1 )・r-0,5 Here, carry C3ut represents a carry to the next higher digit. The product P represents the value of the relevant digit of the numerical value representing the multiplication result. Further, 05 is a noise margin.

An example of a multiplication circuit in the case of r=4 is shown in FIG. As can be seen from this figure, the multiplication circuit is composed of the above-mentioned emphasizing circuit and the division circuit.

In the quantization circuit (140) in the circuit of FIG. 10, the same components as those shown in FIG. 5 are given the same reference numerals. Current sources (52a) to (52c) with a value of 1 in FIG.
), input terminal (126) and 3 output current mirror (
120) are provided. An input terminal (126) is provided with a sinking input current representing the value of one input, X, and three currents representing the value of X are generated by a three-output current mirror. The other input terminal, the current representing the value of y, is provided by the input terminal (56). Depending on the value of y, a floating switch (51a
) to (51C) are controlled to be turned on or off. The larger the value of y, the more floating switches are turned on. Therefore, from the node (57), (X
-V) is discharged, and this current is sent to the next stage division circuit (141).

In r-valued logic, the maximum value of the multiplication result is (r-1)x(
r-1). This is transformed as follows.

(r-1) X (r-1) -r2-2r+1 =j'×(r-2) +1...(3-3)
Therefore, the maximum value of carry output C8,t is (r-2)
It is. Therefore, (r-2> current comparison circuits are required in the division circuit portion of the multiplication circuit. (r
-1) It is sufficient to prepare a value division circuit.

The division circuit (141) in FIG.
1) It is configured like a value division circuit. In this figure, the same components as the division circuit of FIG. 8 are given the same reference numerals. However, in the current sources (122a) (122b), floating switches (121a) (121b), etc. that constitute part of the quantization circuit in the division circuit (141), the configuration of the quantization circuit (140) in the previous stage The same symbols are written in parentheses to avoid confusion with the elements.

The high output Q terminal (54) in FIG. 8 corresponds to the carry output C3ut output terminal (124) in FIG.

A product output P appears at the output terminal (108). The multi-output current mirror (104) in FIG. 8 is replaced by the current source (104) in FIG.
31) (132) (133) (134) can be easily understood.

From the operation of the division circuit described above, it will be easily understood that the circuit shown in FIG. 10 performs the multiplication expressed by equations (3-1) and (3-2).

It goes without saying that the noise margin can be arbitrarily selected in this multiplication circuit as well.

The input/output characteristics of the multiplication circuit (r=4>) shown in FIG. 10 are shown in FIG. 11. A comparison with FIG. 9 shows that the input/output characteristics are very similar to the input/output characteristics of the division circuit.

[Brief explanation of the drawing]

FIG. 1 shows the types of switches; FIG. 1(A) shows a grounded switch, and FIG. 1(B) shows a floating switch. FIG. 2 is for explaining the drawbacks of the grounded switch, and shows a state in which two circuits including grounded switches are connected in parallel. FIG. 3 shows an example of a floating threshold switching circuit, and FIG. 4 shows models of two types of floating threshold switching circuits. FIG. 5 is a circuit diagram showing an example of a hanging circuit, FIG. 6 is a diagram showing another example of a current source, and FIG. 7 is a graph showing an example of input/output characteristics of a hanging circuit. FIG. 8 is a circuit diagram showing an example of a division circuit, and FIG. 9 is a graph showing its input/output characteristics. FIG. 10 is a circuit diagram showing an example of a multiplication circuit, and FIG. 11 is a graph showing its input/output characteristics. (50a) ~ (50c) ... Current source, (51a)
~ (51c) -...Floating switch, (
53)...Second current distribution circuit, (55a) to (55
c)... Node point of current comparison circuit, (56) (126)
...Input terminal, (51)...Node point, (108)
...Product output terminal, (120)...First current distribution circuit, (124)...Carry output terminal, (141)...
Division circuit. (A) (B) Figure 2 Figure 8 Io" [o) - ¥1τ):21:) Figure 4 (A) Procedural Amendment Written Procedural Amendment 1985 6 25th of the month

Claims (1)

[Scope of Claims] A first current formed by a MOSFET that generates (r-1) currents equal to the first input current representing one of the values x to be multiplied, which is the base r minus 1. a distribution circuit, a floating switch connected respectively to the output side of the first current distribution circuit, a node connecting the output sides of these floating switches to each other, a second value representing the other value y to be multiplied; a second current distribution circuit comprising a MOSFET that generates (r-1) currents with a value equal to the input current minus 1 by the base; a current source that generates currents each representing a plurality of threshold values; A current comparison in which the current output from the current distribution circuit No. 2 and the threshold value current output from the current source are respectively compared, and the corresponding floating switches are controlled to be turned on or off according to the comparison results. A multiplication circuit comprising: a circuit; and a division circuit that generates currents representing carry and product by dividing a current representing the value of x and y outputted from the node by a base number r.