JPS61176148A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a dynamic random access memory (D-RAM) cell having one transistor/one capacitor structure with increased capacitance.

As the functions of information processing devices have expanded, the D-RAMs installed in the information processing devices have also become larger in scale. Integration is progressing rapidly.

However, when the D-RAM becomes extremely dense and highly integrated, the amount of information charge stored in the capacitor decreases significantly due to a significant reduction in capacitor capacity due to the reduction in cell area. The D
-There is a problem that the credibility of RAM is decreasing,
D-RA with small cell area and large capacitor capacity
M cell is requested.

[Conventional technology]

In the one-transistor/one-capacitor type D-RAM cell, a stacked capacitor type cell, whose side cross section is schematically shown in FIG. 3, was originally proposed as a structure for increasing the capacitor capacity.

In FIG. 3, 1 is a p-type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, 5 is a gate electrode, and 6 is a word・Transistor gate electrode), 7
is a first insulating film, 8 is an n3 type drain region, 9 is an n0 type region which becomes a storage node, 10 is a first capacitor electrode,
11 is a dielectric film, 12 is a second capacitor electrode, Tr is a transfer transistor, and C is a capacitor.

According to this cell structure, the first capacitor electrode for charge storage extends to the upper part of the word [6] adjacent to the gate electrode 5 of the transfer transistor Tr of the own cell, so that the second Compared to a normal D-RAM cell in which eight mold regions serve as one electrode of the capacitor, the capacitance of the capacitor is increased approximately two to three times.

However, in a situation where high integration has progressed significantly, increasing the capacitance by a factor of 2 to 3 is insufficient in terms of detection accuracy of stored information and resistance to soft error alpha rays, and it is necessary to further increase the capacitor capacity. A trench capacitor type cell has conventionally been provided as a structure for this purpose.

FIG. 4 schematically shows a side cross section of the trench capacitor type cell, in which 12a and 12b are trenches, 13a and 13b are charge storage regions (depletion layers), and 14
indicates a capacitor electrode, and other symbols indicate the same objects as in FIG.

This trench capacitor type cell has the advantage that by increasing the depth of the trench, the capacitor capacity can be further increased significantly compared to the stacked capacitor type cell having the same cell area.

[Problem that the invention seeks to solve]

However, in the trench capacitor type D-RAM cell, the charge storage regions 13a, 13b, etc., which are made up of depletion layers formed around the trenches 12a, 12b, etc., greatly expand due to the voltage applied to the capacitor electrode 14 (as shown in the figure). The trenches of adjacent cells, for example, 12a and 12b, are provided close to each other because the back bias is particularly thick (widened) in the middle between the tip of the trench where it functions strongly and the base of the trench where the channel cut region functions. In this case, leakage of accumulated charges occurs and information is lost.

Therefore, the width of the isolation region between each cell, that is, the field oxide film 3
It is necessary to widen the width of the region in which the ICs are arranged, which poses a problem in that the improvement in the degree of integration is hindered.

[Means for solving problems]

The above problems are: - MI formed on a conductive type semiconductor substrate;
an S-type transfer transistor; an insulating film formed on the transistor; a first through hole that exposes a first opposite conductivity type region of the transistor formed in the insulating film; a cylindrical first capacitor electrode whose bottom portion formed on the inner surface is in contact with the first opposite conductivity type region; a dielectric film formed on a surface of the opposite conductivity type region; a second capacitor electrode embedded within the first capacitor electrode via the dielectric film and having an upper portion extending above the insulating film; a second through hole that exposes a second opposite conductivity type region of the transistor formed in the insulating film; The problem is solved by a semiconductor memory device according to the present invention, which has a conductive layer whose upper portion is connected to a bit line.

[Effect]

That is, in the D-RAM cell of the present invention, a thick insulating film is provided above the transfer transistor, and a cylindrical insulating film is formed in the insulating film so as to penetrate through the insulating film and contact the impurity diffusion region that becomes the storage node of the transfer transistor. By forming the insulating film thickly, the capacitor capacity can be greatly increased, which improves information detection accuracy and soft error α-ray resistance, and also improves the resistance of adjacent cells. Since the capacitor is completely separated from the capacitor by the insulating film, leakage of stored charges does not occur, and the reliability of stored information is improved.

〔Example〕

The present invention will be specifically described below with reference to illustrated embodiments.

FIG. 1 is a schematic plan view (a
) and a schematic side sectional view (b), and FIG. 2 is a process sectional view showing the manufacturing method.

Identical objects are designated by the same reference numerals throughout the design.

In FIG. 1, 1 is a p-type silicon substrate, 2 is a p-type channel cut region, 3 is a field oxide film, 4 is a gate oxide film, and 5a, 5b, and 5c are first polycrystalline silicon layers PA. The gate electrode (word line), 8 is an n++ drain region, and 9 is an n° type region 21 which becomes a storage node, and has a thickness of, for example, 1 to 2 μm, formed by chemical vapor deposition (CVD).
A silicon dioxide (Si(h) insulating film with a thickness of approximately 1.5 to 2 m, for example 1.5 to 2
A first through hole with a diameter of about μm, 23 a second through hole with a diameter of about 0.7 to 1 μm, for example, which exposes the n++ drain region, 24 a second polycrystalline silicon layer (PB)
The charge storage capacitor electrode 25 is also PR.
The drain electrode 26 has a thickness of about 100, for example, 3i0. 27 is a counter capacitor electrode made of a third polycrystalline silicon layer PC, 28 is a phosphosilicate glass (PSG) insulating film, 29 is a contact window, 30 is a bit wiring made of aluminum or the like, and Tr is a transfer wire.・Transistor, C indicates a capacitor.

As shown in the figure, the D-RAM cell according to the present invention has a thick St〇-
An insulating film 21 is provided, and this 5ift insulating film 21 has a first through-hole 22 for a capacitor that exposes an n-type region 9 which becomes a storage node of a transfer transistor Tr, and a second through-hole 22 that exposes an n+-type drain region 8. A through hole 23 is formed in the first through hole 22, and a cylindrical charge storage capacitor bridge 24 is in contact with the bottom of the n-type region 9 which becomes a storage node of the transfer transistor Tr; a dielectric film 26 formed on the inner and upper surfaces of the n+ type region 9 exposed inside the electrode 24;
A capacitor C consisting of a counter capacitor electrode 27 embedded through the capacitor 6 and whose upper part extends to the SiO□ insulating film 21.
The n0 type drain region 8 of the transfer transistor Tr is connected to the bit wiring 30 via the drain electrode 25 buried in the second through hole 23 and the contact window 29.

The D-RAM cell is formed, for example, by the method described below with reference to process cross-sectional views shown in FIGS. 2(a) to 2(e).

After forming a transfer transistor Tr on a p-type silicon substrate 1 by a conventional method, a SiO□ insulating film 2 with a thickness of about 1 to 2 μm, for example, is formed on the substrate by a CVD method.
1, followed by regular glue active ion etching (RI).
E) A first through hole 22 with a diameter of, for example, about 1.5 to 2 μm is exposed in the Si0g insulating film 21 to expose an n+ type region 9 that will become a storage node, and an n1 type drain region 8 is formed by the method E).
A second through hole 23 with a diameter of, for example, about 0.7 to 1 .mu.m is formed to expose the.

Refer to Figure 2) Next, a second through hole 2 is formed on the substrate by CVD method.
A second polycrystalline silicon layer PB is formed to a thickness of, for example, about 5,000 layers to fill the second polycrystalline silicon layer PB. At this time, the first through hole 22 is not filled, and a PB layer having the above-mentioned thickness is formed on the side and bottom surfaces thereof.

Refer to FIG. 2(C). Next, the entire surface is etched by RIE to expose the upper surface of the JSi02 insulating film 21 and nine surfaces of the n-type region that will become the storage node in the first through hole 22, and then thermal oxidation is performed to A Sing dielectric film 26 having a thickness of, for example, about 100 layers is formed on the surface of the PA layer and the exposed surface of the n-type region 9.

Note that the PR layer in the first through hole 22 becomes a cylindrical charge storage capacitor electrode 24, and the PR layer in the first through hole 22 becomes a cylindrical charge storage capacitor electrode 24.
The PB layer in 3 becomes the drain electrode 25.

Referring to FIG. 2(d), a third polycrystalline silicon layer pc having a thickness of, for example, about 5000λ is formed on the substrate by the CVD method to fill the inside of the cylindrical charge storage capacitor electrode 24, and then RI
An opening 31 exposing the upper surface of the drain electrode 25 is formed in the 20th layer by the E method.

Here, the 20th layer becomes a counter capacitor electrode 27.

Refer to Figure 2+11) Next, a PS film with a thickness of about 18 parts is deposited on the substrate by CVD method.
A G insulating film 28 is formed, and a drain electrode 2 is formed on the PSG insulating film 28 by a normal method.
A contact window 29 exposing the upper surface of the contact window 29 is formed, and a bit wiring 30 is formed on the insulating film 29 by a conventional method so as to be in contact with the drain electrode 25 at the contact window 29 portion.

Thereafter, a cover insulating film (not shown) is formed, and the D-RAM cell according to the present invention is completed.

As is clear from the description of the above embodiments, in principle, in the D-RAM cell according to the present invention, the cylindrical capacitor can be formed as deep as the CVD method allows the conductive layer to grow to the bottom. Is possible. Therefore, the capacitance of the capacitor can be significantly increased compared to the conventional one.

Furthermore, since the cylindrical capacitor is provided within the insulating film,
The insulating film separates the cylindrical capacitors of adjacent cells, and leakage of information charges is completely prevented.

Furthermore, since the capacitor is provided within the insulating film, charges generated in the silicon substrate due to incidence of α rays do not reach the capacitor, and resistance to soft error α rays is also increased.

Note that the capacitor electrode is not limited to the polycrystalline silicon shown in the above embodiment, but may be made of a conductive material such as molybdenum silicide.

〔Effect of the invention〕

As explained above, according to the present invention, one transistor/one
It is possible to significantly increase the capacitance of a dynamic random access memory (D-RAM) cell with a capacitor structure, eliminate information charge leakage between adjacent capacitors, and improve resistance to soft error alpha rays. Its credibility will improve.

[Brief explanation of drawings]

FIG. 1 is a schematic plan view (a
) and schematic side sectional view), FIGS. 2(8) to (e) are process sectional views showing the manufacturing method, FIG. 3 is a side sectional view of a stacked capacitor type D-RAM cell, and FIG. 4 is a side sectional view of the stacked capacitor type D-RAM cell. FIG. 2 is a side cross-sectional view of a trench capacitor type cell. In the figure, 5a, 5b, 5c are gate electrodes (word lines) 8 are n9 type drain regions, 9 is an n0 type region which becomes a storage node, 21 is a silicon dioxide insulating film, 22 is a first through hole, 23 is a first through hole. 2 is a through hole, 24 is a charge storage capacitor electrode, 25 is a drain electrode, 26 is a dielectric film, 27 is a counter capacitor electrode, 2 is a phosphosilicate glass insulating film, 29 is a contact window, 30 is a bit wiring, Tr indicates a transfer transistor, and C indicates a capacitor. y'I ¥-2 Hisho 3 Intoxication Fist 4 Intoxication

Claims (1)

[Claims] An MIS transfer transistor formed on a semiconductor substrate of one conductivity type, an insulating film formed on the transistor, and a first conductivity type transfer transistor of the transistor formed on the insulating film.
a first through hole that exposes a region of opposite conductivity type; a cylindrical first capacitor electrode formed on the inner surface of the through hole, the bottom of which touches the first region of opposite conductivity type; a dielectric film formed on the inner surface of the capacitor electrode and the first opposite conductivity type region exposed inside the capacitor electrode; and a dielectric film formed on the first opposite conductivity type region surface exposed inside the capacitor electrode; a second capacitor electrode whose upper portion extends over the insulating film; a second through hole that exposes a second opposite conductivity type region of the transistor formed in the insulating film; a conductive layer embedded in a through hole, a bottom portion of which is in contact with the second opposite conductivity type region, and an upper portion of which is connected to a bit line.