JPS61184975A - Solid-state image pickup element - Google Patents

Abstract

PURPOSE:To sharply increase the proportion of opening sections to the area of vertical charge transferring element regions so as to improve the sensitivity of an interline CCD, by making the area of vertical charge transferring element regions in which signal charges to be accumulated and transferred are distributed in plural transfer stages. CONSTITUTION:At a certain time in the course of horizontal scanning, a vertical shift register 18 turns on a photo-gate 15 by applying a voltage across the vertical gate line 50 of the n-th line and transfers accumulated signal charges to a vertical charge transferring element 12 side. At this moment, a high voltage is applied across all vertical pulse lines 51 and the signal charges are accumulated over plural transfer stages of the vertical charge transferring elements in the vicinity of the selected vertical gate line 50 in accordance with the quantity of the charges. When a vertical transfer shift register 16 is actuated thereafter, voltages of the vertical pulse lines 51 successively become lower one transfer stage by one transfer stage from the farthest line from a horizontal charge transferring element and a resulting potential barrier moves in the vertical charge transferring elements 12 so as to approach the 1st line. When the barrier reaches a transfer stage near the n-th line where the signal charges are accumulated, the signal charges are transferred to the next stage and, when the next stage is filled up with signal charges, to an empty transfer stage after the next stage.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a solid-state image sensor, and particularly to a CCD (Character).
The present invention relates to a circuit configuration suitable for realizing high sensitivity, high resolution, low smear, and high yield in a solid-state imaging device (Coupled Device) and its control method.

[Background of the invention]

CCD is conventionally known as a type of two-dimensional surface imaging device.
One of the methods, an interline CCD solid-state image sensor, is Sequin, Tompsett
Authorrcharge Transfer Device
esJ Academic Press 1975
It is described in PP152~, and has a circuit configuration as shown in FIG. In FIG. 4, 1 is a photodiode that is arranged two-dimensionally and performs photoelectric conversion, 2 is a vertical charge transfer element that is arranged in each column and performs vertical scanning, and 3 is a vertical charge transfer element that is arranged in each column and performs vertical scanning.
4 is a horizontal charge transfer element that performs horizontal scanning; 4 is an output portion of the horizontal charge transfer element; 5 is a photogate that transfers signal charges from the photodiode l to the vertical charge transfer element 2; Also.

The vertical solid line in the horizontal charge transfer element 3 and the horizontal solid line in the vertical charge transfer element 2 indicate the boundaries of one transfer element in both charge transfer elements.

In the illustrated circuit, first, during the vertical blanking period, the photogate 5 is opened, and the signal charges that have been photoelectrically converted and stored in the photodiode 1 are transferred to the vertical charge transfer element 2. Then, during the horizontal blanking period, When an external clock is received, signal charges are transferred within the vertical charge transfer element 2 for one transfer element, and the signal charges in the first row are transferred to the horizontal charge transfer element 3. During the horizontal scanning period, signal charges are sequentially transferred within the horizontal charge transfer element 3 and output from the output section 4. By repeating this operation within the vertical scanning period, signal charges in each row are sequentially read out.

Furthermore, in order to improve the resolution, this circuit performs interlaced scanning, that is, the signal charges are read out in the odd rows in the first field and in the even rows in the second field.

In this circuit, at least one transfer element of the vertical charge transfer element is provided for every two photodiodes l so that the signal charges of the photodiodes l are not mixed during vertical transfer, and one transfer element of the vertical charge transfer element is It is necessary to have a capacity sufficient to store and transfer the signal charges of two photodiodes 1. Furthermore, in order to prevent exposure during vertical scanning, 1. The vertical charge transfer element 2 is optically sealed.
It is necessary to As a result, the light sensing area (hereinafter referred to as the aperture) is only about 30 to 40% of the entire device.

By the way, in the above-mentioned interlaced scanning, the signal accumulation time of one photodiode is l frames,
An afterimage for one field is generated.

As a method for reducing this afterimage and realizing a single-chip color image sensor with high resolution and high image quality, N and K are used.

ike et al 1 (179I 5scc Dig
There is a vertical two-pixel simultaneous readout method that performs interlaced scanning, which is described in EST PP193-.

This method uses one field in one scanning period.

For example, signal charges in two rows, n rows and n+1 rows, are read out, and signal charges in two rows, n-1 rows and n rows, are read out in one horizontal scanning period of the next field.

When applying the above readout method to an interline COD, in Japanese Utility Model Publication No. 58-56458, two vertical charge transfer elements 2 are arranged for one column of photodiodes 1, and time readout between two pixels is performed. This has resulted in improved image quality.

However, the sensitivity decreases due to the decrease in the aperture ratio,
No consideration is given to the reduction in yield due to the relatively complex and dense planar structure of the pixel portion, which occupies most of the device.

On the other hand, in all solid-state image sensors, when a bright subject is photographed, a vertical smear phenomenon occurs that leaves white tails at the top and bottom of the reproduced image, which causes image quality deterioration under high illuminance. As a method for reducing this vertical smear under all subject conditions, there is a smear differential method described by Ozawa et al. in Proceedings of the 1984 Television Society National Conference 3-15° PP67~.

This method first reads only the vertical smear.

Next, read out the signal charges superimposed on the vertical smear.

By making a difference between the two, only the signal charge is output. Also, this method can be applied to interline CO
In order to apply this to D, a vertical charge transfer element 2 is required to transfer vertical smear charges. As a result, the aperture area is further reduced compared to the device of FIG.

[Purpose of the invention]

The purpose of the present invention is to solve such conventional problems, and to solve the problem in interline COD without reducing the aperture ratio or making the planar structure of one pixel part complicated or overcrowded.
Realizes 2-pixel time readout and smear differential method, high sensitivity,
High resolution, low smear.

An object of the present invention is to provide a high-yield solid-state imaging device.

[Summary of the invention]

In order to achieve the above objects, 1 the solid-state image sensor of the present invention has 2
photoelectric conversion elements arranged in a dimension, a vertical charge transfer element that transfers signal charges from the photoelectric conversion elements in a vertical direction;
In a solid-state imaging device including a horizontal charge transfer element that horizontally transfers signal charges from the vertical charge transfer element, the signal charges in the vertical charge transfer element are transferred to the horizontal charge transfer element within one horizontal scanning period. It is characterized by having a shift register that sends out a pulse train.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

First, a first embodiment of the present invention will be described with reference to FIGS. 1 to 3.

Figure 1 is a circuit configuration diagram of the solid-state image sensor, Figure 2 is a timing diagram of the drive pulses in Figure 1, and Figure 3 is the potential of the vertical charge transfer element, transfer gate, and horizontal charge transfer element at the timing of Figure 2. It is a diagram. In order to simplify the explanation, only a 3×3 photodiode matrix is shown in FIG.

In FIG. 1, 11 is a photodiode that is arranged in a two-dimensional manner and performs photoelectric conversion; 12 is a vertical charge transfer element that is arranged in each column and performs vertical charge transfer; 13 is a horizontal charge transfer element that performs horizontal scanning; 14 is an output part of the horizontal charge transfer element 13; 15 is a photogate that transfers the signal charge of the photodiode 11 to the vertical charge transfer element 12; 16 is a vertical transfer shift register that generates a pulse train for driving the direct charge transfer element 12; 17 is vertical transfer shift register 1
6 pulse train to the desired voltage, vertical pulse line 5
1 is a buffer circuit that outputs the output to the vertical charge transfer element 12 through 1, and 18 is a vertical shift register that turns the photogates 15 in the same row into a 1 on' state.

19 is a transfer gate for switching between the vertical charge transfer element 12 and the horizontal charge transfer element 13; 20H and 220V are storage regions; 21H and 21V are transfer regions; ,
In one horizontal charge transfer element 13, provided for each column,
Constitutes one transfer stage. 50 is a vertical gate line that sends the output from the vertical shift register 18 to the photogate 15 in the same row, and 51 is a vertical pulse line that sends the output from the buffer circuit 17 to each transfer stage of the vertical charge transfer element 12.

The horizontal charge transfer element 13 includes US Pat. No. 40329
52, an embedded charge transfer element comprising two-layer polysilicon electrodes and performing two-phase drive.

For one vertical charge transfer element 12, a buried charge transfer element made of a two-layer polysilicon electrode is used.

Vertical transfer shift register 16 and vertical shift register 18
is composed of a two-phase ratioless dynamic shift register described in Japanese Patent Application No. 53-69793.

The buffer circuit 17 includes an inverter circuit that outputs the signal input from the vertical transfer shift register 16 to each vertical pulse line 51.

The timing of driving the solid-state image sensor shown in FIG. 2 is as follows.
This is a case where the vertical photodiodes 11 have the minimum number of 485 photodiodes corresponding to the standard NTSC system, and for convenience of explanation, the potential of the vertical pulse line 51 is set to the horizontal charge transfer element 1.
3, Vl, V2. V3.・・・・・・
...Indicated by v485.

Further, the potential of a certain vertical gate line 50 is indicated by VP, the potential of the transfer gate 19 is indicated by TG, the potential on the electrode of the horizontal charge transfer element 13 is indicated by H1, and the horizontal blanking pulse is indicated by HB L.

The potential of the vertical charge transfer elements 12 etc. shown in FIG. 3 is determined by the potential of each transfer stage (1, 2, . . .
...n..., 485), transfer gate 19 (TG),
Each potential below the first transfer stage electrode (Hl) of the horizontal charge transfer element 13 is shown. Note that the black portion in the figure is a signal charge (the same applies hereinafter).

Now, at a certain time in the horizontal scan including the horizontal blanking period, the vertical shift register 18 moves to the n-th vertical gate line 50 (
When a voltage is applied to VP) to turn on the photogate 15, the signal charge accumulated in the photodiode 11 is
Transfer to the vertical charge transfer element 12 side. At this time, since a high voltage is applied to all the vertical pulse lines 51, the signal charge is applied to one selected vertical gate line 51 according to the amount of charge.
The charge is accumulated over a plurality of transfer stages of nearby vertical charge transfer elements 12 (1-11 in FIG. 3).

Thereafter, by operating the vertical transfer shift register 16, the voltage of the vertical pulse line 51 is lowered for each transfer stage starting from the 485th row, which is farthest from the horizontal charge transfer element, and the resulting potential barrier is used to transfer the vertical charge. 1 inside the element 12
Move closer to the row (t=tzpt3 in Figure 3)
)-When the potential barrier reaches the transfer stage near the n-th row where signal charges are accumulated, the signal charges are transferred to the next stage. If the storage region 20v of the next stage is full of signal charges at this time, the signal charges are transferred to the empty transfer stages (accumulation region 20v of the next stage) (t=t in Fig. 3).
4).

Every time the operation at t=t4 is repeated, the vertical charge transfer element 1
The signal charges in the horizontal charge transfer element 13 are sequentially sent in the direction of the horizontal charge transfer element 13. In parallel with these operations, the signal charges in the horizontal charge transfer element 13 that have been transferred from the n-1th row is transferred in the direction of the output unit 14 and output, and at the time of the horizontal blanking period, the horizontal charge transfer element 13
There is no signal charge inside.

When entering the horizontal blanking period, transfer gate 19 (TG
) is applied to turn it into the 'on' state, and at the same time, a voltage is also applied to the electrode (Hl) of the horizontal charge transfer element 13 so that the signal charge is transferred from the vertical charge transfer element 12 to the horizontal charge transfer element 13.
Allow movement to the side (t = t 5 in Figure 3)
), when the signal charge starts to be transferred to the horizontal charge transfer element 13, assuming that the vertical pulse line 51 which is at a low voltage is in the m-th row, the signal is transferred to each transfer stage between the l=m-1 rows. This means that charge is accumulated.

After this, by the operation at t=t4 in FIG. 3, the signal charge is further sent to the horizontal charge transfer element 13 side, and when the potential Vt of the vertical pulse line 51 in the first row becomes a low voltage, Vertical charge transfer is completed, and the signal charges in the n-th row are transferred below the electrode H1 of the horizontal charge transfer element 13 (t=tstt7 in FIG. 3).

Next, the voltage of the transfer gate 19 is lowered and turned off, and the horizontal charge transfer element 13 returns to a state in which transfer output is possible, and the readout operation of the signal charges in the n+1 row is stopped at t.
Start in the same way as steps 1 to t7.

In this way, the signal charge is transferred to m− of the vertical charge transfer element l2.
It is sufficient to distribute the information to one transfer stage, accumulate it, and transfer it. As a result, the storage capacitance required for each transfer stage of the vertical charge transfer element 12 can be reduced to 1/(m-1) compared to the conventional method, and the area of the vertical charge transfer element 12 region can be greatly reduced. , the aperture ratio can be dramatically increased. Note that the above effect can be sufficiently obtained regardless of the electrode structure of the horizontal charge transfer element 13. Similarly, vertical transfer shift register 16. Buffer circuit 17. Vertical shift register 1
8, without depending on the specific circuit configuration of each.
You can get enough. Further, in the embodiment, a case has been described in which the storage region 20V and the transfer region 21V are provided in one transfer stage, but the transfer region 21V may not be provided.

Next, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6.

FIG. 5 is a timing diagram of drive pulses similar to FIG. 2;
FIG. 6 is a potential diagram of the vertical charge transfer element 12 similar to FIG. 3. Note that in both figures, only timings t 1 to t 3 are shown for convenience of explanation.

In the circuit operation shown in FIG. 1, the voltage of each transfer stage changes from high to low with the accumulation region 20 of each transfer stage in the vertical charge transfer element 12 filled with signal charges, and the signal charges are transferred. Ru. At this time, if the potential under the electrode of the previous stage is low, the potential barrier under the transfer region 21 of the transfer stage is modulated by the electric field of the previous stage, and charges flow in the opposite direction to the transfer direction, resulting in a decrease in transfer efficiency. occurs.

In this case, as shown in FIGS. 5 and 6, first, n+
Transfer of signal charges starts from the transfer stage of one row, and signal charges are accumulated in a plurality of transfer stages including n rows (t=t1 in FIG. 6). Next, the potential under the electrode of row n becomes high, and signal charges are transferred from the transfer stage of row n (t=t2 in FIG. 6).

At this time, the potential under the electrode of the (n+1)th row remains high, thus preventing charge from flowing backward from the (n) row to the (n+1) row. After completing the charge transfer from the nth row, n+1
The potential of the row is lowered to become a signal charge accumulation state for the fifth-order transfer (t=t3 in FIG. 6).

In this way, by repeating the operation of changing the potential of each transfer stage from high to low while the potential under the electrode of the previous stage is high (potential is low), it is possible to prevent charges from flowing in the opposite direction. vertical charge transfer with high transfer efficiency.

Next, a third embodiment of the present invention will be described with reference to FIGS. 7 and 8.

FIG. 7 is a timing diagram of drive pulses similar to FIG. 2;
FIG. 8 is a potential diagram of the vertical charge transfer element 12, etc., similar to FIG. 3.

In the circuit operation shown in FIG. 1, the channel width of the vertical charge transfer element 12 becomes extremely narrow, which may reduce charge transfer efficiency.

In this case, as shown in FIGS. 7 and 8, when the signal charge is first transferred from the transfer stage in the fourth row, a small portion of the signal charge is left behind in the transfer stage in the fourth row. (t=tl in FIG. 8). Next, signal charges are transferred from the transfer stage in the third row. At this time as well, a small amount of signal charge is left behind at the transfer stage in the third row (t=t 2 in FIG. 8), and is further transferred from the transfer stage in the second row. From this time, the potential of the transfer stage in the fourth row is raised again, and at time t1, the charge remaining in the transfer stage in the fourth row is transferred to the transfer stage in the third row (t = t 3 in Fig. 8). After that, the signal charges in the first row are transferred to the horizontal charge transfer element 13, and the charges remaining in the third row from the previous transfer are transferred to the second row (1=14 in FIG. 8).

After this, similar two-stage transfer is performed in all transfer stages, and at the end of vertical charge transfer, all signal charges are sent to the horizontal charge transfer element 13 with low transfer loss (see Fig. 8). t=t6).

In this way, the transfer efficiency can be improved by outputting a plurality of pulse trains from the vertical transfer shift register 16 during the -horizontal scanning period and performing the vertical charge transfer operations in FIGS. 2 and 3 multiple times. I can do it. Note that, as long as the number of pulse trains is two or more, sufficient effects can be obtained by this method.

Further, the time interval of the pulse train is determined by the vertical shift register 18.
Any value may be used as long as it is twice or more the shift period of the pulse train output from the pulse train.

Next, a fourth embodiment of the present invention will be described with reference to FIG.

FIG. 9 is a circuit diagram of a solid-state imaging device in which one transfer stage of the vertical charge transfer device 12 is provided for every two photodiodes 11.

In the circuit shown in FIG. 1, the horizontal scanning repetition period is always 17 so that the signal charges in the n row and the n+1 row are not mixed.
It is necessary to complete the vertical charge transfer within the range. Now, assuming that the number of transfer stages of the vertical charge transfer element 12 is Nv, the scanning frequency fV of the vertical transfer shift register 16 needs to satisfy the first-order equation (1).

fV≧Nv/Tv ”・(L) Also, one transfer stage in the vertical charge transfer element 12 is provided for each photodiode 11.

The number of pixels in the vertical direction ny of the photodiode 11 and the number of transfer stages NV of the vertical charge transfer element 12 are equal, but as the number of pixels in the vertical direction nv increases as in a high resolution solid-state image sensor, the number of transfer stages NV also increases. In addition, the vertical transfer shift register 16 shortens the horizontal scanning repetition period TV.
The scanning frequency fV increases, and the efficiency of vertical charge transfer decreases.

In this case, as shown in FIG. 9, by providing one transfer stage in the vertical charge transfer element 12 for each of the plurality of photodiodes 11, the scanning frequency fv of the vertical transfer shift register 16 is reduced. That is, vertical charge transfer element 1
Inside 2-1, there is one for every two photodiodes 11.
A transfer stage is provided, and from the vertical transfer shift register 16, a buffer circuit 17. Through the vertical pulse line 51, one output is sent out to one transfer means corresponding to two photodiodes 11. Note that the operation of one circuit is the same as that in FIG. 1 described above.

As a result, the number of transfer stages of the vertical charge transfer element 12-1 is reduced to 1/2 compared to the case of FIG. 4, and the scanning frequency fV is reduced to 1/2.
/2, the efficiency of vertical charge transfer can be improved. Note that even if one transfer stage is provided for two or more photodiodes ll, the effect of this method can be sufficiently obtained.

Next, a fifth embodiment of the present invention will be described with reference to FIGS. 10 and 11.

FIG. 10 is a timing diagram of the driving pulses shown in FIG. 1;
FIG. 11 shows the transfer stages (1, 2, 3, . . . , etc.) of the vertical charge transfer element 12 at the timing shown in FIG. 10.

485) is a potential diagram of the transfer gate 19 (TG) and the horizontal charge transfer element 13 (Hl).

What is the smear phenomenon in CCD solid-state image sensors?

This occurs because the load generated in the device substrate during the vertical charge transfer process is collected in the potential well of the vertical charge transfer element 12, so smear will not occur unless the potential well exists. Therefore, as shown in FIGS. 1O and 11, potential wells are formed only in the plurality of transfer stages that accumulate and transfer charges.

By moving this potential well, signal charges with reduced amount of smear contamination are transferred.

First, at tl in FIGS. 1O and 11, the potential of all the vertical pulse lines 51 from the 3rd row to the m+1th row is raised to form one potential well under the electrode of each corresponding transfer stage. Then, signal charges are accumulated in this. Note that 1 m is a value obtained by dividing the time during which the potential of the vertical pulse line 51 is at a high level by the shift period of the vertical transfer shift register 16, and determines the length of the potential well to be formed. Further, at this time, a low voltage such that the potential under each electrode becomes equal to the substrate potential is applied to the vertical pulse lines 51 in the rows other than the above, so that no potential well is formed (tr in FIG. 11).

Thereafter, the potential of the vertical pulse line 51 in the m+1 row is increased to transfer signal charges, and the transfer stage in the second row is newly brought into the potential well range (tl in FIG. 11).

By repeating the above operation, the potential well is moved and the signal charge is transferred from the vertical heavy transfer element 12 to the horizontal charge transfer element 1.
3 (j3+1, + in FIG. 11). As a result, the storage capacitance required for each transfer stage of the vertical charge transfer element 12 can be reduced to 1/(m -1) vertical charge transfer element 12
It becomes possible to greatly reduce the area of the region, and the ratio of openings can be dramatically increased.

In addition, the number of potential wells in which smear charges accumulate is reduced from the conventional (m
1)/Nv, smear can also be significantly reduced6.For example, when the above ratio is 1150, it is possible to improve by about 34 dB.

In this embodiment, since the signal charge of the photodiode 11 is transferred to the vertical charge transfer element 12 when a potential well is formed in the vertical charge transfer element 12, the time at which the photogate 15 is turned on is determined for each row. You need to choose.

This selection can be easily realized by providing a synchronous circuit outside the element. Also.

The pulse train over multiple (m) shift periods of the vertical transfer shift register 16 is 1, for example, according to Japanese Patent Application Laid-Open No. 53-6979.
It is sufficient to use the shift register described in Publication No. 3, select the feedback period to be m, omit the buffer circuit 17, and directly output the signal to the vertical pulse line 51.

Next, a sixth embodiment of the present invention is shown in FIGS. 12 to 14 (a).
) and (b).

Fig. 12 is a circuit configuration diagram of a solid-state image sensor using a two-pixel time readout method and a smear differential method, Fig. 13 is a timing diagram of the drive pulses in Fig. 12, and Fig. 14 (a).
is a potential diagram of the vertical charge transfer element 12 at timing jl+t2 in FIG. 13, and (b) is the sweep gate (S G) at timing t2 to t8 in FIG.
and the drain (SD) and the lower electrode (Hl) of the horizontal charge transfer element 13.

It is a potential diagram of transfer gates (TGI to TG3).

In FIG. 12, 31 and 32 are sweep gates and drains for discharging smear charges to the outside of the element, and 33 is synchronized with the output pulse from the vertical shift register 18 and performs row selection necessary for time readout between two pixels. L3-1 to 13-3 are first to third horizontal charge transfer elements, which are used to read out the first signal, second signal, and smear signal, respectively; 14-1-14; -3 is the first to third
The output parts of the horizontal charge transfer elements 19-1-19-3 are the first to third transfer gates, and the output parts 19-1-19-3 are the first to third transfer gates, respectively, between the vertical charge transfer element 12 and the first horizontal charge transfer element 13-1. and the second horizontal charge transfer element 13-1.13-2, and between the second and third horizontal charge transfer elements 13-2.13-3. As the interlace circuit 33, for example, a circuit described in Japanese Patent Application No. 57-144042 and Japanese Patent Application No. 55-54158 is used. Furthermore, parallel horizontal charge transfer elements are used for the horizontal charge transfer elements 13-1 to 13-3 in order to simultaneously read out two signal charges and one smear charge.

In FIG. 13, HBL, Vl ~ V485°Hl are the same signals as in FIG. 2, and vPl is a certain vertical gate line 51.
The potential VF6 is the potential of the other vertical gate vA51, and the timing differs depending on the row in which the signal is read. TO1 to TG3 are first to third transfer gates 19-
1 to 19-3, SG is the potential of the sweep gate 31.

In FIGS. 14(a) and (b), 41 is a smear charge swept out of the device, and 42 is a third horizontal charge transfer device 1.
3-3 is the smear charge read out, 43 is the nth row signal charge that is read out by the second horizontal charge transfer element 13-2, and 44 is the n+1st row signal charge that is read out by the first horizontal charge transfer element 13-1. It is a signal charge. In addition, ms in <a> of the same figure is the value obtained by dividing the time interval t m B between the smear sweeping pulse train and the smear readout pulse train shown in FIG. 13 by the shift period of the vertical transfer shift register 1G, and ml is the smear readout pulse train. The value 19m2 obtained by dividing the time interval tml between the first signal readout pulse train and the first signal readout pulse train by the shift period of the vertical transfer shift register 16 is the time interval tm2 between the first signal readout pulse train and the second signal readout pulse train. is divided by the shift period of the vertical transfer shift register 16.

The operation of this circuit is such that at a certain time during horizontal scanning including the horizontal blanking period, the vertical transfer shift register 16 sequentially lowers the potential of the vertical pulse line 51 for each transfer stage starting from the 485th row, and the vertical charge transfer element moving the first potential barrier within 12; after that.

After t m 8 hours, a second potential barrier is applied at its t m i
Afterwards, the third potential barrier is applied, and after tmz, the fourth potential barrier is applied, and so on, and so on, and so on, and so on, and so on, and starts moving in the vertical charge transfer element 12 sequentially from the 485th row. As a result, at a certain time of vertical charge transfer, m of the vertical charge transfer element 12 is
A first potential well that spans five transfer stages, and a second potential well that includes m1 transfer stages.

This means that a third potential well consisting of m2 transfer stages is formed.

When each potential well passes near a row selected by the vertical shift register 18 and the interlace circuit 33, the signal charge of each photodiode 11 is transferred to the corresponding photogate 1 according to the timing of an externally provided synchronization circuit.
A voltage is applied to 5 and transferred to the potential well in vertical load transfer element 12 . Note that the selection of each row is performed immediately before the shift of the fourth potential barrier in the previous scanning period is completed and the vertical transfer shift register 16 operates next.

After the signal charge is transferred from the photogate 15, the smear charge 41 to be swept from the first potential barrier to the first row transfer stage is read out to the horizontal charge transfer element 13 in the first potential well. The smear charge 42 is converted into a signal in the nth row in the second potential well. 1J43, and the signal charge 44 of the (n+1)th row is accumulated in the third potential well (t"tl in FIG. 14(a)).

Thereafter, when the pulse train from the vertical transfer shift register 16 moves by one transfer stage, each potential well also moves by one transfer stage (t = t 2 in FIG. 14(a)). By repeating this operation, the sweep Subegi smear charge 41. Smear charge to be read 42. First signal charge 43. horizontal charge transfer element 1 without mixing the second signal charge 44.
3-1 to 13-3.

When the first potential barrier approaches the first row, the smear charges 41 are sequentially swept out from the sweep gate 31 (t=t3 in FIG. 14(b)).

After this, during the horizontal blanking period, the sweep gate 3
1 is turned off, and charges are sent from the vertical charge transfer element 12 to the parallel horizontal charge transfer elements 13-1 to 13-3. First, the first transfer gate 19-1 is turned on', voltage is applied to the electrodes of the horizontal charge transfer elements 13-1-13-3 to lower the potential, and the smear charge 42 is transferred to the first horizontal charge. Transfer to transfer element 13-1 (Fig. 14 (
b) t=ta). Note that the transfer continues until the second potential barrier reaches the first row.

After this, the first transfer gate 19-1 is set to 1 off',
The electrode potential of the horizontal charge transfer elements 13-1 to 13-3 is increased, and a voltage is applied to the second transfer gate 19-2 to lower the potential.
The smear charge 42 within 1 is transferred under the electrode of the second transfer gate 19-2 (t=t5 in FIG. 14(b)). next,
The first transfer gate 19-1 is turned on again, voltage is applied to the electrodes of the horizontal charge transfer elements 13-1 to 13-3 to lower the potential, and the potential of the second transfer gate 19-2 is increased. The first signal 43 is transferred from the vertical charge transfer element 12 into the first horizontal charge transfer element 13-1, and the smear charge 42 is transferred to the second transfer gate 19-2.
to the second horizontal charge transfer element 13-2 (first charge transfer element 13-2).
t=t6 in Figure 4(b)).

When this operation is repeated and the fourth pulse train of the vertical transfer shift register 16 reaches the first row.

The third horizontal charge transfer element 13-3 has a smear charge 42, the second horizontal charge transfer element 13-2 has an n-th row signal charge 43, and the first horizontal charge transfer element 13-1 has a smear charge 42. n +
The signal charges 44 in the first row are transferred (14th
t=t7+ts in figure (b)).

During the horizontal scanning period, three horizontal charge transfer elements 13
-1 to ■3-3 operate simultaneously, resulting in a smear charge of 42. n
Output unit 1 outputs the signal charge of the row 44 and the signal charge 44 of the n+1 row.
Simultaneously output from 4-1 to 14-3.

After this, by subtracting the smear charge 42 from each signal charge 43.44, n rows where no smear charge is mixed, n+1
Only row signal charges can be generated. Furthermore, in the next field, interlaced scanning is possible by reading out the signal charges in rows n-1 and n.

In this way, the area of the vertical charge transfer element 12 can be reduced by forming a plurality of potential wells across multiple transfer stages of the vertical charge transfer element 12 and moving them to simultaneously transfer a plurality of charge packets. 2 without increasing
Both methods of inter-pixel time readout and smear differential can be realized. In this embodiment, three horizontal charge transfer elements 13-1 to 13-3 are arranged in parallel in order to read out the smear signal and the first and second signals. As long as it can be read, any number of interlace circuits 33, one or more, may be used. (2) The interlace circuit 33 can be used without depending on the specific circuit configuration. (2) This can be realized without carrying out the operation of sweeping out smear charges by the sweep gates and drains 31 and 32. ■The vertical transfer shift register l6' may start sending out a pulse train during the scanning period.1゜In the smear differential system used in this example, random noise generally increases due to arithmetic processing, /N ratio will be lowered. In the conventional method, the amount of smear mixed into the signal charge and the amount of smear when only the smear is read out are the same.
Total random noise Nt.

teeth.

Nt, 2 = Sn12 + Sn2 2
...”・(2). However, Snl, S
n2 is the amount of random noise mixed into the signal charge and smear charge, respectively.

If Snl 2=Sn22, the noise will increase by 3 dB due to the smear differential, but in this example, the smear amount mixed into the signal and the smear amount for the differential are ml:ms
, or m2':ms, and now.

If m 1 = m 2 =mm, the total random noise N't2 after smear differential is N''t2=Sn12+ +u+2・Sn22/ms2・
・It can be expressed as (3). In other words, the number of transfer stages ms of potential wells formed to accumulate and transfer signal charges
From the number of transfer stages +++m of potential wells formed to accumulate and transfer smear, Mine < L (ms> mm).

By making the amount of smear when extracting only the smear signal greater than the amount of smear mixed into the signal, it is possible to prevent an increase in random noise due to smear differential and obtain a high S/N ratio. In addition, ffl 1 r ITI 2 rm
The value of s should be any number greater than or equal to 2. Also, in this embodiment, as in the case of FIG. 11, a driving method is used in which the potential on the electrode of the vertical charge transfer element 12 in areas other than the area where the smear charge and the two signal charges are accumulated and transferred is made equal to the substrate potential. can do. Furthermore, in this embodiment, the smear charge sweeping operation can be made unnecessary, so the first
The sweep gate 31 and sweep drain 32 shown in FIG. 2 become unnecessary.

Next, a seventh embodiment of the present invention will be described with reference to FIGS. 15 to 17.

FIG. 15 is a circuit configuration diagram of the solid-state image sensor when the vertical shift register 18 is omitted, FIG. 16 is a circuit configuration diagram of one stage of the row selection circuit, and FIG. 17 is an operation timing diagram of FIG. 16. .

In FIG. 15, numeral 34 is a row selection circuit that functions as the vertical shift register 18 in FIG. Other numbers and operations for selecting a row of elements are the same as in FIG. 12 above.

In FIGS. 16 and 17, VPD is a row selection pulse for selecting a row, VSR is the output of the vertical transfer shift register 16 of a certain row, and V, v2 is a two-phase clock that drives the vertical transfer shift register 16. each one clock, V
R is a reset clock for resetting the row selection circuit, ■OUT is the output of the row selection circuit sent to the interlace circuit 33, T1 to T9 are MOS transistors,
, ゛ii′.

't is the node voltage.

The row selection circuit 34 selects only the first pulse in the pulse train of a certain row outputted (VSR) by the vertical transfer shift register 16, and performs the logical product of this pulse and the externally applied row selection pulse vpo. By this, row selection of the photodiode 11 is performed. First, when the first pulse is input from the vertical transfer shift register 16, the MOS
) - transistor Tl becomes conductive, the node A becomes a high voltage, and MOS transistor T2 also becomes conductive.

After that, when the clock vl is input, MOS transistor T2→node "I" becomes a high voltage→MOS transistor T3→node 1' becomes a high voltage→MOS transistor T4 becomes conductive.In this state, the vertical transfer shift register When a second pulse is input from 16, the MoS transistor T5 becomes conductive and the voltage at node 'A' becomes low.As a result.

MOS transistor T2 no longer becomes conductive, and the voltage at node I' remains low. That is, in synchronization with the first output pulse from the vertical transfer shift register 16, the voltage at node I' increases, and at this time, when the external row selection pulse VPD is input to the gate of the MOS transistor T6, the output vouT goes high to select a row of elements. Thereafter, a blanking period begins, and immediately before the vertical transfer shift register 16 operates, a reset clock vR is input to reset the row selection circuit 34.

In this way, by using the row selection circuit 34 and externally inputting a row selection pulse synchronized with the pulse train of the vertical transfer shift register 16, it is possible to select a row without using the vertical shift register 18. The number of elements can be reduced to simplify the element circuit.

Next, an eighth embodiment of the present invention will be described with reference to FIGS. 18 and 19.

FIG. 18 is a circuit configuration diagram of the solid-state image sensing device when the blooming phenomenon is suppressed, and FIG. 19 is a timing chart of the drive pulses shown in FIG. 18.

In FIG. 18, 35 and 36 are the gate and drain of the RAB circuit that suppresses blooming.

Other numbers are the same as in FIG. 12 above.

When strong light hits the solid-state image sensor, photodiode 1
1 becomes saturated and excess charge overflows into the vertical charge transfer element 12, in other words, a blooming phenomenon occurs, and as in the case of smear, a pseudo white band appears on the screen above and below the area hit by strong light. In this embodiment, the RAB circuit system described in Utility Model Application No. 130240/1980 is used to read out the signal charges accumulated in the photodiode 11 immediately before reading out the signal charges. A portion of the charge is swept out of the element and the unsaturated signal charge is read out to suppress the blooming phenomenon.

In this circuit, as shown in FIG. 19, in the period immediately before starting the next sending operation after a series of operations for sending out a pulse train by the vertical transfer shift register 16, first, the gate 35 of the RAB circuit is opened from the RG end. Apply a high voltage to RD, then RD
By applying a slight voltage to the drain 36 of the RAB circuit from the end, the photogates 15 of all pixels (photodiodes 11) are slightly opened, and a part of the saturated charge of the photodiodes 11 is flowed out to the vertical charge transfer element 12. After that, lower the voltage in the order of drain 36 → gate 35 of the RAB circuit,
The photogate I5 is closed. As a result, when reading out the smear charge and reading out the two signals, the photodiode 1
1 is in a state before saturation, so no blooming phenomenon occurs. Note that the charges flowing into the vertical charge transfer element 12 are swept out of the element together with the smear charges. Further, the subsequent operation is exactly the same as that shown in FIG. 12 above.

In this way, just before reading a signal from the photodiode 11, only the saturated charges are swept out of the element to bring the photodiode 11 into a non-saturated state, so that the blooming phenomenon can be suppressed.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of signal charges (m-
1) Since the area of the vertical charge transfer element region is reduced by distributing the charge transfer elements to the transfer stages, the ratio of the openings can be greatly increased, and the sensitivity is improved. In addition, the two-pixel time readout and smear differential method can be realized without reducing the aperture ratio or making the planar structure of one pixel area complicated or overcrowded, and the solid-state image sensor has high sensitivity.

High resolution, low smear, and high yield.

[Brief explanation of drawings]

1, 9, 12, 15, and 18 are circuit configuration diagrams of a solid-state image sensor showing one embodiment of the present invention, and FIGS. 2, 5, 7, and 10 13 and 19 are timing diagrams of driving pulses, and FIGS. 3, 8, and 11 are vertical charge transfer elements. Transfer gate, potential diagram of horizontal charge transfer element, 4th
The diagrams are circuit diagrams of conventional solid-state image sensors, Figures 6 and 14.
Figure (,) is a potential diagram of a vertical charge transfer element, the 14th
Figure (b) is a potential diagram of the sweep gate, drain, horizontal charge transfer element, and transfer gate, Figure 16 is a circuit configuration diagram of one stage of the row selection circuit, and Figure 17 is an operation timing diagram of Figure 16. . 1.11: Photodiode, 2, 12.12-1=vertical charge transfer element, 3.13.13-1 to 13-3=horizontal charge transfer element, 4, 14.14-1 to 14-1 output section, 5
, 15: Photogate, 16: Vertical transfer shift register,
17: Buffer circuit, 18: Vertical shift register, 19
, 19 1 to 19-3: Transfer gate, 20: Accumulation area, 21: Transfer area, 31: Smear sweep gate, 32:
Smear sweep drain, 33: Interlace circuit. 34: Row selection circuit, 35: RAB circuit gate, 36:
Drain of RAB circuit, 41: Smear charge to be swept out,
42: Smear charge to be read out, 43: Signal charge on the 'nth row, 44: Signal charge on the n+1th row, 50: Vertical gate line, 51: Vertical pulse line. Patent Applicant: Hitachi, Ltd. Figure 1 Figure 2 Figure 4 Figure 5, t1t2t3 Figure 6 Figure 7 Figure t5 Figure 8 Figure lO Figure Hl... Figure 11 Figure 15 Figure 18

Claims (11)

[Claims] (1) Photoelectric conversion elements arranged two-dimensionally, vertical charge transfer elements that transfer signal charges from the photoelectric conversion elements in the vertical direction, and horizontal transfer elements that transfer the signal charges from the vertical charge transfer elements in the horizontal direction. A solid-state image sensor including a charge transfer element, characterized in that the solid-state image sensor includes a shift register that sends out a pulse train for transferring signal charges in the vertical charge transfer element to the horizontal charge transfer element within one horizontal scanning period. . (2) The shift register sends pulses to be transferred to each transfer stage of the vertical charge transfer element from the time when the transfer is being sent to the previous stage of the transfer stage until after the sending to the previous stage has ended. A solid-state image sensor according to claim 1, characterized in that: (3) A patent claim characterized in that the shift register sends a pulse to be transferred multiple times within one horizontal scanning period to each transfer stage of the vertical charge transfer element in order to transfer one signal charge. The solid-state imaging device according to the range 1 above. (4) A patent characterized in that the shift register sends a pulse to be transferred multiple times within one horizontal scanning period to each transfer stage of the vertical charge transfer element in order to transfer a plurality of signal charges. A solid-state imaging device according to claim 1. (5) The solid-state image sensor according to claim 1, wherein one transfer stage of the vertical charge transfer element is provided for a plurality of the photoelectric conversion elements. (6) When the transfer stage of the vertical charge transfer element does not form a potential well, the potential under the electrode of the transfer stage is set to the potential of the mounting board. element. (7) In order to sweep out pseudo signals such as smear in the vertical charge transfer element to the outside of the element, a sweep means consisting of a sweep gate and a sweep drain is connected to the vertical charge transfer element and the horizontal charge transfer element. A solid-state image sensor according to claim 1, characterized in that the solid-state image sensor is provided between. (8) The solid-state imaging device according to claim 1, further comprising smear differential means for differentially controlling the signal charge and smear charge sent out from the horizontal charge transfer device. (9) The smear differential means is characterized in that the signal charge and the smear charge are differentially transferred within one horizontal scanning period and the amount of smear charge mixed in the signal charge is smaller than the output amount of the smear charge. A solid-state imaging device according to claim 8. (10) A selection signal synchronized with a pulse train of a shift register that sends out a pulse train for transferring signal charges in the vertical charge transfer element to the horizontal charge transfer element within one horizontal scanning period is received from outside the element, and the photoelectric conversion is performed. The solid-state image sensor according to claim 1, further comprising row selection means for selecting a row of elements. (11) Immediately before the start of operation of a shift register that sends out a pulse train for transferring signal charges in the vertical charge transfer element to the horizontal charge transfer element within one horizontal scanning period, the charge in the photoelectric conversion element is brought into a non-saturated state. The solid-state image sensor according to claim 1, further comprising a reset means for.