JPS61180998A - Dynamic rom circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an integrated circuit having a dynamic ROM circuit, such as a microcomputer integrated on one chip, having a dynamic ROM circuit configured with N-type and P-type MOS transistors. The present invention relates to means for improving the operating speed of the ROM circuit.

BACKGROUND ART FIG. 2 shows a conventional dynamic ROM circuit having N-type and P-type MOS transistors, in which 16 is a row decoder, 17 is a word line, 18 is a bit line, and 19 is an enhancement type MOS transistor ( Below MO3Tr
), 2o is enhancement WM O5Tr12
1 is enhancement type MO8Tr, 22.23.24
．． 25 and 26 are enhancement type MO8Tr.

AI and A2 indicate part of the word line, and Dl indicates part of the bit line. FIG. 3 is a timing diagram of the circuit shown in FIG. 2, in which word line 17 is set to a predetermined word line due to clock pulses φ1 and φ2! , M2 and the voltage of a predetermined bit line D1 of the bit line 18 are shown in a timing diagram.

In FIG. 2, word line 17 of row decoder 16 is activated by clock φ1. Regarding the predetermined word line input 1 and A2 of the word lines 17, when the clock φ is "H", a change in the state of the word line input 1 and person 2 occurs. In the timing diagram of FIG. 3, the initial state of a predetermined word line connection is "L", and when the clock φ1 becomes "°H", the state of the word line connection changes from "L" to 11 HI+. Furthermore, when the clock φ1 becomes 1ll (+1) for the second time, the state of the word line ON changes from "H" to "L11".Similarly, the initial state of another word line A2 is IIL.
+1, and when the clock φ1 becomes "H", the state of the word line A2 becomes "L 11" and does not change.Furthermore, when the clock φ1 becomes "'H" for the second time, the state of the word line A2 becomes "L11" and does not change.
The state changes from "[1" to ``H''.

Further, the enhancement type MO8Tr21 in FIG. 2 is activated by the clock φ1, and all the bit lines 18 are set to "H". At this time, the bit line 18 is connected to the enhancement type MO
It is said that it is precharged with 3Tr20, and this mechanism is called a precharge mechanism. Regarding bit line D1,
When clock φ1 is (NHTT), MO3Tr21 is turned on and precharged. In the timing diagram of FIG. 3, the initial state of bit line D0 is "I, ++, and when clock φ1 becomes IIHI+, the same bit Line D
The state of 1 changes from "L" to "'H". Furthermore, when the clock φ1 becomes "H" for the second time, the state of the bit line D1 changes from "L" to "H11".

Next, when clock φ2 is activated, word line 17 is already activated.
The bit line 18 having a current path to OV is discharged through the MOSTr which is turned on by activation of OV.

Bit lines 18 for which transistors are not arranged for the accessed word remain in a precharged state. Looking at the predetermined bit line D1 in FIG.
When clock φ1 becomes “H”, word line A goes “H”,
The word line A2 becomes "L", the MOSTr22 is turned on, and the M05Tr23, 26, and 26 are turned off. Next, when clock φ2 becomes “H′ν, MO8Tr
20 is turned on, and the bit line D1 is turned on.
A current path to Ov is created through the 8Tr22, and the current is discharged. In other words, the read data becomes "L, ++. When the clock φ1 becomes "H" for the second time, the word line A1 becomes "L".
”, word line A2 (mo3Tr227)
;Off state, MO3Tr23.25.26 becomes on state. Next, clock φ2 is 11)! When it becomes I+, M
OSTr 2 o is turned on and bit line D1 is O
Since there is no current path to v, it remains at "'H". That is, the read data becomes ≦1)1+1.

Problems to be Solved by the Invention However, the above conventional dynamic ROM circuit has the following problems. That is, if the clock φ2 is activated with all the bit lines 18 of the ROM precharged while the clock φ1 is active, the bit that has a current path to Ov through the transistor that has already become conductive due to the activation of the word line 17 The time that line 18 discharges determines the operating speed of the read cycle. For this reason,
To increase the operating speed of the ROM read cycle, MO8Tr22.23.24.25.26 and MO5T
It is necessary to increase the current driving capability of the current path configured by r20. 2 in the integrated circuit is MO3Tr20122
．． The geometric size of 23.24.26.26 increases, making it unsuitable for high-density integrated circuits.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a dynamic ROM circuit that is suitable for high-density integrated circuits and has a fast read cycle operation speed.

Means for Solving the Problems In order to solve the above problems, the present invention provides a pair of MO8Tr corresponding to the load transistors at the drains of the load transistors for precharging the bit lines, and connects the sources of the MO5Trs. The line connecting the drain of MO5Th- is connected to the power source, the line connecting the gate of MO5Th- is connected to the source of the load transistor connected to the power source, the gate and drain of MO8Tr are connected to the source of the load transistor, and the source of MO3Tr is connected to the source of the load transistor. By connecting to the drain and gate of MO8Tr and grounding the source of MO3Tr,
The time required for the bit line voltage to drop from the precharge voltage to the input switching level of the MOS circuit connected to the bit line by lowering the bit line precharge load transistor drain (D voltage) and lowering the bit line precharge voltage. This reduces the read cycle time of a dynamic ROM circuit, which is determined by .

Operation The present invention uses the circuit configuration described above to reduce the read cycle time of the dynamic ROM in order to lower the bit line precharge voltage.
．． without increasing the geometric size of 25.26.
It is suitable for high-density integrated circuits because the time required for bit line precharging does not increase. Generally, when the threshold voltage Vτ of MO3Tr increases, the read threshold voltage of ROM also increases. When the circuit of the present invention is adopted, when the threshold voltage VT of the MOSTr increases, the precharge voltage also increases automatically, and there is an advantage that process variations can be automatically compensated for.

Example FIG. 1 shows an embodiment of the invention.

1 is a row decoder, 2 is a word line, 3 is a bit line, 4 is an enhancement WM OSTr, 5 is an enhancement type MO3T36 is an enhancement type MO8Tr,
7.8.9.10.11 is enhancement type MO8T
r112.13.14 is enhancement type M O5T
r116 is a depression type MO8Tr. A...
A2 indicates a part of the word line, and D2 indicates a part of the bit line.

φ1 and φ2 are clocks shown in FIG. The timing diagram of FIG. 3 can be applied to the circuit of FIG. A timing diagram shows voltage changes.

The operation of the dynamic ROM circuit configured as above will be explained below.

A power supply is connected to the connecting line, and a line connecting the gate of MO5Tr12 is the load transistor 1 connected to the power supply VDD.
The gate and drain of MO8Tr13 are connected to the source of the load transistor, and the gate and drain of MO8Tr13 are connected to the source of MO3Tr1.
The source of MO3Tr14 is connected to the drain and gate of MO3Tr14, and the source of MO3Tr14 is grounded.

FIG. 4 shows the relationship between bit line voltage and time in a read cycle of a dynamic ROM.

The read cycle time of a dynamic ROM is the time required for the voltage of the bit line to drop from the precharge voltage to the input switching level of the MOS circuit connected to the bit line, as shown in FIG. The input switching level of a MOS circuit is constant from process to process without special design.

For example, in the case of an N-type MOS transistor operating at 5V, the voltage is approximately 1.5V. Furthermore, it can be seen that the discharge curve is determined by the geometric dimensions of the MOS transistor, and that it is sufficient to lower the geometric voltage. FIG. 4 shows the case where the person does not lower the precharge voltage, and B shows the case where the precharge voltage is lowered. B
It can be seen that the reading time is shorter for T than for humans.

The effect of MO8Tr12.13.14.15 will be explained with reference to FIG. As shown in Fig. 6, if a depletion type MO3Tr with its gate and source connected is used as the load transistor 1S, and vl, v2, and v3 are the voltages at the points shown in the figure, MO8Tr13 and 14 have their drains and gates connected, respectively. Since the source and gate are connected, the MO3Tr15 operates in the saturation region characteristics of the MOSTr, and if the source-gate voltage is VaS, it operates at v,5=Ov, and the threshold voltage of the MO3Tr15 is If VT is VT, and Δv1 is the threshold variation due to the back gate bias effect of MOSTr, then since the operating condition of MO3Tr is VG3≧VT, V t =V T ,
V 2 =VT+ V7+ΔvT=2vT+2sVas
≧Vdotearuka, V3”:V2 V〒=V'r+Δv
T tonal. Temporary Kt source vDD wo 5 V, v ding 1,5
v, ΔV? If is 1v, then V,=1.5V1vz=
41%V3=2.57/.

Next, in FIG. 1, word line 2 of row decoder 1 is activated by clock φl. Regarding predetermined word lines A1 and A2 of word line 2, clock φ1 is ≦l l
(When +1, the state of each word line INPUT 1 and MMU 2 changes. In the timing diagram of FIG. 3, the initial state of word line INPUT 1 is "L", and when the clock φl becomes "H", The state of the word line A1 changes from il], +7 to "H".

Furthermore, when the clock φl becomes "H" for the second time, the word line input state changes from "IIH" to "L".Similarly, the initial state of the word line A2 is "L'", and the clock φ
1 becomes “°H”, the state of word line A2 becomes “L”
and does not change. Furthermore, clock φ1 becomes H″ for the second time.
Then, the state of the word line A2 changes from "L" to "H".

The enhancement type M O5Tr5 in Figure 1 is Kuro-1.
The bit line 3 is activated by the link φl, and all bit lines 3 are set to "H". Regarding bit line D2, clock φ1 is “H”
At this time, MO5Tr5 is turned on and precharged. In the timing diagram of FIG. 3, the initial state of the bit line D2 is "L", and when the clock φl becomes "H", the state of the bit line D2 changes from "L" to "H".

Furthermore, when the clock φl becomes "H" for the second time, the state of the bit line D2 changes from "L" to "H".

The H level of the bit line D2 means that the drain voltage of MOiSTr5 is v+Δv! If the H level of φ1 is "DD", the operating condition of MOSTr5 is VGS≧V, and then "DD (vT+ΔvT)?" If there is vTte, then V
It becomes T+ΔvT. In normal processes, this condition holds true.

Next, when the clock φ2 is activated, the bit line 3, which has a current path to OV through the MO3Tr which is already on due to the activation of the word line 2, is discharged. Bit lines 3 for which transistors are not arranged for the accessed word remain in a precharged state. Regarding bit line D2 in FIG. 3, clock φ1 is 1"H.
``When it comes to K, the word line person is 4''H, the word line person is 2''
°L is turned on, MO3Tr7 turns on, and MO
8Trs, IQ, and 11 are turned off. Next, when the clock φ2 becomes “H”, MOSTre turns on, and the bit line D2 is turned on through the on-state MO5Tr6.
A current path to v is created and discharged. In other words, the read data becomes “L + j.The clock φ becomes “H” for the second time.
”, word line A1 becomes (“L”, word line input 2 becomes “H1”, M O5Tr7 is off, M O
5Trs, 1o, and 11 are turned on. Next, when the clock φ2 becomes "H", the MO8Tr and others are turned on, and the bit line D2 remains "HT" because there is no current path to Ov. That is, the read data becomes "H".

One of the factors that determines the read cycle time is the bit line precharge voltage. In the circuit of FIG. 2, the bit line precharge voltage is VDD-%, and in the circuit of FIG. 1, it is +ΔV. Bit line 3 is MO3
``The time required for the voltage to be discharged through Tr6 and lowered to a voltage sufficient for switching the next stage MO3 circuit is short because the precharge voltage of bit line 3 is low.For example, if the power supply Vt1D is 6V and V is 1V. , 47 is set to 2V, and the switching voltage of the MO8 circuit in the next stage is set to 1.6V.The time it takes for the bit line precharge voltage to drop to 1.5V is approximated by the voltage dropping as a linear function of time. Then, the bit line precharge voltage of the conventional circuit is 4V,
Since the circuit of the present invention has a voltage of 3V, if the voltage of the conventional circuit is 1, the voltage of the circuit of the present invention is 0.6, and the time is shortened by 40%. Therefore, the operating speed of the dynamic ROM read cycle is increased by 40q6. Bit line D2 shown in FIG.
At the timing, T1 indicates the difference in read cycle time between the conventional circuit and the circuit of the present invention.

In general, when the threshold voltage vT of MO8Tr increases,
The read threshold voltage of the ROM also increases.

In the circuit of the present invention, the bit line precharge voltage is V〒
+ΔV, and when the voltage increases, the bit line precharge voltage automatically increases, which also has the advantage of automatically compensating for process variations.

Effects of the Invention The dynamic ROM circuit of the present invention newly uses MO3Tr.
By providing a circuit for bit line precharging, M
By lowering the voltage at the drain of the OSTr and lowering the precharge voltage at the bit line, it is possible to speed up the read cycle, and because the time required for precharging does not increase, the chip size does not increase and high-density integrated circuits are realized. It is suitable for use and has great practical effects.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a conventional dynamic ROM circuit diagram, Fig. 3 is a timing diagram, and Fig. 4 is a timing diagram.
The figure is a characteristic diagram of the relationship between voltage and time of a read cycle, and FIG. 5 is a circuit diagram of the main part of an embodiment of the present invention. 1... Row decoder, 2... Word line,
3... Bit line, 4... Enhancement WM O5Tr15... Enhancement WM O5Tr16... Enhancement type MO8
Tr, 7.8.9.10, 11...Enhancement WM OSTr, 12.13.14...
・・Enhancement 9M OSTr, 1s・River・
・Depression 5M OSTr, 1e...
・・Row Te: + - Da, 17... Word line, 18
・・・・・・Bit line, 19th enhancement type MO3
Tr, 20...Enhancement type MO3Tr
, 21...Enhancement type MO5Tr, 2
2.23.24.25.26...Enhancement type MO3Tr. Name of agent: Patent attorney Toshi Nakao, Idiot 1
Fig. 2-He'7-)-)'K3-1-(To the 5th figure

Claims (2)

[Claims] (1) In a dynamic ROM circuit configured with N-type and P-type MOS transistors, a pair of MOS transistors corresponding to the load transistors are provided at the drains of the bit line precharge load transistors, and their sources are connected to the drains of the MOS transistors. A dynamic ROM circuit characterized in that a power source is connected to a line connecting the drain of the MOS transistor, and a line connecting the gate of the MOS transistor is connected to a voltage source divided from the power source. (2) A patent claim characterized in that a voltage source connects one or more MOS transistors with gates and drains connected in series to a resistor connected to a power source, and uses the voltage between the terminals of the MOS transistors. Dynamic ROM circuit according to scope 1.