JPS61196579A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To position source and gate regions and a gate region to be interposed therebetween in a predetermined positional relation (self alignment) and to set an offset precisely and uniformly, by utilizing first and second mask layers in combination. CONSTITUTION:A semiconductor substrate S is provided thereon with a first mask layer 3 having a predetermined width W corresponding to the length of a gate. A second mask layer 4 is further provided on the layer 3. The first mask layer 3 has, in its sections adjacent to the opposing side faces 3a1 and 3a2, a thickness d1 sufficiently larger than a thickness d2 in the other sections, and a width Ws in these thicker sections 4a is determined corresponding to an interval (offset) between gate and source regions and between gate and drain regions. The interval between the source and drain regions 5 and 6 is determined corresponding to the sum of the width Ws of the thicker section 4a and the width W. The second mask layer 4 is etched to expose the first mask layer 3, and a window 4W is opened in the second mask layer 4. A gate region 8 is provided while forming a gate junction J. The offset is set to be a predetermined narrow interval Wo.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device, particularly a semiconductor device that is used to obtain a single semiconductor device or a semiconductor integrated circuit having various field effect transistors having a junction type gate portion. Related to manufacturing method.

[Summary of the invention]

In obtaining a field effect transistor whose gate portion is a junction type gate portion, the present invention forms a field effect transistor by forming source and drain regions with a predetermined offset amount on both sides of the junction type gate portion. In order to obtain a gate, first and second masks having different etching properties are used.First, the first mask is selectively formed at the position where the gate portion will ultimately be formed, and then the first mask is formed on top of the first mask. By forming the second mask to a required thickness, a thick portion is finally formed with a width corresponding to the amount of offset of each source and drain region with respect to the gate portion, and then, using these masks, , forming a source region and a drain region.

Then, a window is formed by removing the first mask and a second mask thereon, and a gate junction is selectively formed through this window to change the positional relationship between the gate junction and the source and drain. Line up.

[Conventional technology]

Conventionally, when obtaining a field effect transistor having a junction type gate part, the gate part and the source and drain regions placed between the gate part and the source and drain regions are formed in a semiconductor substrate using independent ion implantation or diffusion masks. This is done by an independent impurity introduction operation using

[Problem that the invention seeks to solve]

As mentioned above, when obtaining a conventional field effect transistor having a junction type gate part, the gate part and each source and drain region are formed by selectively doping impurities independently. Problems include the positional relationship between the source and drain regions, that is, the amount of offset, which tends to vary, and it is not possible to select a sufficiently small offset amount taking into account errors in mask alignment for selective formation of each of the two regions. In the field effect transistor formed in this manner, there are problems such as a relatively large gate-source resistance and difficulty in obtaining uniform characteristics with good reproducibility.

[Means for solving problems]

In the present invention, a first mask, for example, an SiO
2 is selectively deposited.

Then, a second mask, such as SiN, having different etching properties, for example, a different etching solution, from the first mask is deposited. In this case, by selecting the thickness of this second mask layer to a required thickness, the desired width on both opposing sides of the first mask, that is, the source and drain regions and gate regions to be finally obtained can be obtained. A second mask layer, which is thicker than other parts, is coated on at least the first mask and both sides thereof with a width corresponding to the offset amount between the source and drain regions and the gate region. A second mask is formed over a large width, that is, over the portion where the source and drain regions will ultimately be formed. Then, using the first and second masks, especially the first mask and the thick portions of the second mask on both sides thereof as masks, impurity ions are implanted into the source and drain regions using a predetermined implantation energy. Then, source and drain regions are formed. The first mask is then removed and a gate region is selectively formed through the removed portion. In this way, a field effect transistor is produced in which the amount of offset between the gate portion and each of the source and drain regions is defined by the interval defined by the width of the thick portion on both sides of the first mask of the second mask, that is, Obtain a semiconductor device.

[Effect]

According to the present invention described above, the edges of the source and drain regions facing the gate portion are formed with a predetermined thickness on the first mask and on both side surfaces of the first mask. By removing the first mask, a gate part is formed in the part where the first mask part was formed, so that the gate part, that is, the gate junction and the source The positions of the source and drain regions are self-aligned, so that the offset between the gate region and the source and drain regions can be reliably and sufficiently small, and can be formed evenly and as designed.

〔Example〕

With reference to FIG. 1, a field effect transistor PI! according to the invention! An example of obtaining T will be explained in order of each step.

For example, semi-insulating compound semiconductor GaAs substrate (
A semiconductor substrate S is provided in which a semiconductor layer (2) of conductivity type 1, for example, n-type, is formed on the surface of substrate 1) to a required depth by full-surface ion implantation or the like. The semiconductor layer (2
) a first mask layer (3) is selectively formed thereon. This first mask layer (3) is made of, for example, 5i02 by CVD.
(Chemical Vapor Depositio
n) is formed on the entire surface by a method such as etching, and unnecessary parts are etched away by photo-etching, and a predetermined width W corresponding to the gate length is formed in the part where the gate part will finally be formed (see Fig. 1A). ).

Next, a second mask layer (4) is formed over the entire surface including the first mask layer (3) (FIG. 1B). This second
The mask layer (4) of the first mask layer (3), for example, is hardly attacked by an etching solution for SiO2, for example, an etching solution containing hydrofluoric acid. For example, Si
Similarly, N is formed by a CVD method or the like. In this case, by appropriately selecting the deposition thickness of the second mask layer (4), the opposing sides (3) of the first mask layer (3) can be
a1) The thickness dl at the part in contact with (3a2) is made sufficiently larger than the thickness d2 at other parts. Further, the width Ws of the thick portion (4a) having the thickness dl is determined by the distance between the final gate region and each source and drain region,
That is, it is set corresponding to the offset amount.

Next, impurity ions of the same conductivity type as the semiconductor layer (2) are implanted from the surface of the semiconductor layer (2) to form a source region (5) and a drain region (6) (FIG. 1C). The selective ion implantation of these source and drain regions (5) and (6) is performed using the first mask layer (3) and the second mask layer (4).
The impurity ions are implanted using each thick part of the semiconductor layer (2) as a mask and with an implantation energy that does not transmit through these parts (in other parts, the impurity ions can be implanted into the semiconductor layer (2)). The spacing between the source and drain regions (5) and (6), that is, the positions of the edges facing each other, is then annealed to activate the implanted ions. It is set corresponding to the sum of the valley width Ws of the thick portion (4a) of the mask layer (4) and the width W of the first mask layer (3).

Note that these source and drain regions (5) and (6)
For the ion implantation, if necessary, as shown in the figure, each region (5) and (6) is placed on the outer peripheral edge of the side facing the gate part, that is, on the so-called field part, or a photoresist or 5i02 is applied. The third ion implantation mask layer (
30) is selectively formed.

Next, the third mask layer (30) is removed, and a protective material layer (7) such as photoresist polyimide resin is coated on the second mask layer (4) so as to fill in the irregularities on the surface. (Figure 1D).

This protective material layer (7) is removed planarly from its surface to a uniform thickness by, for example, ion milling, 02 plasma, or whole surface exposure and development etching.
The second mask layer (4) is exposed on the first mask layer (3) and in the thick portions on both sides thereof (FIG. 1E).

Next, the second mask layer (4) is etched using the protective material layer (7) as an etching mask, and the first mask layer (3) is etched.
) is exposed to the outside (Fig. 1F).

Next, the protective material layer (7) and the first mask layer (3) are removed, and a window (4) is formed in the second mask layer (4) (FIG. 1G).

Through the window (4), that is, using the second mask layer (4) as a mask, the source region (5) and the drain region (6) of the semiconductor layer (2) are spaced apart from each other.
5) and a conductivity type different from (6), in this example p
type impurities are selectively formed by ion implantation or diffusion to form a gate region (8) and a gate junction J.
form. In this case, as explained in FIG. By appropriately selecting the spread of diffusion, etc., the gate region (8) and the source and drain regions (5) and (6)
, that is, the offset amount is selected to be a predetermined narrow interval Wo (FIG. 1H). Formation of this gate region (8) is as follows:
For example, it can be formed by diffusion treatment of impurities such as Zn at 600° C. for 5 minutes.

Next, the source region (5) is applied to the first mask layer (4).
An electrode window is formed on the drain region (6) and the drain region (6).
A source electrode (9) and a drain electrode Ql made of ohmic metal are formed on the mold regions (5) and (6), and a gate electrode (11) made of ohmic metal is formed on the gate region (8) for the p-type region. Then, the desired FET is obtained (Fig. 1 I).

According to this FET, the gate junction J and the substrate (
Although this is an FET in which a channel portion is formed by a semiconductor layer (2) between
It can also be used to obtain a so-called HEMT high-speed operation semiconductor device in which the channel portion is formed by a two-dimensional carrier gas layer, for example, a two-dimensional electron gas layer.

An example of obtaining a so-called reverse HEMT will be described with reference to FIG.

In the example in Figure 2, two-dimensional electron gas (2-DEC)
In this example, the same steps as those explained in FIG. 1 are performed, and each step is shown in FIG. 2 A corresponding to FIG. 1 A-I. The same reference numerals are given to the parts corresponding to those in FIG. 1 in FIG.
Similarly, on the substrate (1) consisting of s, a semi-insulating film, for example Aj! A first semiconductor layer (21) made of a GaAs compound semiconductor, a second semiconductor layer (22) made of an n-type GaAs compound semiconductor, and an energy band that is lower than that of the second semiconductor layer (22). A third semiconductor layer (23) made of, for example, a GaAs compound semiconductor, which is semi-insulating and has a large gap, and a layer having the same composition as the third semiconductor layer (23).
A fourth semiconductor layer (24) doped with type impurities is sequentially deposited by a series of MOCVD (Metal Organ
c Chemical Vapor Depositio
n) formed by a method. And this board S
A first mask layer (3) with a predetermined width W is selectively formed on the portion where the gate portion will ultimately be formed.
), and on top of this, a second mask layer (4) is formed on both sides of the first mask layer (3) with a predetermined width Ws (thick part (4a)).
2B), followed by the source and drain regions (5) as shown in FIG. 1C. 23).

Next, the protective material layer (7) is formed by etching to expose the thick part of the second mask layer (4) (Fig. 2E), and the protective material layer (7) is formed. The second mask layer (4) is selectively etched as a mask (FIG. 2F), and the first
The mask layer (3) is removed by etching to form a window (4-) (FIG. 2G). Next, the gate region (8) is connected to the fourth semiconductor layer (24) through this window (4).
Formed by selective diffusion of impurities in the mold (Fig. 2H)
. Then, the second mask layer (4) is etched to open an electrode window, the source and drain electrodes (9) and the α electrodes are alloyed, and the gate electrode (11) is formed in the gate region (8).
) is ohmically deposited (Fig. 2 1). According to such a configuration, the two-dimensional electron gas channel 2 is formed on the interface side of the third semiconductor layer (23) with the second semiconductor layer (22).
-1) A so-called reverse HEMT in which EG is formed is formed. In this case as well, the amount of offset between the source and drain regions (5) and (6) and the gate region (8) is determined by the width Ws of the thick portion (4a) of the second mask layer (4).
It can be set correspondingly.

When a reverse HEMT is formed by such a method, the dark voltage vth shifts as shown in FIG. 3 depending on the selection of the diffusion time of the p-type impurity when forming the gate region (8). By controlling the setting and addition of the diffusion time while measuring vth, desired characteristics can be obtained.

〔Effect of the invention〕

As described above, according to the present invention, by using the first and second mask layers in combination, the gate region and the source and drain regions disposed sandwiching the gate region are placed in a predetermined positional relationship, that is, a self-alignment line is formed. Therefore, these offset amounts can be set accurately and uniformly, and accordingly, a field effect transistor having highly reliable and uniform desired characteristics can be reliably obtained.

[Brief explanation of drawings]

FIG. 1 is a process diagram of one example of the method for manufacturing a semiconductor device according to the present invention, FIG. 2 is a process diagram of another example, and FIG. 3 is an explanatory diagram of its characteristics. S is a semiconductor substrate, (1) is a substrate, (2) is a semiconductor layer, (21) to (24) are first to fourth semiconductor layers,
(3) is the first mask layer, (4) is the second mask layer, (
4a) is the thick part, (5) and (6) are the source and drain regions, (7) is the protective material layer, (8) is the gate region, (9) and αω are the source and drain electrodes, (
11) is a gate electrode. Figure 3 Figure 1 l Manufacturing process diagram

Claims (1)

[Claims] (a) A first step that finally defines the gate length on the semiconductor substrate.
(b) forming a second mask from both opposing sides of the first mask to the portion where the source and drain will ultimately be formed; (c) the above step; forming source and drain regions by ion implantation using first and second masks; (d) then removing the first mask and selectively forming a gate region through the removed portions; (e) The second mask has a width in a portion contacting a side surface of the first mask, which defines an offset amount between the source and drain regions and the gate region, compared to the other portion. A method of manufacturing a semiconductor device having a thick portion.