JPS61198650A - Master slice semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To enable a large degree of freedom to be given to circuit construction, by a method wherein cells in the gate region of I/O circuits can be utilized as inner gate cells. CONSTITUTION:In I/O gate cell arrangement, the gate regions of I/O circuits A1-An+2 and C1-Cn+2 have cells each disposed in parallel in the same structural array as the inner gate cell array I1 or In outside it, and the gate regions of I/O circuits B1-Bn+2 and D1-Dn+2 have cells each disposed in succession at both ends of this parallel-disposed I/O circuit gate cell arrays or at both ends of the inner gate cell arrays. Those cells which can adopt such an arrangement are obtained by eliminating the necessary minimum numbers of cells satisfying the I/O circuit function: for example, cells constituting the Schmitt circuit, tri-state circuit, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a conductor integrated circuit in a master slice for logic circuit configuration.

(Prior art) Master slice semiconductor integrated circuit #-1''1 for the purpose of creating logic circuits Normally, the gate cell array and the wiring channel region are in the internal area of the substrate, and the input/output circuit is Each is placed in the surrounding area.

Here, in the logic gate cell array (hereinafter referred to as internal gate cell array), cells with the same structure and the same dimensions are regularly arranged to match the wiring grid of the assumed wiring channel axis area. , Internal pressure in the gate region of the input/output circuit Since the gate cell arranged is designed only for the purpose of controlling the input/output circuit section, its structural dimensions and wiring grid Fi are both internal gate φ cell arrangement and wiring channel region. different from that of

(Problem to be solved by the invention) However! Slice semiconductor integrated circuits in star
Due to their nature, they are used to construct logic circuits with different numbers of gates. Therefore, in some cases, there will be a surplus in the internal gate cells, and in other cases, there will be a shortage in some parts. There is an example of a master slice semiconductor integrated circuit in which 4104 internal gate cells are arranged at 132 bits per cell, but depending on the scale of the logic circuit to be constructed, the number of gates may still be insufficient1. This imposes undesirable restrictions on circuit configuration. In this case, the number of gates that a circuit designer considers to be insufficient per circuit ranges from just a few gates to at most several dozen gates.Of course, these shortages must be prepared in advance and included in the internal gate/cell arrangement. However, if a circuit configuration that causes an excess in the number of gates is used, the efficiency of cell utilization is further reduced. Furthermore, in another usage mode, for example, only 40 bins are used, but there may be a case where the required number of gates is partially insufficient. In this case, there will be excess space in the input/output circuit, and the gates and
The cells are not used at all, that is, despite the painstaking preparation of K, it is not possible to cope with the shortage of gates, and the circuit design has no degree of freedom and lacks flexibility.

(Object of the Invention) In view of the above circumstances, an object of the present invention is to provide a master slice semiconductor integrated circuit equipped with a gate cell arrangement that can flexibly accommodate various usage forms and provide a large degree of freedom in circuit configuration. It is to be.

(Structure of the Invention) A master m-slice semiconductor integrated circuit of the present invention includes a plurality of internal gate cell arrays arranged in parallel on a semiconductor substrate via wiring channel regions, and a gate region that controls an input/output circuit section. At least some of the gate cells in the internal gate cell array are set to have the same structural dimensions as the cells in the internal gate cell array, and the assumed wiring grid K of the wiring channel region [along with the periphery of the internal gate cell array region] and input/output circuits placed in each.

(Means for solving the problem) That is, according to the present invention, the number of gate cells arranged in the gate region of the input/output circuit is one, for example, the first stage of the input 2771 circuit and the last stage of the output buffer circuit. , gate/threshold voltage 7 IC1ll! Except for those that require high quality or sufficiently high electrostatic withstand voltage! -1 Most of them are set to have the same structural dimensions as the cells of the internal gate cell array, that is, the same channel length and channel width, and are aligned to match the pitch spacing of the expected wiring grid in the wiring channel region. Moreover, they are arranged around the internal gate cell arrangement area.

(Function) Therefore, the gate cells in each gate region of the plurality of input/output circuits arranged perpendicularly to the internal gate cell array are arranged in the same structure outside the internal gate cell array. The gate cells of each gate region of the plurality of input/output circuits arranged in parallel and parallel to each other are arranged consecutively at both ends of the internal gate cell array. In addition, if necessary, the wiring channel area is arranged in parallel with the pitch of the rltKIjJ constant grid grid. Such an array structure of gates and cells in the gate area of the input/output circuit may be arranged in parallel with the wiring channel area. The number of cells in the gate cell array appears to have increased, and by simply applying the respective wiring solution to correspond to various usage patterns, it can be used to compensate for the insufficient number of gates or to solve the original problem. It can also be used as an input/output circuit control gate cell.The present invention will be described in detail below with reference to the drawings.

(Embodiment) FIG. 1 is a layout diagram of an input/output circuit gate area showing an embodiment of the present invention. In this embodiment, a semiconductor substrate 1 and an internal region of this semiconductor substrate 1 (N internal gate cell arrays I arranged respectively) are described.

~1. and M wiring channel regions with assumed wiring grids, , Lllll, and (N+2) input/output circuits arranged in the surrounding @ area' 1-An+ 2 *B
1 '-Bn+2 + CI ''-Cn+2 +
and D I-D n + 2, and input/output gates set in the gate region to have the same channel length as the internal gate cells, and arranged to match the pitch interval of the assumed wiring grid in the wiring channel regions L1 to L1.・Cell array ai1~”nil + b1+++bn+2, Cl
~'n+4 and d12d0+2.

In the input/output gate-cell arrangement of this embodiment, the input/output circuit A
In the gate regions of I'' A n+ 2 and c1 to Cn+2, the internal cells are arranged in parallel in a row in the same structural arrangement on the outside of the internal cell array structure! or cell array structure.
Further, in the gate regions of the input/output circuits Bl-Bn44 and D1 to Dn+4, they are successively arranged at both ends of the parallelly arranged input/output circuit gate cell array or at both ends of the internal gate Φ cell array. Cells that can be arranged in this manner are cells that constitute, for example, Shemit circuits and tri-state circuits, excluding the minimum necessary cells that satisfy the input/output circuit function. Therefore, K, such as the cells forming the first stage of the input balancing circuit and the final stage of the output balancing circuit, is not applied. According to this example,
The number of cells in the internal gate cell array appears to have increased by more than the two arrays above, and may be used to compensate for the insufficient number of gates in response to various usage patterns, or to use a crystalline circuit or tri-state circuit. It can also be used for many purposes in circuit configuration.

FIG. 2 is an input/output circuit gate showing another embodiment of the present invention.
This embodiment shows an arrangement structure in the case where an integer number of cells cannot be arranged conveniently due to the internal pressure of the gate region of one input/output circuit.

In this case, input/output circuits that are in contact with each other, such as λl
One cell is formed over each gate region of A2 and A2. That is, one input/output circuit is formed upside down and two gate regions are used to form one cell, as shown by the dotted line. Here 1F'' and lol
is one input/output circuit person = is the other A! This symbol indicates that it is in the form of a long return.

FIG. 3 is a partial layout diagram of input/output circuit cells showing another embodiment of the present invention. In the embodiment, the cells in the gate region are arranged in two arrays. One is the wiring channel region, which is arranged to match the pitch interval of the assumed lattice arrangement of ~L and 11, respectively. In the case of this embodiment, one of which is shown as array b1' in FIG. Can be used for configuration.

(Effects of the Invention) As described in detail above, according to the present invention, the gate area of the input/output circuit can be easily removed without any change in the basic design philosophy or manufacturing technology of the master or slice semiconductor integrated circuit. The cell can also be used as an internal gate cell, giving greater flexibility in circuit design and making it ideal for master-slice semiconductor integrated circuits, which require flexibility in adapting to various usage patterns. This can bring about extremely significant effects in terms of design technology.

[Brief explanation of drawings]

FIG. 1 is a layout diagram of an input/output circuit gate area showing one embodiment of the present invention, FIG. 2 is a partial layout diagram of an input/output gate cell showing another embodiment of the invention, and FIG. FIG. 7 is a partial layout diagram of an input/output circuit gate cell showing another embodiment of the present invention. l...Semiconductor substrate, I1%I,...
・Internal gate cell arrangement, Ll-LI! l...
Wiring channel region, Al~person n+t+ B1-Bts
+2m C1~Cn+z, 1)1~Da44 ""
"Input/output circuit, a 1 ~ afl-H, b l ~ bn+
2゜' l -'n+2 y dl ~dn+2 *
b1'"""I/O boot cell array in the gate area of the I/O circuit.

Claims (3)

[Claims] (1) A plurality of internal gate cell arrays arranged in parallel on a semiconductor substrate, and at least some of the gate cells in the gate region that controls the input/output circuit section as cells of the internal gate cell array. A master slice semiconductor integrated circuit comprising: an input/output circuit arranged around the internal gate/cell arrangement region, set to the same structural dimensions and aligned with an assumed wiring grid of the wiring channel region. (2) The input/output circuit gate cell in the gate region is
The master slice semiconductor integrated circuit according to claim 1, wherein the master slice semiconductor integrated circuit is arranged around the internal gate cell array in two array structures in parallel or in series. (3) A portion of the input/output circuit gate cells in the gate region are arranged between the two parallelly arranged internal gate cell arrays and are arranged to match the pitch width of the assumed wiring grid in the wiring channel region. The master slice semiconductor integrated circuit according to claim 1, wherein the master slice semiconductor integrated circuit is arranged in a manner that the master slice semiconductor integrated circuit is arranged in a manner that the master slice semiconductor integrated circuit is arranged as follows.