JPS6193613A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6193613A JPS6193613A JP59215603A JP21560384A JPS6193613A JP S6193613 A JPS6193613 A JP S6193613A JP 59215603 A JP59215603 A JP 59215603A JP 21560384 A JP21560384 A JP 21560384A JP S6193613 A JPS6193613 A JP S6193613A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- shape
- hexagonal
- chips
- quadrilateral
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000013078 crystal Substances 0.000 abstract description 7
- 230000007547 defect Effects 0.000 abstract description 7
- 230000015556 catabolic process Effects 0.000 abstract 1
- 230000006378 damage Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10156—Shape being other than a cuboid at the periphery
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
本発明は、半導体集積回路装置のチップ形状に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a chip shape of a semiconductor integrated circuit device.
（従来技術）
従来、半導体集積回路装置の素子形状は、四角形（長方
形）であった。しかし、従来技術では、以下のような欠
点がありた。(Prior Art) Conventionally, the element shape of a semiconductor integrated circuit device has been a square (rectangle). However, the conventional technology has the following drawbacks.
第１に、長方形のチップ状では、現在使用されている円
形ウェハーに対し有効チップ数の上から見【、前記ウェ
ハーに無駄な領域ができ、第２Ｋ、長方形の素子では第
１図に示す斜線部においてパッケージ組立部（％にモー
ルドパッケージ組立時）は熱による、あるいは応力歪み
等による半導体基板の結晶欠陥や該半導体基板上に形成
した素子の破壊が発生するという欠点がある。First, in the case of a rectangular chip, there is a wasted area on the wafer when viewed from the top of the effective number of chips compared to the currently used circular wafer; However, the package assembly section (particularly when assembling a molded package) has the disadvantage that crystal defects in the semiconductor substrate and destruction of elements formed on the semiconductor substrate occur due to heat or stress strain.
又、
第３に、組立時に、ボンディングワイヤの長短が生じ（
特に長辺と短辺の差が大きい場合）エツジタッチ等によ
る組立歩留低下になる。Thirdly, during assembly, the length of the bonding wire may vary (
Especially if the difference between the long side and the short side is large), the assembly yield will decrease due to edge touching, etc.
（発明の目的）
本発明の目的は、ウェハー上の有効チップ数を増大させ
、組立時の結晶欠陥を少なくし、組立歩留を上げるよう
なチップを提供することにある。(Object of the Invention) An object of the present invention is to provide a chip that increases the number of effective chips on a wafer, reduces crystal defects during assembly, and increases assembly yield.
（発明の構成）
本発明の構成は、半導体集積回路装置のチップ形状が六
角形であることを特徴とするものである。(Configuration of the Invention) The configuration of the present invention is characterized in that the chip shape of the semiconductor integrated circuit device is hexagonal.
（発明の効果） 本発明の効果には、以下のようなものがある。(Effect of the invention) The effects of the present invention include the following.
チップ形状が六角形であることは、円形母材ウェハー（
結晶成長の点から母材ウェハーは、円形のものが使用さ
れる）に対して、数字的に四角形なチップ形状に較べて
数多くのチップを得られる。The hexagonal chip shape means that the circular base material wafer (
From the viewpoint of crystal growth, a circular base material wafer is used), but numerically a larger number of chips can be obtained than a square chip shape.
すなわち、母材ウェハーに無駄な領域が少なくなる。こ
のことを数学的に最も簡単に説明すると、第１図（ｂ）
に示すように、一つのチップを考えた場合に、四角形、
六角形、それぞれに外接する円の大きさには目明の差が
ある。実際には、大きな円形ウェハーに四角形、六角形
のチップがリピートされて作られるが、六角形のチップ
に較べて四角形のチップの方が無駄な領域が多くなる。In other words, there is less wasted area on the base wafer. The simplest way to explain this mathematically is as shown in Figure 1(b).
As shown in , when one chip is considered, a rectangle,
There are differences in the size of the circles circumscribing each hexagon. In reality, square and hexagonal chips are repeated on a large circular wafer, but square chips have more wasted area than hexagonal chips.
次に、チップ形状が六角形であることから、四角形のチ
ップに較べて組立時における熱歪み、機械的歪み等によ
る結晶欠陥や形成素子の破壊が少ない。これは、チップ
端部において、チップにかかる歪みの力学的密度は、四
角形（９０°）より六角形（１２０’）の方が小さいた
めである。また、ポンディングパッドの配置の自由度が
高く、ボンディングワイヤの長さを短かくすることが容
易であり、エツジタッチ等が少なくなり組立歩留を上げ
ることが出来る。Next, since the chip shape is hexagonal, there are fewer crystal defects and destruction of forming elements due to thermal strain, mechanical strain, etc. during assembly than with square chips. This is because the mechanical density of strain applied to the chip at the end of the chip is smaller in a hexagonal shape (120') than in a square shape (90°). Furthermore, the degree of freedom in arranging the bonding pads is high, the length of the bonding wire can be easily shortened, edge touching, etc. can be reduced, and the assembly yield can be increased.
（発明の実施例）
第３図に本発明の実施例としてチップ形状の一例を示す
。(Embodiment of the Invention) FIG. 3 shows an example of a chip shape as an embodiment of the present invention.
第３図にて半導体記憶装置に本発明を用いた場合につい
て説明する半導体記憶装置（読み出し、書き込み可能記
憶装置以下ＲＡＭと略す）などのようにチップ内にメモ
リセルなアレイ状に配置した場合には、従来の四角形メ
チツブ形状の場合、チップ内での各素子レイアウトの観
点からポンディングパッド配置可能領域は第２図の２１
で示す領域となる。尚、第２図の２２、第３図の３２は
メモリセルアレイ領域である。しかし、本発明によれば
、実施例として第３図の３１に示した領域がポンディン
グパッド配置可能領域となる。この３１の領域の中から
適当な所にポンディングパッドを置けば良く、自由度が
高い。本実施例では、約４割領域が広（なっている。ま
た、ペースリボンの設計にも有利である。もちろん第２
図、第３図のチップの面積は同じである。このようにＲ
ＡＭなどには本発明が％に効果があるが、他にアレイ部
を含むものとして読み出し専用記憶装置、ゲートアレイ
などにも＃に効果がある。もちろん一般の半導体装置に
おいても充分効果がある。When the present invention is arranged in a memory cell array within a chip, such as in a semiconductor memory device (readable/writable memory device hereinafter abbreviated as RAM), the present invention will be explained with reference to FIG. 3. In the case of the conventional square mesh shape, the area where the bonding pad can be placed is 21 in Fig. 2 from the viewpoint of the layout of each element within the chip.
This is the area shown by . Note that 22 in FIG. 2 and 32 in FIG. 3 are memory cell array areas. However, according to the present invention, as an example, the area shown at 31 in FIG. 3 is the area where the bonding pad can be placed. It is sufficient to place the bonding pad at an appropriate location among these 31 areas, giving a high degree of freedom. In this example, about 40% of the area is wide. It is also advantageous for designing the pace ribbon. Of course, the second
The areas of the chips in FIG. 3 and FIG. 3 are the same. Like this R
The present invention is most effective in AM and the like, but it is also very effective in read-only storage devices, gate arrays, etc. that include an array section. Of course, it is also sufficiently effective for general semiconductor devices.
尚、本発明において、チップ形状が六角形であることか
らスクライプが少し複雑になる。しかし、従来のスクラ
イプ装置でも可能だが、スクライプ装置とし【、レーザ
ー等を用いれば何ら問題とはならない。また、スクライ
プ装置とマイクロ；ンピ為−ター等を連動させれば、完
全自動化も可能であり本発明がスクライプ工程で従来と
較べて問題となる点は何もない。Incidentally, in the present invention, since the chip shape is hexagonal, scribing becomes a little complicated. However, although it is possible to do this with a conventional scribing device, there is no problem if a laser or the like is used as a scribing device. In addition, if the scribing device is linked with a microcomputer or the like, complete automation is possible, and the present invention poses no problems in the scribing process compared to conventional methods.
（発明のまとめ）
以上説明したごとく、本発明によれば、同一ウニバーで
の有効チップ数を多く取れ、組立時におけるチップ端の
熱歪み、機械的歪み等による結晶欠陥を無くすことが出
きる。さらに、チップ内でのポンディングパッド配置可
能領域が多く、ボンディングリード線の長さの均一化が
出来エツジタッチ等の不良を無くすことが出きる。(Summary of the Invention) As explained above, according to the present invention, it is possible to increase the number of effective chips in the same unit and eliminate crystal defects caused by thermal distortion, mechanical distortion, etc. at the chip end during assembly. Furthermore, there is a large area in which bonding pads can be placed within the chip, and the length of bonding lead wires can be made uniform, thereby eliminating defects such as edge touching.
第１図（ａ）は、従来技術を示す図であり、同図で１１
・・・・・・組立時結晶欠陥が生じゃすい領域である。
第１図（ｂ）は、同じ面積の四角形と六角形に外接する
円を示す図であり、同図において、１２・・回正六角形
、１３・・・・・・正方形、１４・・曲長方形、である
。
第２図は、従来の四角形のチップ形状をした半導体記憶
装置を示す平面図であり、同図で、２１・曲・ポンディ
ングパッド配置可能領域、２２・・・・・・メモリセル
アレイ領域、である。
第３図は、本発明の実施例の半導体記憶装置を示す平面
図で、３１・曲・ポンディングパッド配置可能領域、３
２・・曲メモリセルアレイ領域、である。FIG. 1(a) is a diagram showing the prior art, and in the same figure, 11
...This is an area where crystal defects are likely to occur during assembly. Fig. 1(b) is a diagram showing circles circumscribing a quadrilateral and a hexagon with the same area. , is. FIG. 2 is a plan view showing a conventional semiconductor memory device having a rectangular chip shape. be. FIG. 3 is a plan view showing a semiconductor memory device according to an embodiment of the present invention.
2... music memory cell array area.
Claims (1)
特徴とする半導体集積回路装置。A semiconductor integrated circuit device characterized in that the chip shape of the semiconductor integrated circuit device is hexagonal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215603A JPS6193613A (en) | 1984-10-15 | 1984-10-15 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59215603A JPS6193613A (en) | 1984-10-15 | 1984-10-15 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6193613A true JPS6193613A (en) | 1986-05-12 |
Family
ID=16675162
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59215603A Pending JPS6193613A (en) | 1984-10-15 | 1984-10-15 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6193613A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2008001824A1 (en) * | 2006-06-29 | 2008-01-03 | Panasonic Corporation | Chip for capacitor microphone, capacitor microphone, and method for manufacturing the same |
| US7485955B2 (en) | 2004-03-22 | 2009-02-03 | Samsung Electronics Co., Ltd. | Semiconductor package having step type die and method for manufacturing the same |
| US8159247B2 (en) | 2009-10-06 | 2012-04-17 | International Business Machines Corporation | Yield enhancement for stacked chips through rotationally-connecting-interposer |
-
1984
- 1984-10-15 JP JP59215603A patent/JPS6193613A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7485955B2 (en) | 2004-03-22 | 2009-02-03 | Samsung Electronics Co., Ltd. | Semiconductor package having step type die and method for manufacturing the same |
| DE102005016439B4 (en) * | 2004-04-01 | 2011-07-28 | Samsung Electronics Co., Ltd., Kyonggi | Semiconductor device package and manufacturing process |
| WO2008001824A1 (en) * | 2006-06-29 | 2008-01-03 | Panasonic Corporation | Chip for capacitor microphone, capacitor microphone, and method for manufacturing the same |
| US8159247B2 (en) | 2009-10-06 | 2012-04-17 | International Business Machines Corporation | Yield enhancement for stacked chips through rotationally-connecting-interposer |
| US9151781B2 (en) | 2009-10-06 | 2015-10-06 | International Business Machines Corporation | Yield enhancement for stacked chips through rotationally-connecting-interposer |
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