JPS62169458A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS62169458A JPS62169458A JP61012448A JP1244886A JPS62169458A JP S62169458 A JPS62169458 A JP S62169458A JP 61012448 A JP61012448 A JP 61012448A JP 1244886 A JP1244886 A JP 1244886A JP S62169458 A JPS62169458 A JP S62169458A
- Authority
- JP
- Japan
- Prior art keywords
- metal wiring
- wiring layer
- layer
- contact
- line width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 229910052751 metal Inorganic materials 0.000 claims abstract description 42
- 239000002184 metal Substances 0.000 claims abstract description 42
- 239000011521 glass Substances 0.000 claims abstract description 19
- 238000007733 ion plating Methods 0.000 claims abstract description 6
- 238000004544 sputter deposition Methods 0.000 claims abstract description 5
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 3
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 3
- 239000000919 ceramic Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 9
- 239000005394 sealing glass Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 6
- 230000035939 shock Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 42
- 239000000463 material Substances 0.000 description 9
- 238000012360 testing method Methods 0.000 description 7
- 239000002241 glass-ceramic Substances 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 3
- 230000005856 abnormality Effects 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000011156 evaluation Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000006023 eutectic alloy Substances 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 238000000752 ionisation method Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
- H01L23/4822—Beam leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特にセラミック基材上に金属配線
層を有するガラス封止型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a glass-sealed semiconductor device having a metal wiring layer on a ceramic substrate.
現在使用されている集積回路（以下Ｉ’ Ｏと略称する
）のパッケージ法は樹脂封止型、ガラス−セラミック封
止型及び積層セラミック型の３種類に分類される。これ
らのパッケージ法は信頼性及び価格の点で長短があり、
信頼性に関しては積層セラミック型、ガラス−セラミッ
ク型、樹脂封止型の順に優れ、一方価格の点ではこの逆
の順序となる。最近では、各パッケージ法の短所を克服
すべく研究が進められているが、信頼性と価格において
中間的なガラス−セラミック封止型の改良が強く望まれ
ている。Currently used packaging methods for integrated circuits (hereinafter abbreviated as I'O) are classified into three types: resin sealing type, glass-ceramic sealing type, and laminated ceramic type. These packaging methods have advantages and disadvantages in terms of reliability and cost.
In terms of reliability, the laminated ceramic type, glass-ceramic type, and resin-sealed type are superior in this order, while in terms of price they are in the opposite order. Recently, research has been carried out to overcome the shortcomings of each packaging method, but there is a strong desire to improve the glass-ceramic sealing type, which is intermediate in terms of reliability and cost.
第２図にガラス−セラミック封止型半導体装置としてビ
ングリッドアレイ （ＰＧＡ）の−例を示す。ｋｌ Ｏ
等のセラミック基材１の凹部に工Ｃ等の半導体素子２が
Ａｕ−８ｉ共晶合金やＡｕペースト等の接着層３により
塔載されている。また、セラミック基材１には多数の導
電層としてｋｌやＡ４合金等からなる金属配線層４が形
成され、半導体素子２の各電極と各金属配線層４とがＡ
ｕまたはＡｔのボンディングワイヤで各々結線されてい
る。そして、半導体素子２を気密封止すべく、セラミッ
ク基材１の周縁部に低融点ガラスペーストを塗布し、そ
の上にセラミックまたは金属からなるキャツブ部材６を
載せて加熱して生じたガラス営荀セラミック基材１とキ
ャップ部材６とを封止する。FIG. 2 shows an example of a bin grid array (PGA) as a glass-ceramic sealed semiconductor device. kl O
A semiconductor element 2, such as a ceramic substrate 1, is mounted on a recessed portion of a ceramic substrate 1, etc., with an adhesive layer 3, such as an Au-8i eutectic alloy or an Au paste. Further, metal wiring layers 4 made of KL, A4 alloy, etc. are formed as a large number of conductive layers on the ceramic base material 1, and each electrode of the semiconductor element 2 and each metal wiring layer 4 are connected to A4.
They are connected with U or At bonding wires. Then, in order to hermetically seal the semiconductor element 2, a low melting point glass paste is applied to the peripheral edge of the ceramic substrate 1, and a cap member 6 made of ceramic or metal is placed on top of the paste and heated. The ceramic base material 1 and the cap member 6 are sealed.
電気信号の入出力は半導体素子２、金属配線Ｎ４及び外
部接続用ピン８を通って行なわれる。Input/output of electrical signals is performed through the semiconductor element 2, metal wiring N4, and external connection pins 8.
工Ｃを中心とする半導体装置の小型化、高集積化及び低
コスト化の傾向に伴ない、パッケージにおいてはセラミ
ック基材１上の金属配線層４の微細化が要望され、従来
のスクリーン印刷に代ってマスク蒸着等により微細な配
線を形成する方向にある。しかし、金属配線層４が微細
になる程その電気抵抗のフントロールは困難になり、温
度サイクルテストや熱衝撃テスト等の半導体装置の信頼
性評価試験において金属配線層の配線抵抗値が設計値か
ら変化する等、安定した特性が得られない現状であった
。With the trend toward miniaturization, higher integration, and lower cost of semiconductor devices, especially semiconductor devices, there is a demand for miniaturization of the metal wiring layer 4 on the ceramic base material 1 in packages, and conventional screen printing Instead, the trend is to form fine wiring by mask vapor deposition or the like. However, as the metal wiring layer 4 becomes finer, it becomes more difficult to control its electrical resistance, and in reliability evaluation tests of semiconductor devices such as temperature cycle tests and thermal shock tests, the wiring resistance value of the metal wiring layer 4 is lower than the design value. The current situation was that stable characteristics could not be obtained due to changes such as changes.
本発明者等は配線抵抗の変化についで詳細に調査、検討
した結果、第２図に示す金属配線層４のガラス層７との
接触部分と非接触部分との接触境界部９において、温度
サイクル（例えば、−６５１：’〜＋１５Ｏｒ）数の増
加に伴なって接触境界部９の抵抗値が第３図に示す如く
増加することを見出した。As a result of detailed investigation and study regarding changes in wiring resistance, the inventors of the present invention found that the temperature cycle was (For example, -651:' to +15 Or) It has been found that as the number increases, the resistance value of the contact boundary portion 9 increases as shown in FIG.
この原因は明確ではないが、温度サイクルを与えた場合
、セラミック基材１、金属配線層４及びガラス層７の熱
膨張率が異なるために接触境界部９に熱応力が集中する
こと、及びその結果Ａ４等の金属配線層４の接触境界部
９の近傍りにボイドの集中及び微細なりラックの発生が
起るため、この接触境界部９付近で金属配線層４の電気
抵抗が上昇するものと考えられる。The reason for this is not clear, but when a temperature cycle is applied, thermal stress concentrates on the contact boundary 9 due to the different coefficients of thermal expansion of the ceramic base material 1, metal wiring layer 4, and glass layer 7. As a result, the concentration of voids and the generation of fine racks occur near the contact boundary part 9 of the metal wiring layer 4 such as A4, so the electrical resistance of the metal wiring layer 4 increases near the contact boundary part 9. Conceivable.
本発明は、か＼る抵抗変化の現象の解析に基いて、信頼
性評価試験における金属配線層の抵抗変化をなくし、信
頼性の高い半導体装置を提供することを目的とする。An object of the present invention is to provide a highly reliable semiconductor device by eliminating resistance changes in a metal wiring layer in a reliability evaluation test based on an analysis of the phenomenon of resistance changes.
本発明は、上記の目的を達するために、半導体素子を塔
載したセラミック基材上に形成した金属配線層と、金属
配線層の一部に接触してセラミック基材とキャップ部材
とを固着する封止用ガラス層とを備えた半導体装置であ
って、金属配線層のガラス層との接触境界部を含む近傍
で金属配線層の線幅がガラス層との非接触部での線幅よ
り５％以上大きいことを特徴とする上記半導体装置を提
供するものである。In order to achieve the above object, the present invention includes a metal wiring layer formed on a ceramic base material on which a semiconductor element is mounted, and a cap member that is fixed to the ceramic base material by contacting a part of the metal wiring layer. A semiconductor device comprising a sealing glass layer, wherein the line width of the metal wiring layer near the contact boundary with the glass layer is 55% larger than the line width at the non-contact part with the glass layer. % or more.
本発明の特徴点を第１図を参照して説明すると、金属配
線層４とガラス層７との接触境界部９を含む近傍りにお
ける金属配線層４の線幅ｌ をガラス７との非接触部分
１）での線幅ｌ よりも５％以上大さく形成するのであ
る。The characteristic points of the present invention will be explained with reference to FIG. It is formed to be 5% or more larger than the line width l in portion 1).
金属配線層４を増加された線幅！ に形成すべき接触境
界部９の近傍りとは、この接触境界部９を含み、その両
側に適当な距離だけ離れた範囲以内を云う。ガラス層７
は金属配線層４との接触境界部９からキャップ部材６と
の接触点まで漸増する断面形状を有するが、上記近傍り
は少なくともこの接触境界部９からキャップ部材６との
接触点までの水平距離だけ接触境界部９の両側から離れ
た範囲を含むことが好ましい。又、金属配線層４の近傍
りに加えてガラス層７との接触部分１０全体を線幅ｔ
に形成しても良い。Increased line width of metal wiring layer 4! The vicinity of the contact boundary portion 9 to be formed is defined as an area including the contact boundary portion 9 and separated by an appropriate distance on both sides thereof. glass layer 7
has a cross-sectional shape that gradually increases from the contact boundary part 9 with the metal wiring layer 4 to the contact point with the cap member 6, and in the vicinity of the above, at least the horizontal distance from the contact boundary part 9 to the contact point with the cap member 6 It is preferable to include a range away from both sides of the contact boundary portion 9 by a distance of 100 mm. In addition to the vicinity of the metal wiring layer 4, the entire contact portion 10 with the glass layer 7 has a line width t.
It may be formed into
金属配線層としては、アルミニウムまたはアルミニウム
合金をイオンプレーティング法またはスパッタリング法
により所定の形状に形成することが好ましい。Ａｌまた
はその合金を使用すれば、半導体素子の電極、ボンディ
ングワイヤ及び金属配線層を同一材料にでき、ワイヤー
ボンディング及びガラス封止の安定性を増し、高品位で
低コストの半導体装置を得ることができる。又、一般的
にセラミック基材上に形成された金属配線は高い密着性
を確保することが困難であるが、本発明者等はプラズマ
ＣｖＤ法、イオンプレーティング法又はスパッタリング
法等の方法によりイオン化した粒子を析出させて成膜す
れば、高い密着性が得られることを見い出したものであ
り、この中でマスキングによる部分成膜が可能で製造コ
ストが安いイオンプレーティング又はスパッタリングを
用いること・が好ましい。As the metal wiring layer, it is preferable to form aluminum or an aluminum alloy into a predetermined shape by an ion plating method or a sputtering method. If Al or its alloy is used, the electrodes, bonding wires, and metal wiring layers of semiconductor elements can be made of the same material, increasing the stability of wire bonding and glass sealing, and making it possible to obtain high-quality, low-cost semiconductor devices. can. In addition, it is generally difficult to ensure high adhesion for metal wiring formed on a ceramic substrate, but the inventors have developed ionization methods such as plasma CVD, ion plating, or sputtering. It was discovered that high adhesion can be obtained by depositing the particles, and among these methods, it is possible to use ion plating or sputtering, which allows partial film formation by masking and has low manufacturing costs. preferable.
金属配線層のガラス層との接触境界部を含む近傍で金属
配線層の線幅をガラス層との非接触部での線幅より５％
以上大きくすることにより、第３図に示したような熱サ
イクルもしくは熱衝撃による金属配線層の接触境界部で
の電気抵抗の上昇が一押えられる。線幅の増加が５％未
満では上記の抵抗の上昇が表われ、金属配線層の抵抗フ
ントロールが困難である。The line width of the metal wiring layer near the contact boundary with the glass layer is set to 5% of the line width at the non-contact area with the glass layer.
By making it larger than this, the increase in electrical resistance at the contact boundary of the metal wiring layer due to thermal cycles or thermal shock as shown in FIG. 3 can be suppressed. If the increase in line width is less than 5%, the above-mentioned resistance increases and it is difficult to control the resistance of the metal wiring layer.
金属配線層の接触境界部での電気抵抗を下げるためには
その部分で膜厚を増加させることによっても可能である
が、その場合には金属配線層の形成コストが高くなるほ
か、微細配線にとり著しく不利となり実用的ではない。It is possible to reduce the electrical resistance at the contact boundary of the metal wiring layer by increasing the film thickness at that part, but in that case, the cost of forming the metal wiring layer increases and it is difficult to make fine wiring. This is extremely disadvantageous and impractical.
一辺が３５ｍｍの正方形のアルミナ基材に、真空度Ｉ
Ｘ １Ｏ−４ｔｏｒｒ、基板温度２００Ｃ，蒸着速度５
０Ａ／ｓｅａの条件でマスクを用いた真空蒸着により、
Ａ４配線層を形成し、第２図に示す従来のＰＧＡ構造の
半導体装置を５０個製造した。Vacuum degree I
X 1O-4torr, substrate temperature 200C, deposition rate 5
By vacuum evaporation using a mask under the condition of 0A/sea,
An A4 wiring layer was formed, and 50 semiconductor devices having the conventional PGA structure shown in FIG. 2 were manufactured.
また、同じアルミナ基材に、Ａｒガス導入後の真空度４
Ｘ １０”−’ ｔｏｒｒ 、基板温度２００ Ｃ，
）＜イアスミ圧Ｉ ＫＶ、高周波出力１５０Ｗ、蒸着速
度５０シ１ｌｌｅｃの条件でマスクを用いたイオンプレ
ーティング法により、第１図の如くガラス層との接触境
界部近傍で線幅を非接触部分の線幅より５％だけ大きく
したＡｌ配線層を形成し、上記と同様にＰＧＡ構造を有
する本発明の半導体装置を５０個製造した。In addition, the same alumina base material had a vacuum degree of 4 after introducing Ar gas.
X 10''-' torr, substrate temperature 200 C,
) <Ion plating method using a mask under the conditions of Iasumi pressure I KV, high frequency output 150 W, and evaporation rate 50 cm, the line width was changed in the non-contact area near the contact boundary with the glass layer as shown in Figure 1. An Al wiring layer 5% larger than the line width was formed, and 50 semiconductor devices of the present invention having a PGA structure were manufactured in the same manner as above.
前記ＰＧＡ組立実装工程において、Ａ４配線層の剥離に
よるワイヤーボンディング不良が、従来の装置では１３
個あったが、本発明の装置では全くなかった。In the PGA assembly and mounting process, wire bonding defects due to peeling of the A4 wiring layer occurred in 13 times with conventional equipment.
However, there were none with the device of the present invention.
次に、−６０Ｃ〜＋１５０Ｃの温度サイクルテストを１
００サイクル実施し、その後各装置の作動テストを行な
った結果、従来の装置では２３個の異常が認められたが
、本発明の装置では全く異常が発生しなかった。Next, a temperature cycle test of -60C to +150C was carried out.
As a result of carrying out 00 cycles and then testing the operation of each device, 23 abnormalities were observed in the conventional device, but no abnormalities occurred in the device of the present invention.
この実施例ではＰＧＡ構造の半導体装置を例示したが、
その他のガラス封圧型の半導体装置にも適用できる。In this embodiment, a semiconductor device with a PGA structure was illustrated, but
It can also be applied to other glass sealed pressure type semiconductor devices.
本発明によれば、金属配線層のガラス層との接触境界部
を含む近傍で金属配線層の線幅をガラス層との非接触部
分での線幅より５％以上大きくすることにより、熱サイ
クルもしくは熱衝撃による金属配線層の接触境界部での
電気抵抗の上昇を抑えることができるので、金属配線層
の抵抗変化をなくし、信頼性の高い半導体装置を提供で
きる。According to the present invention, thermal cycle Alternatively, since it is possible to suppress the increase in electrical resistance at the contact boundary of the metal wiring layer due to thermal shock, it is possible to eliminate resistance changes in the metal wiring layer and provide a highly reliable semiconductor device.
第１（ａ）図は本発明における金属配線層及びガラス層
の構造を示す断面図であり、第１（ｂ）図はその平面図
である。第２図は従来のガラス封止型半導体装置の部分
断面図であり、第３図は従来の半導体装置における温度
サイクルテストでのサイクル数と抵抗変化比の関係を示
すグラフである。
１・・セラミック基材 ２・・半導体素子４・・金ｆｆ
ｉ配線層 ５・・ボンデ′イングワイヤ６・・キャップ
部材 ７・・ガラス層
９・・接触境界部 １０・・接触部分
１）・・非接触部分
Ｌ ’／力゛う７肩
第２図
第３図
サイクル数FIG. 1(a) is a sectional view showing the structure of a metal wiring layer and a glass layer in the present invention, and FIG. 1(b) is a plan view thereof. FIG. 2 is a partial sectional view of a conventional glass-sealed semiconductor device, and FIG. 3 is a graph showing the relationship between the number of cycles and the resistance change ratio in a temperature cycle test of the conventional semiconductor device. 1. Ceramic base material 2. Semiconductor element 4. Gold ff
i Wiring layer 5...Bonding wire 6...Cap member 7...Glass layer 9...Contact boundary part 10...Contact part 1)...Non-contact part L'/force 7 shoulder Fig. 2 3 figure cycle number
Claims (2)
た金属配線層と、金属配線層の一部に接触してセラミッ
ク基材とキャップ部材とを固着する封止用ガラス層とを
備えた半導体装置において、金属配線層のガラス層との
接触境界部を含む近傍で金属配線層の線幅がガラス層と
の非接触部での線幅より５％以上大きいことを特徴とす
る、上記半導体装置。(1) A metal wiring layer formed on a ceramic substrate on which a semiconductor element is mounted, and a sealing glass layer that contacts a part of the metal wiring layer and fixes the ceramic substrate and the cap member. In the semiconductor device, the line width of the metal wiring layer near the contact boundary with the glass layer is 5% or more larger than the line width at the non-contact part with the glass layer. Device.
スパッタリング法により形成されたアルミニウムまたは
アルミニウム合金からなる、特許請求の範囲（１）項記
載の半導体装置。(2) The semiconductor device according to claim (1), wherein the metal wiring layer is made of aluminum or an aluminum alloy formed by an ion plating method or a sputtering method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012448A JPS62169458A (en) | 1986-01-22 | 1986-01-22 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61012448A JPS62169458A (en) | 1986-01-22 | 1986-01-22 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62169458A true JPS62169458A (en) | 1987-07-25 |
Family
ID=11805616
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61012448A Pending JPS62169458A (en) | 1986-01-22 | 1986-01-22 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62169458A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511272B2 (en) | 2004-05-14 | 2009-03-31 | Hitachi High-Technologies Corporation | Method for controlling charged particle beam, and charged particle beam apparatus |
| WO2013057867A1 (en) * | 2011-10-21 | 2013-04-25 | パナソニック株式会社 | Semiconductor device |
-
1986
- 1986-01-22 JP JP61012448A patent/JPS62169458A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7511272B2 (en) | 2004-05-14 | 2009-03-31 | Hitachi High-Technologies Corporation | Method for controlling charged particle beam, and charged particle beam apparatus |
| WO2013057867A1 (en) * | 2011-10-21 | 2013-04-25 | パナソニック株式会社 | Semiconductor device |
| US9117770B2 (en) | 2011-10-21 | 2015-08-25 | Panasonic Corporation | Semiconductor device |
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