JPS62194562A - cache memory system - Google Patents

Abstract

PURPOSE:To increase the response speed to respond quickly by giving a module constitution to a cache memory and detecting hit/unhit conditions of respective modules in parallel independently of the constitution of the cache memory. CONSTITUTION:Cache memory parts 210, 211, and 212 are formed as modules, and outputs h1-h4 of respective modules are selected in accordance with information designated in a register 215 by the first selecting means 213 to change the number of ways. That is, designating data of the number of modules to be operated simultaneously in parallel is set from a CPU 1 to the register 215, and a signal M is outputted from the register 215 to the means 213 and a replace means 214. If modules 210-212 are designated, hit signals of all modules are outputted, and the second selecting means 2144 outputs 6-bit outputs of replace information storage modules 242 and 243 in parallel by the signal M. Since memory parts are formed as modules and hit signals outputted from them are selectively outputted in this manner, the response speed is increased.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art Problems to be Solved by the Invention Means for Solving the Problems Working Examples CA) Replacement Information (1) 4-way configuration , (II) 2-way configuration CB)
Embodiment configuration (C) Operation description a; 4-way operation b; 2-way operation 2-way replacement logic gate; 2-way new LRU value creation gate; Selection gate 12; Selection gate 13; CD) Modifications/Applications Example Effects [Summary] The present invention provides a cache memory system in which the system configuration, that is, the number of entries and the number of ways, can be changed.
By checking the unhit status in parallel, the response speed is increased regardless of the system configuration.

[Industrial application field]

The present invention relates to a cache memory system that stores a frequently used data group in a high-speed memory and outputs data from the high-speed memory when the low-speed data memory is accessed and there is stored data in the high-speed memory. In particular, a cache memory system that can change the configuration of the cache memory system, that is, the number of storage areas (referred to as ways) that can store data in parallel at the same address, and the number of addresses that can be stored in one way (referred to as the number of entries). It is related to.

[Prior art]

FIG. 8 is a block diagram of a conventional cache memory system.

In the figure, 1 is a main processing unit that outputs address data, 2 is a cache memory section, and 3 is a data memory section, which has a storage address of address "0000"-'FFFF" (in hexadecimal notation). 4 is an address decoder.

When the main processing unit 1 accesses a specific address in the data memory 3, the specific address “xx” is stored in the address register 20.
xx”. Some addresses of the address register 20, for example, the lower 8 bits, are stored in each cache memory 21.
~2n address decoders 21d-2nd.

The upper 8 bits of the address are fully stored in the tag memories 21a to 2na, and as described above, the corresponding upper 8 bit data is read out to the comparators 21c to 2nc from the storage address pointed to by the lower 8 bit address. 0 comparator 21
At c~2nc, the upper 8 bits of the address register 20 are read from the tag memories 21a~2na.
The bits are each compared.

If the comparison results in a match, the replacement control circuit 20
a (hereinafter referred to as LRU(I, act Re5ent Us
e) A hit signal h1~ which means a match (referred to as a circuit)
hn is supplied. On the other hand, in the memories 1721b to 2nb, the lower 8 bits of the data stored in the data memory 3, especially the storage address of the data memory 3, are shown in the register 20, and the higher 8 bits are stored in the corresponding addresses of the tag memories 21&~2na. The same data is stored at the address that is the combination of the address and address.

As mentioned above, any one of the gates 21e to 2ne is opened by the output from the comparator of the cache memory where the error No. 1 has occurred, and the readout of any one of the cache memories 21 to 2n is performed as read data of the data memory 3. Data is supplied to the main processing unit 1. Also, when the LRU circuit 20a receives this hit signal, it sends the data to the cache memory where the hit signal occurred.
Change the replacement logic so that the cache memory is rewritten at the latest time.

On the other hand, when no hit signal is received from any cache memory, the LRU circuit 20a instructs to rewrite a specific cache memory according to a certain replacement logic.

The cache memory designated by this writes the data read from the data memory 3 to the memory unit 21b address indicated by the lower 8 bits of the address register 20, and tags the data indicated by the upper 8 bits of the address register 20. Write to the same address in the memory 21a.

In this way, by storing the data once read from the data memory 3 in any one of the data portions of the cache memories 21 to 2n, the next time the same address is accessed, it can be accessed at high speed (in a short time). Data can be obtained from table memory (cache memory) in a short time.

[Problem that the invention seeks to solve]

In the conventional cache memory system mentioned above,
Usually, the number of ways, that is, the number of addresses whose lower 8 bits are the same, is fixed, and the number of entries, that is,
The storage area of one cache memory is fixed. On the other hand, the number of ways and the number of entries depend on the processing form of the entire system including the cache memory system.

It varies depending on the business content and system configuration.

This makes the cache j% suitable for a particular system.
Even if an IJ system is constructed, it has the disadvantage that it cannot be applied to other systems, that is, its versatility is low.

There are also proposals to vary the number of ways and entries, but
Since the carriage tool memory with multiple ways is physically composed of one memory, the response speed in the case of multiple ways is slower than the response speed in the case of one way. ◇ [Means for solving the problem] In FIG.
0, 211, 212.21x are converted into modules, and the number of ways is changed by selecting the output of each module, -h, according to the information specified in the register 215 using the first selection means.

[For production]

The operations and effects shown in Figure 1 are shown in Figures 2 (a) and (b).
The explanation will be based on.

First, the CPU sets data in the register 215 to designate the number of modules to be operated simultaneously in parallel.

The signal M of the register 215 is supplied to the first selection means 213° and the replacement means 214.

This signal M applies to all modules 210, 211, 212
．． 21! For example, when specifying that four modules should operate simultaneously in parallel, the connection system will be as shown in FIG. 2(a).

That is, in FIG. 2(a), the first selection means 213
All memory modules 210.211.21x, 212
These outputs are outputted as a hit signal through an OR circuit (not shown).

Further, the second selection means outputs 6 bits of the outputs of the replacement information storage modules 2142 and 2143 in parallel using the mode signal M.

The replacement information is 1 corresponding to the path that can be transitioned between the ways created by the memory modules 210 to 212.
Each bit is allocated to the memory module 210.
212 constitutes 4 ways, it is 6 bits, when it constitutes 2 ways, it is 1 bit, and when it constitutes 8 ways, it is 28 bits.

That is, for the number of ways n, (n-1)+(n-2)+・
...+(n-n+1) bits are required. Also, for each bit, its logic level @1"O" indicates the direction of transition between ways.

In the example of this principle, we will explain the case where the number of ways is 4, so (4-1) + (4-2) + (4-3) - 6
5 or 6 bits are required. These 6 bits are stored in each of the replacement information storage modules 2142 and 2143.
Allocate and store bit by bit.

Therefore, the second selection means 2144 is instructed by the signal M to
6-bit parallel output for both replacement information storage module 2
3 bits are obtained from 142.2143 and combined and output.

In FIG. 1, the selection output of the second selection means 2144 is given to the change means, which changes the replacement information according to a predetermined change logic in response to the hit signal of the first selection means 213,
The contents of the storage locations indicated by the lower addresses b1 to b of the registers 20 of the replacement information storage modules 2142 and 2143 are updated.

Further, if the hit signal ho does not match, the replacement information is decoded and an instruction is given to rewrite a specific memory module among the memory modules 210 to 212.

On the other hand, when the CPU 1 specifies in the register 215 the number of memory modules to be operated simultaneously in parallel as "@2 modules", each selection means 213 and 214 takes the connection form shown in FIG. 2(b). That is, the register 2009 Bit l)
If the signal line 9 is, for example, logic “O”, each selector lR
213 and 214 have a connection form shown by a solid line, and in the case of logic 11', a connection form shown by a broken line.

As a result, the address allocation for the memory modules 210 to 212 becomes the allocation shown in FIG. 2(b)K. That is, in two memory modules the address "ooo =
~@IFF' addresses form a unit way.

Therefore, if there are 4 memory modules, the number of ways is 2.
becomes. Further, when the number of ways is 2, the replacement information only needs 1 bit as described above. Therefore, each replacement information storage module 2142.2143 has +! It is sufficient that one bit of replacement information is stored for each address of the +7 fresh memory module, and two storage modules 2 are required.
142 and 2143 are selected by the signal b9 at the ninth bit position of the register 20, and only one read signal is used. That is, the storage module 2142 has the memory module at vx″ooo=−−OFF=(hexadecimal)+7
2143 is the address 1100”~
11FF'' replacement information is stored.

As described above, in the present invention, the cache memory portion is modularized, and each hit signal is selectively output. Therefore, the response time from giving address data to register 2 to obtaining the hit signal is The number of ways changes, that is, the number of module combinations does not depend on the changer. In other words, the response time of the smallest unit of cache memory module is sufficient.

Moreover, since the replace information storage means of the replace means is modularized and the outputs thereof are combined and/or selected, the storage area of this storage means can be effectively utilized.Hereinafter, embodiments will be described in detail.

〔Example〕

In this embodiment, there are four memory modules,
For example, when the number of ways is 2 ways and 74 ways), the number of storage areas for each module, Rp, 2), and the number of IJ are 51.
The present invention is not limited to the embodiments described below, and when one memory module is provided, the number of ways can be changed to 2, 4, etc. in accordance with the spirit of the present invention.
8. ...2n number of ways can be configured, and various numbers of ways can be configured by appropriately combining the number of memory modules.0 CA) Replacement information Figures 3 (a) and (b) FIG. 3(e), which is an explanatory diagram of replacement information in the embodiment, is an explanatory diagram of a memory module to be replaced.

In the figure, each memory module is 51L~5ckX, 8~g
is the transition route, 6'F Eliplace information storage area W1 ~
W4 is a way 0 (1) The case where there are 4 ways in a 4-way configuration cache memory system will be explained with reference to FIG.
It is equipped with storage areas a-f corresponding to
The bit information is stored in one replacement information storage module 6aK referred to in the present invention, and the other 3-bit information of df is stored in another replacement information storage module.

The arrows shown in the transition paths a-f between the ways W1 to W4 are changed according to the following logic.

Each code displayed in the storage area d is assigned in advance to the direction of the arrow shown in FIG. 3(1k).

That is, the arrow of route a has a logic "1", the arrow of route C has a logic "11", the arrow of route C has a logic "O", etc.
..., the logic "Om" is assigned to the arrow of the path f.

When the direction of the arrow is reversed from that in the figure, the logic "11" is changed to the logic ""01, and the logic "Om" is changed to the logic "11."

Also, the more arrows point to each way, the more it is defined that the way has been referenced in the past.
The way that receives the most arrows is the way whose stored contents should be changed first.

Therefore, in the state shown in FIG. 3(a), way W2 receives the most arrows, and the memory module 5b of way W2 becomes the next memory module to be changed. When accessing memory,
If the cache memory does not store the data at the address issued by the CPU, the memory module 5b is changed and controlled.On the other hand, when accessing the cache memory, if any way, for example way W1, is hit, that is, if the CPU issues When the data at the address is stored, the directions of all arrows pointing toward way W1 are reversed. In this case, the path al
The direction of the do f arrow is the opposite direction and follows the dashed line. Therefore, data corresponding to each route a=f in storage area d)':! '1.1.0.0.1゜Om changed to @0.1.0.1.1.1'? :-
Accordingly, the next target way to update the contents, that is, the memory module becomes the way 3 memory module 5c.

(I+) FIG. 3(b) shows a case where the two-way configuration cache memory system takes a two-way configuration.

In the case of 2-way, there is only one transition route g,
Either way W1 or way W2 is selected as the change target ◇Each way W1. W2 is provided with storage modules 5a, 5b and storage modules 5c, 5d, respectively, and each storage module in a way is distinguished by the value of the 10th bit (y) position b9 of the address data given by the CPU to the cache memory system. It will be held in

Further, the replacement information is only 1 bit, and is stored in the storage area 6' of either the storage module 6a or 6b.

In FIG. 3(C), in the case of 4-way, each replacement target storage module is targeted for change when the content of each bit of the replacement information a=f shown in FIG. 3(e) becomes reverse logic. . When the corresponding module to be replaced is replaced, the replacement storage area is changed to the logical data shown in the figure.

Note that the rXJ mark in the replacement information indicates that it does not depend on the sign.

Therefore, in the case of a 4-way structure, the module 5a is route a,
The replacement logic based on each information of b and e is a-1)-c
ffll, module 5b routes a r d
, the replacement logic based on each information of f is i・d−f−1
If , module 5c routes.

The replacement logic based on each information of c and f is 5・C・T-1
In this case, the module 5d is designated as a change target when the replacement logic based on the information on the routes C1d and e is stone, a, and e-1, respectively.

On the other hand, in the case of a 2-way configuration, the module 5a is determined by the replacement information g and the sign of the 10th bit b9 of the address data given from the CPU, and each module is changed according to the relationship shown in FIG. 3(e). Specified as the target module.

CB) Description of example configuration FIG. 4 is a block diagram of one embodiment of the present invention.

In comparison with FIG. 1, the tag memory module 5 in FIG.
a-5diZ memory module I~IV210~212
corresponds to Further, the first selection means 213 in FIG.
Gate circuit 7 in the figure. Corresponds to OR circuit 05° selector 8 and encoder 9.

Furthermore, the changing means 2141 in FIG. 1 is replaced by the 4-way replacement logic gate 10.2-way replacement logic gate 14.4-way new LRU value creation gate 11.2 in FIG. The second selection means 2144 in FIG. 1 corresponds to the new LRU value creation gate 15, and the second selection means 2144 in FIG.
corresponding to storage modules 2142 and 2143 in FIG.
correspond to the LRU memory modules 6a and 6b, respectively.

In this embodiment, the address data has a total of 32 bits from A0 to AH, and the Oth bit position of the address data to
Each memory module is accessed using the address data ADO~8 up to the 8th bit position as a key. Therefore, each memory data section has a storage address of 21, ie, @512'.

Furthermore, in this embodiment, as will be described later, the data stored in each tag memory module 5a to 5d is only the upper address pins AD9 to AD31 of the address data and their control data, and the data memory shown in FIG. The stored data of No. 3 is not stored in the tag memory modules 58 to 5dK.

Data to be stored in the cache memory is stored in a cache memory data section ioo different from the data memory 3.

Therefore, the number of storage addresses in the cache memory data section 100 matches the total number of storage addresses in each tag memory module 5a to 5d.

In this embodiment, each tag memory module has 512 addresses, so the cache memory data section 100
The number of storage addresses is as follows: 4 (number of tag memories) x 5
12-20482048 pieces.

This is a memory whose addresses are the cache memory data section 100) Data is sent and received between the address and the Mm address.

Note) The cache-memory data section 100 may be configured as a memory with a series of addresses assigned by combining a plurality of tag memory modules as in this embodiment, but the cache-memory data section 100 may be configured as a memory to which a series of addresses are assigned. It may also be modularized.

When the cache memory data section 100 is modularized to correspond to each of a plurality of tag memory modules, each hit code ~h4, which will be described later, is used as an enable signal for each module.

If the character sim control circuit 200 and the cache memory data section 100 are constructed so as to be separable as in this embodiment, only the cache control circuit 200 can be made into an LSI and can be made smaller.

The configuration of the tag memory module 5a is shown in FIG.

Note that the other tag memory modules 5b, 5c, and 5d also have the same configuration as this tag memory module.
Address data (A9 to A3) from the 10th bit position to the 32nd bit position of the address data are stored in this tag memory 51.
1) is stored in each storage address addressed by the first bit to the ninth bit of the address data. First, the control data memory 54 includes a storage address corresponding to each storage address of the tag memory 51, and a validity data pit indicating whether the corresponding address of the tag memory 51 is used, and a tag memory. The operation of the 0 module in which the parity data bits of the address data stored at the corresponding addresses of 51 will be explained.

When address data is given to the address signals 1Ao-A31, the address data of the signal lines ADO~8 is given as the address to be accessed to the tag memory 51 and the control data memory 54. This causes the address signal @AD9~ from the tag memory 51. A number of stored data AD9' to AD31' corresponding to 31 are read out, and at the same time, validity data V and validity data P are read out from the control data memory 54. Comparison circuit 51 is connected to address signal line A
Data D9-31 and read data AD9'-31
If they match, a logic "1" signal is generated, and if they do not match, a logic "O" result signal is generated.

The parity check circuit 53 also checks the read data AD9.
Parity data is automatically generated through steps ' to 31' and compared with the read parity data P. Further, the parity check circuit 53 outputs the comparison result to the signal iPe as a parity check signal when the validity data V is logic "1", that is, the logic that the corresponding address is used as a cache memory.

Although the main signal MAPe is not disclosed in FIG. 4,
This signal line Pe may be considered to be combined with corresponding signal lines of other modules and connected to the CPUI shown in FIG.

The comparison result signal of comparison circuit 52 is supplied to AND gate A7. The AND gate A7 is supplied with the validity data V, the signal of the inhibit signal line INH, and the result signal.

Note that the inhibit signal line INH is connected to the CPU shown in FIG.
1, and a signal of logic "1#" is always supplied when the cache memory system is used from the CPUI.

Therefore, if the corresponding address is logically used as a cache memory, the computer A7 supplies the result signal of the comparison circuit 52 to the signal line.

Later, when a logic "1" signal is applied to the replace signal line rp, which will be described later, the tag memory 51 transfers the address data shown on the address signal lines AD9-31 to the address shown on the address signal lines ADO-8. Store. At this time, the parity generation circuit 81 simultaneously outputs the address signal line AD9.
It generates and outputs parity signals of address data shown in . For this reason, the control data memory 54 is
This parity signal is stored at the address shown on address signal lines ADO-8.

The operation of the embodiment will be described below with reference to FIG.

(C) Operation description a; 4-way operation When operating the cache memory system in 4-way mode, a signal of logic level "11" is supplied to the mode signal line M to the cache control circuit 200.

Mode signal i! JM is connected to the gate circuit 71 selection gate 11.about.13.

In the gate circuit 7, when a logic "1" signal is supplied to the mode signal line M, the AND gate Al is activated.

A3. A4. A6 is opened, and IAI is closed. By closing IAI, the output of this gate IAI becomes logic 'Om'.
A5j-! , closed and inhibited gate I A 2. To I A 3! It will be released. As a result, the hit signals output from the tag memory modules 5a to 5d, that is, the result signals explained in FIG. 5, are output from the AND gate Al.

A3. A4. A6 and gate IA2. The 0 outputted through IA3 and the OR gates 01 to 04 and each hit signal h (h+ to h4) outputted from the gate circuit 7 are logically summed at the OR gate 05, and the hit/unhit signal is sent to the hit signal line H. The cache memory access means (not shown) monitors the generation time of the signal on the hit signal line H, and if a signal indicating a hit is received within a certain period of time, the cache memory data unit 100 outputs a signal indicating a hit. A read signal R is supplied to the terminal.

On the other hand, the hit signal line ~h4 is also supplied to the selector 8. The selector 8 selects a hit signal line ~h4 or a replacement signal line rP to be described later by a signal on a select signal line ch supplied from an access means (not shown).
Connect one of s to rp4 to the output terminal.

On the select signal line ch, a logic "0" signal is given when it is necessary to obtain data from the cache memory system, and a logic @1" signal is given when data is written to the cache memory system. In the selector 8, the signal on the select signal line ah is logic “O”
If the hit signal i! ! Connect ha-h4 to the output terminal.

The encoder 9 encodes the signals on the hit signal lines h1 to h4 into a 2-bit code and outputs it. This output is given to the cache memory data section 100 as a part of the address signal.

As described above, upon receiving the read signal R, the cache memory data section 100 reads data from the address indicated by the output code from the encoder 9 and the address data of the address signal lines ADO to 8, and reads the data to the data line. Output data.

Further, in parallel with these operations, the LRU memory module 6 JLI 6 b+replace logic gates 10, 14 . New LRU value bottom game) 1
1.15. Select gates 12.13 operate.

Each of the LRU memory modules 6a*6b is
This memory has the same number of storage addresses as each of the tag memory modules 58 to 5d.

Each storage address can store 3 bits of data, and its read terminal and/or write terminal can be connected to a--a--, as shown in FIGS. 3(a) and (e), in the case of 4-way.
6-bit data of f is output or supplied.

Further, each storage address of the LRU module corresponds to each storage address of the tag memory modules 5a to 5d, and replacement information for the storage address data of all the corresponding tag memory modules 58 to 5d is stored.

Regarding the initial value of the replacement information stored in the LRU memory modules 6a and 6b, an access means such as a CPU transfers a value according to the configuration of the cache system to the LRU memory module via a line (not shown) when the system starts operating. It may be loaded and stored. Alternatively, when the control circuit 200 is created, the value may be set in another nonvolatile memory in advance, and the value may be automatically stored in the LRU memory modules 6a and 6b in response to a signal given to the mode signal IRM. .

In the case of 4-way structure, LRU memory module 6a,
When the signals of the address signal lines ADO~8 are applied to the LRU memory modules 6a and 6b as shown in FIG.
The 6-bit replacement information, in which all 6 bits are valid, explained in a) is transferred to the 4-way replacement logic gates io and 4.
The output is supplied to the new LRU value creation gate 11.

FIG. 6 is a detailed circuit diagram of the 4-way replacement logic gate 10° and the 4-way new LRU value creation gate 11.

Each of the hit signal lines h1 to h connected to the gate circuit 7 is connected to a NOR gate (Nl) of a 4-way replacement logic gate. The NOR gate N1 connects each hit signal line b+ -
When at least one of ha is a logic "1" signal indicating a hit, the output is set to logic "0". As a result, AND gate 7 and AND gate IA with inhibit gate
4 to IA6 are closed. Therefore, the four-way replacement logic gate 10 does not output a signal specifying the tag memory module to be replaced.

On the other hand, if all of the hit signal lines h1 to h are at logic "O", that is, if there is an unhit state in which no tag memory module is hit, these games)A
7. IA4 to IA6 are open ◇ Each gate A7. IA4 to IA6 detect whether or not each tag memory module should be updated based on the output a to f of each LRU module using the logic described above as shown in FIG. 3(C).

Therefore, in the unhit state, a signal of logic "1m" is output from any one gate.

The input gate 8 is connected to the inhibit signal line INH explained using FIG. Therefore, the signal from the 4-way replacement logic gate 10, IJ! (rp1') ~ (r
A signal of logic level .degree.1" is supplied to any one of the signal lines (rpl') to (rp4'). These signal lines (rpl') to (rp4') are connected to the selection gate 12 shown in FIG.

The signal #(rp white is a replacement module designation signal for changing the tag memory module 5a shown in FIG. 4, and the signal line (rp2') is a replacement module designation signal for changing the tag memory module 5b shown in FIG. 4. The module designation signal is the signal line (rp3'), which is the replace module designation signal for changing the tag memory module 5C shown in Figure 4, and the signal line (rp4') is the replacement module designation signal for changing the tag memory module 5D shown in Figure 4. Replace module designation signals for each are supplied.

4) The new LRU value calculation gate 11 receives the replacement information supplied from the LRU memory modules 6a and 6b,
The hit signal (Hira) supplied from the gate circuit 7 [No.
! h, to h4 signals) and a replace module designation signal supplied from the 4-way replace logic gate 10, the OR gate group 06 to 015 and the AND gate group with inhibit gates IA7 to IAI2 output the replace information. Update.

The logic of this update has been explained with reference to FIG. 3(C), so a detailed explanation will be omitted.
The logic is shown in FIG. 1, and the operation when a logic "1" signal is supplied to the line 1 ht will be explained.

The 4-way replacement logic gate 1o becomes inoperable due to the output of the NOR gate N1, and one input of the OR gates 06 to 09 all becomes logic @O''. Therefore, the OR game)
As for the outputs of 06 to 09, only the OR gate 06 outputs a signal of logic 1" as if the hit signal ah I was input, and the others become logic 0". Since the output of OR gate 06 is logic "1" and the others are logic ''01, gate IA7.IA
8. IAI1 is opened and the other gates IA9. lAl
0. lAl2 is released. Or game) 011-015
are supplied with logic "O" signals from OR gates 07 to 09 and signals from gates IA7 to IAI2, but since gates IA7.IA8.IAII are closed, the output is logic "0". So, in the end, all ORGATE 010~
The output of 015 becomes logic @0''.

That is, the replacement information has been converted to correspond to the state shown by the broken line in FIG. 3(a).

In FIG. 4, the outputs 1 (rpl') to (rp4) of the 4-way replace logic gate explained in FIG.
) (shown as (rp')) is supplied to the selection gate 12, and the replacement information of the 4-way new LRU value bottom gate 11 is supplied to the selection gate 13.

The selection gate 12 further receives a 2-bit output from a 2-way replace logic gate 14, which will be described later, a mode signal from a mode signal line M, and an address signal @AD9, and in response to these, a replacement signal is output only when the unhit state is present. A signal of logic "11" is generated on one signal line among the lines rpl to rp4.

In addition, the selection gate 13 responds to the signal on the mode controller M, and in the case of 4-way, the 4-way new LRU value creation gate 11
and supplies this output to each LRU memory module 6a, 6b.

The LRU memory modules 6a, 6b replace the storage addresses corresponding to the address data of the address signal lines ADO-8, which have been continuously applied since the time of reading the replacement information, with the replacement information supplied from the selection gate 13dTh.

On the other hand, if no hit signal is generated from the tag memory modules 58-5d, one of the tag memory modules 58-5d is selected by the replace signals rpl-rp4 from the selection gate 12.

At the same time, the replace signals rpl to rp4 are applied to the selector 8. It is given to the cache-memory data section 100 via the encoder 9 as part of the address data.

As mentioned above, the designated tag memory module, for example, the tag memory module 5a, stores other parts of the address data,
That is, data shown on signal lines AD9 to AD31 is stored. Further, when data is read from a data memory (not shown), the read data is supplied to the cache memory data section 100 via a data line. The cache memory data section 100 writes this applied data to the storage address indicated by the address data of the address signals 1ADo to 8 and the code data of the encoder 9 of the cache control circuit 200 at the write timing indicated by the signal line W. Storing O b; 2-way operation Also in case of 2-way configuration, tag memory module 5&~5d
The operation is the same as in the case of the 4-way configuration.0 In the case of the 2-way configuration, the signal on the mode signal line M is
''. Therefore, only the gate 7, selection gate 12, and selection gate 13 operate differently from the case of the 4-way configuration.

At gate 7, a signal of logic 10'' on mode signal line M closes AND gates Al, A3, A4, and A6. Also, gate IAI is opened.

As a result, the signal on the address signal line AD9 is transferred to the gate IA.
IA2. A2. Supplied to IA3°A5.

Gate IA2. IA3 has address signal line AD9 as logic@
01, the tag memory module 5a, 5 is released.
Pass the hit signal of c. Also, gate A2. A
5 is opened when the address signal line AD9 is at logic 11'', allowing the hit signals of the tag memory modules 5b and 5d to pass through.

Therefore, the 10th bit position (AD9) of address data
Two hit signals are derived from gate 7 by switching according to the logic of .

These hit signals are supplied from the OR gate 05 to the access means in the same manner as in the 4-way case, and
The signal is encoded by the encoder 9 via the selector 8 and supplied to the cache memory data section 100 as an address signal.

Furthermore, the hit signals sh+, hat! or gate 01
Further, the hit signals Hha and ha are combined into one hit signal @hb via an OR gate 17 51.

These lines ha and hb are supplied to a 2-way replacement logic gate 14 and 2 to a new LRU value calculation bottom gate 15.

The two-way replacement logic gate 14 receives this signal aha.
, hb hit signal and the LRU memory module 6a,
6b output terminals a and d, a 2-bit replacement information signal, an address signal line AD9 signal, and a mode signal line M.
mode signal is supplied, and when the hit signal becomes a hit state, two signals related to replacement are transferred to the selection gate 12. In addition, the new LRU value bottom gate 1
5 also transfers the replacement information to be written next to the selection gate 13.

FIG. 7 shows a detailed gate circuit of the 2-way replacement logic gate 14.2-way new LRU value creation gate 159 selection gate 12.13.

2-way replacement logic gate; signal lines a and d led out from the 2-way replacement logic gate 14 and the LRU memory modules 6a and 6b
(signal lines of terminals a and d) and address signal line AD
The signal of the signal line AD9 of O to 31 is connected to the AND gate IAI3 with inhibit gate and the AND gate A9.
supplied to This gate IAI3 outputs the signal at the terminal a of the LRU memory module to the OR gate 018 when the address signal line AD9 is at the logic "O", and the gate hA9 outputs the signal at the terminal a of the LRU memory module to the OR gate 018 when the address signal line AD9 is at the logic "1". A signal is output to OR gate 018.

That is, these two games (IAI 3 and A9) select 1-bit replacement information necessary in the 2-way configuration from the 2-bit outputs of the LRLI memory modules 6a and 6b by the logic of the address signal line A9.

On the other hand, when a logic "1" signal indicating a hit is supplied to either of the hit signal lines ha and hb, the NOR gate N2
．． ANDGATE A10. The AND gate lAl4 with inhibit gate causes the two-way replace logic gate 14 to output logic @02. Conversely, if no human is indicated, gate AIO.

A logical 1 output is made to either side of IAI 4.

2-way new LRU value creation gate; 2-way new LRU value creation gate 15 is or game-)01
9,020,021 and an AND gate IAI 5 with an inhibit gate, and generates 1-bit new replacement information. ◇ Now, suppose that the output terminal a of the LRU memory module 6a is a logic ``11'' signal, and the address AD9 is a ``10'' signal. '', the OR gate outputs a logic ``1'' signal.Next, assuming that both hit signal lines hathb are in the unhit state, that is, the logic is ``Oo'', the AND gate AIO outputs a logic ``1'' signal. 1'' signal is output.The AND gate A10 is connected to the tag memory module 5a shown in FIG.
, 5b, which generates a change instruction output. Therefore, the hit signal @h a s at the gate 15, that is, the hit signal line h of the tag memory modules 5a, 5b.
t.

The OR gate 019 performs a logical OR with the output of OR gate h.

On the other hand, the game) IAI4 outputs a replacement instruction for the tag memory modules 5c and 5d shown in FIG. A replace instruction is output as a logic "1" signal.

The table below, Table 1 is a table of output logic values of gate 15. In other words, if the hit tag memory module is the module 5c, 5d "C" corresponding to hb, the final output X is set to logic "1", Next, the modules to be corrected are made to point to modules 5a and 5b.

Selection gate 12; In selection gate 12, AND gate A of gate 14
The output signal of IAI4 (IO and gate) and the signal (rp
One of them (l') to (rP4') is selected by the signal of the mode signal line, and the two output signal lines of the gate 140 are distributed to four signal lines by the signal of the address signal line AD9.

That is, when the mode signal line M indicates logic "1m", therefore,
When 4-way structure is specified, AND gate A
l1-Al4 are opened and gates IAI6 to IAI
9 is closed, and the output signals (rpl') to (rp4') of the 4-way replacement logic gate 10 are output to the OR gate 02.
It is output from the selection gate 12 via 2 to 025.

On the other hand, when the mode signal sM indicates logic "O", the AND gates A11 to A14 are closed. Furthermore, one of the input terminals of each of the AND gates IAI6 to A19 with inhibit gates becomes logic 11'. In this case, if the logic of address signal line AD9 is 10m, IAI 6 and l
A18 becomes open, and the two outputs of gate 14 are outputted via OR gates 022 and 024. Also, when the address signal line AD9 is logic 1',
．． lA19 is selected, and the two outputs of gate 14 are outputted via OR gates 023 and 025.

Therefore, gate lA13. of gate 14. One of the replacement information rpl selected by A9゜018 is logical @
1” and is not in the hit state, the tag memory module 5a* according to the address data shown in the address signal AD9
One tag memory module of the group 5b is instructed to be replaced. Conversely, if one of the replacement information rpt is at logic °0'' and is not in the hit state, the address signal A
One tag memory module of the pair of tag memory modules 5c and 5d is instructed to be replaced according to the address data shown in D9.

Selection gate 13; Similar to the selection gate 12, the selection gate 13 also receives the outputs a' to f' of the four-way new LRU value creation gate 11 shown in FIG.
and the output of gate 15 are selected according to the logic of mode signal line M and address signal line AD9.

1A20. lA21. lA22. lA23 is closed and AND gates A15 to A2 for 4-way configuration
0 is released. Therefore, the outputs a' to f' of the 4-way new LRU value creation gate are output from the selection gate 13,
It is supplied to LRU memory modules 6a and 6b, respectively.

On the other hand, when the logic of the mode signal line M is "0",
The 4-way gate group AI5 to A20 is closed, and the other gates A20 to IA23 are enabled. ``Furthermore, the outputs of the AND gates A16, A17, A19, and A20, that is, the 4-bit replacement information of terminals e, e, and f, which are unnecessary in the case of a 2-way configuration, are all set to logic ``02''.

This gate group lA20. lA21. lA22. lA2
3, the output of one LRU memory module selected by the logic of the address signal line AD9 is corrected by the correction value X output from the gate 15, and the output of the other LRU memory module is corrected. It is configured to output the output of the LRU memory module as is.

For example, when the logic of address signal line AD9 is @o1, L
Gate air A13. from the way the RU memory module comes out. A9
．． 018 selects the output of terminal a as replacement information. At this time, the selection gate 131c Oite+X, Ge)lA20. lA23O is open. Therefore, gate air A20 OR gate 026 outputs the output X of gate 15.
The gate lA23 directly outputs the output of the terminal d of the LRU memory module 6b as new replacement information on the terminal d side via the OR gate ◇ Conversely, the logic of the address signal aAD9 When it is "1", game lA21 and lA22 are opened. Therefore, the readout method of the terminal a of the gate lA21eXLRU memory module 6a is the same as that of the terminal a, and the gate lA22 is
The output X of 5 is output as the output value on the terminal d side.

In FIG. 4, the values output in this way are stored in the LRU memory modules 6a and 6b.

CD) Modifications/Applications The present invention is not limited to the above embodiments, but may be modified in various ways.

Application is possible.　　.

First, as a memory module, although only the tag memory module was explained in the embodiment, the cache memory data 5
The evening part may be included in the memory module.

Second, the number of memory modules is 4-1 in the above embodiment.
: Although the explanation is limited to joules, the number is not limited to this and may be any number that matches the maximum number of ways of the cache memory system. Further, the number does not necessarily have to match the maximum value.

That is, in the present invention, it is sufficient that the comparison means outputs a signal indicating hit/unhit in response to one access by a plurality of memory modules in parallel, and if the number of memory modules is plural, the number There are no limits.

Thirdly, in the embodiment, LRU memory modules 6a and 6bT have been described as replacement information storage modules, but the present invention is not limited to this.

The rep source information storage module also requires 0 if it is a memory in which multiple pieces of replacement information can be read in parallel.
Any device that stores the replacement information of the other side may be used.

〔effect〕

As described above in detail, according to the present invention, the cache memory has a modular configuration, and each module has a pictograph/
Since the unhit state is loaded and unloaded in parallel regardless of the configuration of the cache memory, the detection output can be obtained in a short time.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams explaining the principle of the present invention, and Figures 3 (a) to
(e) is an explanatory diagram of the replacement information of the embodiment, Fig. 4 is a block diagram of the embodiment, Figs. 5 to 7 are detailed circuit diagrams of main parts of the embodiment, and Fig. 8 is a conventional block diagram. . In the figure, 210 to 212 are memory modules, 213 is a first selection means, 214 is a replacement means, 2142, 21
43 is a replacement information storage module, 244 is a second selection means, and 2141 is a change means. Takume and Remote Remoji Giant's AT Filoso 20 Season 5 Oral Procedures Amendment (Method) Showa Year Month Date Showa Year Patent Application No. 22-2-2 +;, I: +゛1 38 Person making the amendment Relationship to the incident Patent applicant address: O15, Kami Elementary School, Nakahara Ward, Yozaki City, Kaminoyo Prefecture (
522) Name Fujitsu Ltd. 4, Agent Address Nakahara-ku, Yozaki City, Kanagawa Prefecture” - 10151 Chi-ichi 8, Ogawa Naka, Contents of amendment (1) “(a) stated in page 47, line 15 of the specification.
)~(e)'' is corrected to r(at~(C)''.

Claims (4)

[Claims] (1) A data memory to which consecutive addresses are assigned and information is stored in each address, a means for specifying each address of the data memory with address data, and a part of the data that constitutes the address data. a plurality of memory modules each having the same storage capacity and storing at least some other data of the address data; a means for outputting storage information of memory modules that match the comparison; a configuration specifying means for specifying the number of memory modules to be operated simultaneously in parallel; and a specification of the configuration specifying means. When the first selection means selects a memory module to be compared based on the comparison means and the output of the comparison means selected by the first selection means shows a mismatch, one of the given address data of the specific memory module is selected. replacement means for replacing the storage information at the address indicated by the data in the memory module with another part of the address data, and the replacement means includes a storage address having the same number of addresses as the number of addresses of the memory module. a replacement information storage module that stores, at each storage address, multiple bits of replacement information for specifying the specific memory module to be replaced next; A cache memory system comprising: second selection means for selecting a combination of outputs of storage modules; and change means for changing the selected replacement information according to the specified configuration of the configuration specification means and the comparison result of the comparison means. . (2) The second selection means outputs a selective combination of the outputs of the plurality of replacement information storage modules according to the number of sets of cache memory modules designated by the configuration designation means;
The cache memory system according to claim 1, characterized in that the cache memory system is means for switching the output of only a single replacement storage means. (3) The changing means includes a number of changing logic circuits corresponding to the number of configurations that can be specified by the configuration specifying means, and a changing logic means that changes the replacement information selected by the second selecting means to the configuration specified by the configuration specifying means. 2. A cache simulator system according to claim 2, further comprising a selection means for supplying the information to the cache memory. (4) A patent characterized in that a plurality of replacement information storage means share and store data corresponding to the number of bits of replacement information corresponding to the maximum number of replacement information that should be operated simultaneously in parallel. A cache memory system according to claim (2).