JPS62195169A - Large scale integrated circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a large-scale integrated circuit, and more particularly to a large-scale integrated circuit provided with a testability film.

[Prior Art] Traditionally, large-scale integrated circuits have been designed in units of circuit blocks with specific functions in order to prevent deterioration in design quality and shorten the design period as the degree of integration has rapidly increased. For the circuit test, a scan path was established to facilitate testing of flip-flops in which flip-flops are connected sequentially and operated as shift 1 to registers, and the fault detection rate was improved. -1- and is effective in reducing the number of test patterns.

[Problems to be Solved by the Invention] However, although the conventional large-scale integrated circuits mentioned above are equipped with a scan path that is designed to facilitate testing of flip-flops in consideration of circuit testing, the scan path is The signal observation point on the campus is only one output terminal for one input terminal, which is effective in improving the fault detection rate and reducing the number of test I/patterns. Therefore, there is a drawback that it takes time to determine whether the used chips are good or bad and to identify the defective areas.

SUMMARY OF THE INVENTION An object of the present invention is to provide a large-scale integrated circuit in which it is possible to determine the quality of a used chip due to a failure of a flip-flop tube and to limit a defective area of a flip-flop tube in a short time.

1' Means for Solving Problems] The large-scale integrated circuit of the present invention has a plurality of circuit blocks including a plurality of flip-flop blocks, and the flip-flops included in the plurality of circuit blocks A scan path is provided for testing the flip-flops which are sequentially connected to operate as shift 1 to registers. It is constructed with a selector circuit which outputs the output signal of the scan path as a shunt l- and outputs other output signals from this circuit block during normal operation.

Embodiment] Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a schematic flow diagram showing one embodiment of the present invention.

The design of this embodiment begins with the design of the system by a circuit block 1.1 having each function. , lh, 1c.

The logic stage IT L is divided into 1d, and its placement and wiring is done within its wiring area for each circuit block, and then the wiring area between each circuit block and the input/output area are performed using the wiring area between circuit blocks. It is designed for wiring.

In this embodiment, circuit blocks 1-, lb, 1c, 1. Multiple free files included in
A scan path 2 is provided to facilitate testing of the flip-flop 11, in which the flip-flops 11 are sequentially connected and operated as a shifter l-1 and a register, and the circuit blocks ]-, ]b, and 1c are each provided with a selector. A circuit 3 is provided and has a two-ellipse configuration.

FIG. 2 is a circuit diagram showing an example of the selector circuit 3.

This circuit has logic circuits 31-33'! fIi is established.

The output signal ■5o of each scan path 2 of the circuit blocks ]-, ], b, ]c is shunted and input to the selector circuit 3, and the output signal ■5o of the scan path 2 of each circuit block ]-, ], b, ]c is input to the selector circuit 3. Campus 2 output signal VSO is selected,
Observation can be made at the output terminal 7 via the output buffer 6 6 Conventionally, the observation point for the scan path signal was only the output terminal 75 of the scan path with respect to the input terminal 45 of the scan path. , in the configuration of this embodiment, the circuit blocks IS, lb, 1. Since the output signal VSO of path 2 can be observed, it is possible to perform a failure test of the Noritsu flop 11 at high speed. Therefore, it is possible to determine whether the chip used is good or not, and whether the flip-flop 11 is defective when the circuit block is installed. It becomes possible to limit the area at high speed, and the output terminal 7 receives other output signals (2) from the circuit block except during test operation. It is effectively used as the 0 output terminal.

〔Effect of the invention〕

As described above, the present invention has a selector circuit that can divide and observe the output signal of a scan path in which a plurality of flip-flops are sequentially connected to operate as a shift register, in circuit block units. It is possible to perform a failure test at high speed, and therefore, it is possible to quickly determine whether the chip used is good or bad and to limit the defective area of the flip-flop tube in units of circuit blocks at high speed.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of the selector circuit shown in FIG. 1. 1-, ], lb, lc, 1d... circuit block,
2...Scan path, 3...Selector circuit, 4s.
...Input terminal, 5s...Input buffer, 6,6s...
・Output buffer, 7,7s...Output terminal, 11...
Furi Sofflop, 31-33...logic circuit.

Claims (1)

[Claims] A large scale device having a plurality of circuit blocks including a plurality of flip-flops, and provided with a scan path for testing the flip-flops in which the flip-flops included in the plurality of circuit blocks are sequentially connected to operate as a shift register. In the integrated circuit, the selector circuit is provided in the arbitrary circuit block and outputs a shunt output signal of the scan path of this circuit block during test operation, and outputs another output signal from this circuit block during normal operation. A large-scale integrated circuit characterized by: