JPS6220035A - Virtual computer system control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a control method for a virtual computer system, and particularly to processing of external interrupts in a virtual computer system.

[Background of the invention]

Conventionally, as a method for improving the performance of a virtual computer system, a virtual machine (Virtual Machine) has been proposed as disclosed in Japanese Patent Laid-Open No. 55-112651.

VM (hereinafter abbreviated as VM)
A control program (virtuatMachi) that manages
ne Control Program below, VMCP
A known method is to directly execute the process on hardware without using software simulation. However, in this method, privileged instructions for manipulating a status register (hereinafter referred to as Sr, also referred to as PSW) that manages the execution mode of the computer, the execution level of the computer, etc. are also directly executed in the VM.

Since the execution level of the real computer is the same as the execution level set by the VM, it is difficult to input external interrupts such as I10 termination to the real computer in a timely manner.

A virtual computer system is a computer system that controls the resources of a single real computer (central processing unit, main storage device, input/output device, etc.) as if there were multiple computers. Each of these multiple computers is a virtual computer (VM).
), and is simulated by a virtual machine control program (VMCP) so that it is functionally equivalent to a real computer. On each VM there is an operating system (
O8) can be executed, and a plurality of different O8s can be executed at an apparent time on one actual computer. The VMCP is executed in a privileged mode to control the hardware of the actual computer, and the VM generated by the VMCP is executed in a non-privileged mode. Since the VM operates in a non-privileged mode, a privileged instruction on the VM is reported to the VMCP as a privileged instruction exception, and the VMCP executes it by performing simulation. FIG. 1 shows a conceptual diagram of VM privileged instruction simulation.

Next, among the simulations of the above privileged instructions.

An overview of the simulation process for privileged instructions that control Sr will be explained. M0 by the applicant as a specific calculator
The architecture of the 68000 microcomputer will be explained as an example (for example, Kida et al., "68000 Microcomputer", Maruzen).

FIG. 2 shows the configuration of S'' in MC68000.

Sr is privileged mode/unprivileged mode, execution level.

Consists of condition code, etc. The execution level is represented by 3 bits and has execution levels from 0 to 7. This execution level is useful for hardware control of whether or not to accept external interrupts.

When an interrupt level signal with a higher number than the execution level occurs, the interrupt is accepted, and the new execution level is set to
It becomes the interrupt level that has just been established.

Now, the simulation of privileged instructions is performed as follows.

(1) Simulate the privileged instruction on VM S'.

(2) If the execution level of tsr becomes low as a result of the privileged instruction simulation, check whether the asynchronous interrupt for that VM is bending.

(3) When the condition in (2) is satisfied, process the interrupt factor causing bending, and then restart the VM.

In a virtual computer system, if all of the above processing is performed by VMCP, the performance will be significantly degraded compared to when it is executed by O8 under a real computer.

To prevent this, there is a firmware assist (VMA) that supports execution of commands on the VM. But the VMAs
The processing is to take over some of the processing of VMCP, and is basically the same as simulation.

As a countermeasure to this problem,
In Publication No. 1, a method is adopted in which a privileged instruction is directly executed at high speed in a VM by hardware, and for this purpose, a dedicated Sr for the VM is provided.

However, this increases the amount of hardware required.

In addition, in patent application Japanese Patent Application No. 186731/1986, V
A method is shown in which M occupies Sr of a real computer.

A problem with the method of having the VM occupy the Sr of the real computer is that the VM directly controls the Sr of the real computer, and therefore the execution level of the real computer is arbitrarily controlled by the VM. For this reason, for example, when VM#O is operating,
Even if the I10 operation issued earlier by M#1 is completed, if VM#0 raises its execution level and processes the end interrupt request, it will not be accepted by the actual computer, and input/output control in VMCP will be performed. will not be carried out efficiently. This may be a factor that degrades the performance of the entire system.

[Purpose of the invention]

The present invention makes it possible to accept interrupts without depending on the execution level indicated by 3r while the execution level of the real computer is being executed in the VM in a virtual computer system that directly executes privileged instructions in the VM. purpose.

[Summary of the invention]

In order to achieve the above object, in the present invention, when an interrupt request is generated from the outside while the VM is being executed, regardless of the execution level indicated by 9r of the actual computer.

The feature is that the above problem is solved by allowing the -C interrupt to be accepted in the actual computer.

[Embodiments of the invention]

Hereinafter, an embodiment of the present invention will be explained with reference to FIG.

In this embodiment, a register VMF LG3 indicating that the VM is being executed is used.
, inverter 4 which takes the negation of its output, S for real computer
It consists of an AND gate 2-1, 2-2, and 2-3 that ANDs the execution level 1-1 indicated by rl and the output of the 1-inverter 4.

The operation of the present invention is as follows. When control is transferred from VMCP to VM, VM'
FLG is set. A negative signal of the output signal of VMF'LG 3 is obtained by an inverter 4 and an AND gate 2-
1 to 2-3 are ANDed with the execution level. As a result, when the VM is running, i.e. when VMFLG 3 is set.

The outputs of AND gates 2-1 to 2-3 are all 0.

In this embodiment, this output is taken as the effective execution level of the actual computer. That is, the execution level of the actual computer during VM execution is O, and interrupts at each level can be accepted.

Although not shown in this embodiment, when an external interrupt is accepted, VMFLG 32>!
Reset and V M CP K! Ri W! Input processing is performed. While VMCP is running, VMFLG
Since 3 is 0, execution level 1 is set to 8rl.
-1 directly becomes the effective execution level 1-2 of the actual computer, and -based on the priority interrupt method - becomes a normal interrupt operation.

FIG. 4 shows the microcode flow at the time of execution of a VMEXEC (VM execution start) instruction, which is the timing of setting/resetting the VMFLG3, and at the time of an external interrupt. Hello, VMFLG is VMEXE
It is paid by the C instruction and set by the occurrence of an external interrupt.

In the following embodiments of the present invention, an example is shown in which the control is implemented using an AND gate, but this control can also be easily implemented using microcode of a computer.

〔Effect of the invention〕

According to the present invention, in a virtual computer system in which a VM directly controls 3r of a real computer, external interrupts are always accepted while the VM is running while maintaining high speed by allowing the VM to directly control Sr of the real computer. This has the effect of increasing the efficiency of input/output processing. The increase in hardware cost for this is almost negligible.

[Brief explanation of the drawing]

Figure 1 shows the VM of a conventional virtual computer system.
A conceptual diagram of the simulation of privileged instructions. FIG. 2 is a diagram showing the configuration of a status register using a microcomputer M068000 as an example, FIG. 3 is a configuration diagram of an embodiment of a virtual computer system according to the present invention, and FIG.
FIG. 3 is a diagram illustrating a situation in which a mode flag is set/reset.

Claims (1)

[Claims] 1. A virtual computer system in which a virtual machine (VM) directly controls a state register that controls the execution state of a computer, and allows a single real computer to efficiently execute multiple operating systems. The computer has a register that identifies whether the VM is running, and when the identification register indicates that the VM is running, the execution level of the computer held by the status register is masked and interrupts can be accepted. A virtual computer system control method that is characterized by being able to control so that interrupts are always accepted. 2. The virtual machine system control method according to item 1, wherein if an interrupt is accepted during execution of a VM, the identification register is reset to indicate that a non-VM is being executed.