JPS62203070A - Loran c receiver - Google Patents

Abstract

PURPOSE:To obtain a measuring result having high reliability even when noise is superposed, by performing the detection of a three-cycle position on the basis of one LORAN pulse obtained by averaging a plurality of LORAN pulses. CONSTITUTION:Eight LORAN pulses arranged at an equal interval and the LORAN pulse having an interval longer than said interval are outputted from a receiving part 12 and given to a signal synchronous circuit 13 to form a synchronous pulse 32 at the cross point of a main carrier. A sampling pulse 34 is generated from the pulse 32 by a sampling pulse forming circuit 16 and each of the LORAN pulses are digitalized by an A/D converter circuit 16 to be stored in a memory part 18 through CPU 17. CPU 17 allows the synchronous pulse 32 to be synchronous to the three-cycle position of the LORAN pulse and, by the completion of synchronism, the time difference of a master station LORAN pulse group and a slave station LORAN pulse group is measured from the synchronous pulse 32 and the pulse made synchronous to a slave station LORAN pulse and the selection of one hyperbola is performed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a Loran C receiver that is used to determine the current location using Loran C signals.

When using a sublimb king Loran C receiver, it is necessary to detect the three cycle positions of the pulses of the Loran C signal. In this pulse waveform, the ratio of the peak values of the waveform in the second cycle and the third cycle is approximately 1:2, so conventionally, the peak value of each cycle is sampled, and the peak value of the waveform in the second cycle and the third cycle is sampled. By checking , the 3-cycle position is detected.

In the method described above, the peak value is compared for each pulse in order to detect the 3-cycle position, but if noise etc. are superimposed, the peak value may change. Since the peak value fluctuates, if the 3rd cycle position is detected based on the peak value, the position is likely to be detected incorrectly, reducing the reliability of the measurement results.

The present invention was devised to eliminate the above-mentioned drawbacks, and an object of the present invention is to provide a Loran C receiver that can obtain highly reliable measurement results even when noise is superimposed.

. Divination n: For the purpose of fortune-telling.

The Loran C receiver of the present invention includes a signal synchronization circuit that generates a synchronization pulse that is synchronized with the Loran pulse, an A/D conversion circuit that converts the four run pulses into a digital signal, and this A/D
It includes a sampling pulse generation circuit that sends a group of sampling pulses to the conversion circuit, and a CPU that analyzes the waveform of the digitized Loran pulse.

The monthly signal synchronization circuit generates a synchronization pulse that is synchronized with the Loran pulse output from the receiver that receives the Loran C signal. The sampling pulse generation circuit sends a group of sampling pulses having a fixed time relationship with this synchronization pulse to the A/D conversion circuit. The A/D conversion circuit converts the Loran pulse into a digital signal based on this sampling pulse group.

The CPU analyzes this digital signal to determine whether the synchronizing pulse is at the 3rd cycle position, and sends a transfer signal to the signal synchronization circuit to move the synchronous pulse to the 3rd cycle position.

Figure 1 is a block diagram showing the configuration of an embodiment of the present invention. The antenna section 11 that receives the Loran C signal is connected to the receiving section 12, and its output, the Loran pulse 31, is
It is led to a signal synchronization circuit 13 that generates a synchronization pulse 32 synchronized with this Loran pulse, and an A/D conversion circuit 15 that converts it into a digital signal. Reference frequency oscillation circuit 14
The output from the oscilloscope is also guided to the signal synchronization circuit 13, where it is internally frequency-divided to generate timing signals necessary for operation. The sampling pulse generation circuit 16 generates a sampling pulse group 34 according to two signals: a synchronization pulse 32 output from the signal synchronization circuit 13 and a synchronization completion signal 33 that indicates that synchronization has been completed, and generates a sampling pulse group 34.
I am sending it to 5. The CPU 17 includes an A/D conversion circuit 1.
A signal obtained by digitizing the Loran pulse from 5 and a synchronization completion signal 33 for instructing the timing of taking in this signal are connected. A keyboard 19 for operation is connected. A storage unit 18 is provided for storing a signal obtained by digitizing the Loran pulse, and the CP
Data is exchanged with U17. A transfer signal 35 is sent from the CPU 17 to the signal synchronization circuit 13 to transfer the position of the synchronization pulse.

FIG. 2 is a timing chart showing the timing of main signals. The operation will be explained with reference to FIGS. 1 and 2.

The output from the receiver 12 includes a main station Loran pulse consisting of a total of nine pulses: eight Loran pulses lined up at equal intervals and one Loran pulse that appears at longer intervals than this interval. A group 41 and a slave Loran pulse group 42 consisting of eight equally spaced Loran pulses appear. When the eight pulses of the main station Loran pulse group 41 are expanded, each pulse is formed by a gradual increase and a gradual decrease in the amplitude of the main carrier 43 of 100Kllz, as shown in 31a. The signal synchronization circuit 13 generates a synchronization pulse 32 that is synchronized with the 0 cross point of the main carrier 43. The sampling pulse generation circuit 16 receives the synchronization pulse 32 at a time t.

The A/D conversion circuit 15 generates a sampling pulse group 34 consisting of a plurality of pulses at intervals of 1 microsecond starting from a previous time, and according to the timing of the sampling pulse group 34, the Loran pulse 31a is sequentially converted into a digital signal. will be converted into

The digitally converted Loran pulse is transferred to the CPII 1 via a buffer (not shown) due to transfer speed limitations.
7 and stored in the storage unit 18. The eight Loran pulses 31a stored in this way are stored in the CPU
17 and are averaged and reproduced into one Nororan pulse. At this time, since the sampling pulse group 34 and the synchronizing pulse 32 always have a constant positional relationship, the positional relationship with the synchronizing pulse 32 is calculated by performing calculations on the above-mentioned reproduced Loran pulse.

FIG. 3 is a timing chart showing the relationship between the synchronization pulse 32 and the regenerated Loran pulse. Since the reproduced Loran pulse 50 is an average of eight Loran pulses, the amorphous components of the noise cancel each other out. When the peak values 51 (a to d) are respectively a - d, the theoretical value is b / c = approximately 0.5, and a / b is 0.
．． c/d is sufficiently smaller than 5, and c/d is sufficiently larger than 0.5. The synchronization pulse 32 is synchronized with the 0 cross point of the Loran pulse, so if we take the ratio of the values of the two peaks 51 that come before the synchronization pulse 32, at the synchronization position 32a, a
/b, b/c in 32b.

32c is c/d, and the synchronization position is determined by calculating the ratio of the peak value 51. When the synchronizing pulse 32 has come before the 3-cycle position, a transfer signal 35 for moving the synchronizing pulse 32 backward is sent to the signal synchronizing circuit. 13, and sends the synchronization pulse 32 to the Loran pulse 31a.
Synchronize to the 3rd cycle position. When the synchronization to the 3-cycle position is completed, the main station Loran pulse group 41 and the slave station Loran pulse group 42 are generated from this synchronizing pulse 32 and the synchronizing pulse synchronized with the slave Loran pulse 42 in the same manner as above.
Measure the time difference between and select one hyperbola.

Note that the present invention is not limited to the above-described embodiment, and the interval between each pulse of the sampling pulse group 34 can be changed within a range that allows the positional relationship between the Loran pulse 31 and the synchronization pulse 32 to be calculated.

In addition, when performing averaging, it is not limited to 8 Loran pulses, but it is possible to wait for the next Loran pulse group and perform averaging using 16 Loran pulses, and the number can be sequentially increased depending on the superimposed noise. It is also possible to increase the number.

As a result, one Loran pulse is regenerated by aggregating and averaging multiple Loran pulses, and the 3-cycle position is detected based on this Loran pulse, so if noise is superimposed. Therefore, it becomes possible to provide a Loran C receiver that can obtain highly reliable measurement results.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention;
FIG. 2 is a timing chart showing the timing of the main signals, and FIG. 3 is a timing chart showing the relationship between the synchronization pulse and the regenerated Loran pulse. 13... Signal synchronization circuit, 15... A/D conversion circuit,
16...Sampling pulse generation circuit, 17...
CPU. Patent Applicant Furuno Electric Co., Ltd. Agent Patent Attorney Takaharu Ohnishi Figure 1

Claims (1)

[Claims] (1) A signal synchronization circuit that generates a synchronization pulse that is synchronized with the Loran pulse output from the receiver that receives the Loran C signal, an A/D conversion circuit that converts the Loran pulse into a digital signal, and this A/D A sampling pulse generation circuit sends a group of sampling pulses having a fixed time relationship with the synchronization pulse to the conversion circuit, and a waveform of the Loran pulse converted into a digital signal by the A/D conversion circuit is analyzed to detect the synchronization position. A Loran C receiver comprising: a CPU that sends a transfer signal to the signal synchronization circuit to transfer the synchronization pulse to a three-cycle position.