JPS62263666A - Resin sealed type semiconductor package - Google Patents
Resin sealed type semiconductor packageInfo
- Publication number
- JPS62263666A JPS62263666A JP10580886A JP10580886A JPS62263666A JP S62263666 A JPS62263666 A JP S62263666A JP 10580886 A JP10580886 A JP 10580886A JP 10580886 A JP10580886 A JP 10580886A JP S62263666 A JPS62263666 A JP S62263666A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- lead
- external lead
- resin
- contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 239000011347 resin Substances 0.000 title abstract description 6
- 229920005989 resin Polymers 0.000 title abstract description 6
- 238000005452 bending Methods 0.000 abstract 1
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高密度実装に適した樹脂封止型半導体パンケ
ージに関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a resin-sealed semiconductor package suitable for high-density packaging.
（従来の技術）
近年、電子機器の軽薄短小化に伴い、半導体素子の高密
度実装がますます重要となり、実装に際してスルーホー
ルが不要で、配線パターンが密にできる高密度面実装が
注目されている。また、半導体素子の高集積化、高機能
化という点から、半導体パッケージの小形化がますます
重要となってきている。(Conventional technology) In recent years, as electronic devices have become lighter, thinner, and shorter, high-density mounting of semiconductor devices has become increasingly important, and high-density surface mounting, which eliminates the need for through holes and allows for dense wiring patterns, is attracting attention. There is. Further, from the viewpoint of higher integration and higher functionality of semiconductor elements, miniaturization of semiconductor packages is becoming more and more important.
面実装用半導体パッケージとして、ＳＯ（ｓｍａｌｌＯ
ｕｔｌｉｎｅ）のようにリードピッチを小さくして、Ｄ
Ｉ Ｐ （Ｄｕａｌ Ｉｎ−１ｉｎｅ Ｐａｃｋａｇｅ
）より小形化したもの、ＳＯのように２方向リードでな
く４方向しこリードを出したＦ Ｐ Ｐ （Ｆｌａｔ
Ｐｌａｓｔｉｃ Ｐａｃｋａｇｅ）が盛んに採用されて
いる。これらの半導体パッケージは、低価格の点からす
べて樹脂封止型である。SO (smallO
utline), reduce the lead pitch and
I P (Dual In-1ine Package
) is smaller than the F P P (Flat
plastic packaging) is being widely adopted. These semiconductor packages are all resin-sealed type from the viewpoint of low cost.
（発明が解決しようとする問題点）
しかしながら、上記の面実装用半導体パッケージは、外
部リードがその側面から突出しており、半田接着法によ
ってプリント基板に実装するので。(Problems to be Solved by the Invention) However, in the surface-mount semiconductor package described above, the external leads protrude from the side surfaces and are mounted on the printed circuit board by solder bonding.
実装面積の中で外部リード部分の占める割合が大きく、
実装面積の縮小化を妨げているという問題があった。The external lead portion occupies a large proportion of the mounting area.
There was a problem in that it hindered the reduction of the mounting area.
また、面実装時に位置決めが難しく１時に小形化に伴っ
て位置決めの困難さが大幅に増大するという問題があっ
た。Further, there is a problem in that positioning is difficult during surface mounting, and the difficulty in positioning increases significantly with miniaturization.
本発明は上記の問題点を解決するもので、外部リード部
分の占める割合が小さく、従って面実装密度を向上する
ことができ、且つ、位置決めの容易な半導体パッケージ
を堤供するものである。The present invention solves the above-mentioned problems, and provides a semiconductor package in which the proportion occupied by the external lead portion is small, and therefore the surface mounting density can be improved, and the positioning is easy.
（問題点を解決するための手段）
上記の問題点を解決するために、本発明は、外部リード
を半導体パッケージの側面から突出したところで、側面
に接するように下方に曲げ、その先端を半導体パッケー
ジの底面より突出しないようにする。また、外部リード
の少なくとも１本以上を半導体パッケージの底面より突
出させるものである。(Means for Solving the Problems) In order to solve the above problems, the present invention provides that, at the point where the external lead protrudes from the side surface of the semiconductor package, the external lead is bent downward so as to be in contact with the side surface, and the tip of the external lead is bent downward so as to be in contact with the side surface of the semiconductor package. Do not protrude beyond the bottom of the Further, at least one of the external leads is made to protrude from the bottom surface of the semiconductor package.
（作 用）
上記の構成により、半導体パッケージの側面に接するよ
うに折り曲げられた外部リードは、実装面積に占める外
部リード部分の割合を低減する。(Function) With the above configuration, the external leads bent so as to be in contact with the side surfaces of the semiconductor package reduce the ratio of the external lead portion to the mounting area.
また、少なくとも１本以上の外部リードを半導体パッケ
ージの底面より突出させであるので、基板に上記の突出
した外部リードが挿入される凹み又はスルーホールを設
けて置くことによって、位に決めが容易となり、しかも
、その他の外部リードはすべて半導体パッケージの底面
より突出しないので、実装高さは半導体パッケージの高
さと同じとなる。Furthermore, since at least one external lead is made to protrude from the bottom surface of the semiconductor package, positioning can be easily determined by providing a recess or through hole in the board into which the protruding external lead is inserted. Moreover, since all other external leads do not protrude beyond the bottom surface of the semiconductor package, the mounting height is the same as the height of the semiconductor package.
（実施例）
本発明による実施例を第１図ないし第３図により説明す
る。(Example) An example according to the present invention will be described with reference to FIGS. 1 to 3.
第１図（ａ）および（ｂ）は、本発明による半導体パッ
ケージの第１の実施例を示す断面図および部分斜視図で
ある。第１図（ａ）において、半導体パッケージは、樹
脂１で封止された中に、半導体チップ２がワイヤ３で内
部リード４に接続され、上記の樹脂１から突出した外部
リード５が、突出したところで直角に半導体パッケージ
の下段側面６に接するように曲げられ、その先端が半導
体パッケージの底面７と同一面になるように形成されて
いる。半導体パッケージの上段側面８は、はぼ外部リー
ド５の厚さ分だけ段違いとなっている。FIGS. 1(a) and 1(b) are a sectional view and a partial perspective view showing a first embodiment of a semiconductor package according to the present invention. In FIG. 1(a), the semiconductor package is sealed with a resin 1, a semiconductor chip 2 is connected to an internal lead 4 by a wire 3, and an external lead 5 protrudes from the resin 1. By the way, it is bent at a right angle so as to contact the lower side surface 6 of the semiconductor package, and its tip is formed to be flush with the bottom surface 7 of the semiconductor package. The upper side surface 8 of the semiconductor package is stepped by an amount equal to the thickness of the external lead 5.
第１０図（ｂ）は、第１図（ａ）の部分斜視図で、第１
の実施例の半導体パッケージは、その側面が上下２段に
分かれ上段側面８と下段側面６に接して下方に曲げられ
ている外部リード５の側面とがほぼ同一平面をなしてい
る。FIG. 10(b) is a partial perspective view of FIG. 1(a).
In the semiconductor package of the embodiment, the side surface is divided into two upper and lower stages, and the side surface of the external lead 5, which is bent downward in contact with the upper side surface 8 and the lower side surface 6, is substantially on the same plane.
第２図（ａ）および（ｂ）は、本発明による半導体パッ
ケージの第２の実施例を示す断面図および部分斜視図で
ある。第２の実施例は第１の実施例の上段側面８が下段
側面６と同一平面となり、−面からなる側面９を形成し
ているものである。FIGS. 2(a) and 2(b) are a sectional view and a partial perspective view showing a second embodiment of a semiconductor package according to the present invention. In the second embodiment, the upper side surface 8 of the first embodiment is on the same plane as the lower side surface 6, forming a side surface 9 consisting of a - plane.
第３図は本発明による半導体パッケージの第３の実施例
を示す部分斜視図である。第３の実施例は、一番手前の
案内ピン用外部リード１０の先端を底面７より突出させ
案内ピンの役目を果させるもので、このような案内ピン
用外部リード１０を２箇所設けることによって１位置と
方向を決めることができる。FIG. 3 is a partial perspective view showing a third embodiment of the semiconductor package according to the present invention. In the third embodiment, the tip of the outer lead 10 for the guide pin located at the front side protrudes from the bottom surface 7 to play the role of the guide pin.By providing such an outer lead 10 for the guide pin at two locations, 1 position and direction can be determined.
上記のいずれの実施例も、案内ピン用外部り−ド１０を
除き、外部リード５の先端は半導体パッケージの底面７
と同一平面上にあるが、外部リード５の先端が底面の内
側になるように短くなっても、基板の配線に半田接続が
可能な限り問題がないことは勿論である。In all of the above embodiments, except for the guide pin external lead 10, the tip of the external lead 5 is connected to the bottom surface 7 of the semiconductor package.
However, even if the tips of the external leads 5 are shortened so that they are on the inside of the bottom surface, there is of course no problem as long as solder connection to the wiring on the board is possible.
（発明の効果）
以上説明したように、本発明によれば、実装面積に占め
る外部リード部分の割合を大幅に低減し、高密度実装が
可能となる。(Effects of the Invention) As described above, according to the present invention, the ratio of the external lead portion to the mounting area is significantly reduced, and high-density mounting is possible.
また、案内ピン用外部リードを設けであるので。In addition, an external lead for the guide pin is provided.
実装時の位置決めが極めて容易である。Positioning during mounting is extremely easy.
第１図（ａ）および（ｂ）は本発明による半導体パッケ
ージの第１の実施例を示す断面図および部分斜視図、第
２図（ａ）および（ｂ）は第２の実施例を示す断面図お
よび部分斜視図、第３図は第３の実施例の部分斜視図で
ある。
１・・・樹脂、 ２・・・半導体チップ、 ３・・・
ワイヤ、 ４・・・内部リード、 ５・・・外部り−
ト、 ６・・・下段側面、 ７・・・底面、 ８・・・
上段側面、 ９・・・側面、 １０・・・案内ピン用外
部リード。
特許出願人 松下電子工業株式会社
第１図
１ 用鮨
２− ＋＃−＾キプブグ
３ フ４Ｙ
４ ψ１ｅンリード
６・１動−・団 ａ −ｔ Ｗ剥め
第２図
第３図
ＩＢ）鮨
５ クト 仔？ ＝）−ド
ア 東面FIGS. 1(a) and (b) are a cross-sectional view and a partial perspective view showing a first embodiment of a semiconductor package according to the present invention, and FIGS. 2(a) and (b) are a cross-sectional view showing a second embodiment. FIG. 3 is a partial perspective view of the third embodiment. 1...Resin, 2...Semiconductor chip, 3...
Wire, 4...internal lead, 5...external lead-
6...lower side, 7...bottom, 8...
Upper row side surface, 9... Side surface, 10... External lead for guide pin. Patent applicant: Matsushita Electronics Co., Ltd. Fig. 1 Sushi 2- + # - ＾ Kipbug 3 Fu 4 Y 4 ψ1 en lead 6 1 movement - group a - t W peeling Fig. 2 Fig. 3 IB) Sushi 5 Kutko? =)-door east side
Claims (2)
ドが、上記の側面に接するように上記の半導体パッケー
ジの表面又は底面と直角に成形され、且つ、一部のもの
を除きその先端が上記の表面又は底面と同一面上又は同
一面より内側にあることを特徴とする樹脂封止型半導体
パッケージ。(1) The external lead taken out from the side surface of the semiconductor package is formed perpendicularly to the surface or bottom surface of the semiconductor package so as to be in contact with the side surface, and the tip of the external lead, except for some, is formed on the surface or bottom surface of the semiconductor package. A resin-sealed semiconductor package characterized by being on the same surface as the bottom surface or inside the same surface.
ケージの表面又は底面より突出していることを特徴とす
る特許請求の範囲第（１）項記載の樹脂封止型半導体パ
ッケージ。(2) The resin-sealed semiconductor package according to claim (1), wherein at least one external lead protrudes from the front or bottom surface of the semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10580886A JPS62263666A (en) | 1986-05-10 | 1986-05-10 | Resin sealed type semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10580886A JPS62263666A (en) | 1986-05-10 | 1986-05-10 | Resin sealed type semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62263666A true JPS62263666A (en) | 1987-11-16 |
Family
ID=14417404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10580886A Pending JPS62263666A (en) | 1986-05-10 | 1986-05-10 | Resin sealed type semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62263666A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4133598A1 (en) * | 1990-10-12 | 1992-04-16 | Atmel Corp | STRAPLESS, SURFACE MOUNTABLE IC CHIP |
| US5428248A (en) * | 1992-08-21 | 1995-06-27 | Goldstar Electron Co., Ltd. | Resin molded semiconductor package |
| US6100598A (en) * | 1997-03-06 | 2000-08-08 | Nippon Steel Semiconductor Corporation | Sealed semiconductor device with positional deviation between upper and lower molds |
-
1986
- 1986-05-10 JP JP10580886A patent/JPS62263666A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4133598A1 (en) * | 1990-10-12 | 1992-04-16 | Atmel Corp | STRAPLESS, SURFACE MOUNTABLE IC CHIP |
| DE4133598C2 (en) * | 1990-10-12 | 2000-06-21 | Atmel Corp | Arrangement with a chip surface-mounted on a substrate with an integrated circuit and method for its production |
| US5428248A (en) * | 1992-08-21 | 1995-06-27 | Goldstar Electron Co., Ltd. | Resin molded semiconductor package |
| US6100598A (en) * | 1997-03-06 | 2000-08-08 | Nippon Steel Semiconductor Corporation | Sealed semiconductor device with positional deviation between upper and lower molds |
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