JPS623498A - Semiconductor memory device with on-chip ECC circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to error detection and correction (Error Check a
The present invention relates to a semiconductor memory device having a nd co-rectjon (hereinafter referred to as rECCl) function.

[Conventional technology]

In recent years, as semiconductor memory devices have become more highly integrated, malfunction of memory cells due to incidence of alpha particles has become a problem.

As a countermeasure to this problem, the ECC function is provided on the same semiconductor substrate (hereinafter referred to as "on-chip 7" ECCj). FIG. 2 shows an example of a block diagram of a conventional on-chip ECC circuit using a Hamming code as an error correction code.

In FIG. 2, 1 is a terminal for inputting input data, 2 is a write check bit generation circuit, 3 is a data pin-memory cell array, 4 is a check bit memory cell array, 5 is a read check and check bit generation circuit, and 6 is a write check bit generation circuit. A syndrome generation circuit, 7 a syndrome decoder, 8 a data correction circuit, 9 a terminal for outputting output data, and 10a.

10b is a normal Y decoder, lla and llb are sense amplifiers, 12 is an X decoder, and SL and S2 are switches for switching between writing and reading.

The memory cell array consists of a cell array 3 of N rows and N columns of data bits and a cell array 4 of 7 check bits of N rows and M columns (the value of M is determined by how many bits are used as the unit of ECC). The decoder 12 determines one of the N
When a book word line is selected, it is connected to it (N+M)
The information of each memory cell is transmitted to the sense amplifiers lla and llb via the bit line, and is sensed and amplified. After that, a bit line is selected by Y decoders 10a and 10b,
Read information of desired memory cell. The ECC function is generally implemented as follows.

■When writing data, the check bit (
data bits and check bits are respectively written into the memory cell array 3.4.

The circuit that generates the check bit in this case is the write check bit generation circuit 2 shown in FIG. This (n+
m) A block of bits (hereinafter referred to as rECC code) is the unit of ECC, and error detection and correction is performed using this ECC.
This is done for each code word.

■When reading data, the aforementioned n data bits and m check bits are read simultaneously, all new check bits (hereinafter referred to as "read check bits") are generated from the n data bits, and this and the check bit memory cell array 4 Exclusive OR bit by bit with the check bit successively generated from . This result is all “0”
” (corresponding to the word check bit and check bit matching), then it is determined that there is no error, and otherwise it is determined that there is an error. The above logical sum is called a syndrome. A syndrome is a data string consisting of m bits. These processes are performed by read check bit generation circuit 5 and syndrome generation circuit 6 shown in FIG.

(2) The above syndrome includes position information of the error bit, and by decoding this information, it can be determined which bit among the n data bits is an error.

According to this, an error bit (one bit or a plurality of bits) of the n data bits and m check bits is corrected (inverted) and at the same time, n bits of information are output.

The syndrome decoder 7 and data correction circuit 8 shown in FIG. 2 perform this.

ECC is performed as described above. In FIG. 2, write check bit generation circuit 2. The read check bit generation circuit 5 is a circuit that generates check bits from n-bit data bits according to the configuration of an error correction/detection code, and the logical operations are the same for both circuits. Further, as described above, the syndrome generation circuit 6 is a circuit that performs a bit-by-bit exclusive OR of the check bits and nodes successively generated from the memory cell array 4 and the read check bits newly generated from the data bits. The syndrome decoder 7 is a decoder that converts the m-pin syndrome into a code (n+m bits) that specifies error bits among n-bit data bits, 7 bits, and m-bit check bits. An output is obtained in which only the bit position is "1" and the others are rOJ. The data correction circuit 8 is a part that performs a bit-by-bit exclusive OR of the data bits and check bits to be corrected and the output of the syndrome decoder 7, thereby inverting the data of only the error bits. The error-corrected code (n + m bits) is written again to a predetermined position in the memory cell array 3.4. Further, the corrected n-bit output is outputted to the outside via the data correction circuit 8.

[Problem to be Solved by the Invention 3] As explained above, in the conventional configuration in which the ECC circuit is on-chip, the information read from the memory cell array is read out to the outside via the data correction circuit. The drawback was that it was time consuming.

The present invention has been made in view of these points, and its purpose is to prevent delays in read speed by independently writing data from the outside and reading data to the outside. An object of the present invention is to provide a semiconductor memory device with an on-chip ECC circuit.

[Means for solving problems]

In order to solve these problems, the present invention has developed a conventional A decoder and a sense amplifier for reading and rewriting data bit data and check bit data for error detection and correction are provided.

[Effect]

In the present invention, the ECC circuit is provided separately from a circuit that performs normal reading/writing, and in particular, redundant circuits are omitted from the reading signal path, so that reading can be performed at high speed.

〔Example〕

An embodiment of a semiconductor memory device with an on-chip ECC circuit according to the present invention is shown in FIG. In FIG. 1, 10 is a normal Y decoder, and S3 is a switch for switching between writing and reading. In FIG. 1, the same or equivalent parts as in FIG. 2 are given the same reference numerals. In this embodiment, data writing and reading are performed by selection using an X decoder and a Y decoder, as in the case without an ECC circuit. The operation will be explained below in order.

First, the write operation will be explained. In this behavior,
The contact of switch S3 is connected to the write side (W).

(a-1): First, by the X decoder 12? ) Select one word line out of N.

(a-2): Next, select n decoders from the Y decoders 10 and write the n-bit input data input to the terminal 1 into the data biwat memory cell array 3.

At this time, (N-n) bit data and M-bit check bit data connected to the same word line are detected and amplified by sense amplifiers lla and llb, and together with the newly written n bits, (N+M ) sense amplifiers lla and llb have fixed states.

(a-3): N-bit information of N sense amplifiers lla (here, all N bits are used to simplify the explanation, but by decoding the sense amplifier output in some way, the bits can be It is possible to reduce the number.) A is manually input to the write check bit generation circuit 2, a write check hit of M pino h is newly generated, and the sense amplifier 1 is input to the check bit memory cell array 4.
Write via 1b.

Next, the read operation will be explained. In this operation, the contact of switch S3 is connected to the read side (R).

(b-1): First, as with writing, one word line is selected from N by the X decoder 12, and (N0M
) bit data is detected and amplified by sense amplifiers lla and 11b.

(b-2): Y decoder 10 independently of the E CC system
Among them, n decoders are selected and n-bit information is outputted from the terminal 9 as output data. At this time, ECC
The circuit performs the following operations in parallel.

(b-3): Confirmed N-bit sense amplifier ll
Input a output a to the read check bit generation circuit 5,
The check bit b of the M bits that has been generated and read out is input to the syndrome generation circuit 6 to obtain the syndrome d.

(b-4): If there is an error in the data hit data or check bit data (syndrome d)
0), the syndrome decoder 7 and data correction circuit 8 rewrite the data bits and check pinpoints in the memory cell arrays 3 and 4 through the sense amplifiers lla and llb.

In the above, we have explained that ECC is not applied during write operation, but if the same ECC operation as during read is performed before selecting the Y decoder 10, ECC can be applied during write as well.
It is possible to apply CC.

〔Effect of the invention〕

As explained above, the present invention includes a normal Y-decoder for writing data from the outside and reading data to the outside independently without passing through each error detection/correction function circuit, and an error detection/correction function. By providing a sense block for reading and rewriting data bit data and check bit data for correction, read operations can be performed independently of ECC operations, making it possible to use semiconductor memory that is an on-chip version of the conventional ECC circuit. This has the effect of eliminating the read speed delay that was a problem with the device.

[Brief Description of the Drawings] Fig. 1 is a system diagram showing an embodiment of a semiconductor memory device with an on-chip ECC circuit according to the present invention, and Fig. 2 is a system diagram showing a conventional semiconductor storage device with an on-chip ECC circuit. It is. 1.9... terminal, 2... write check bit generation circuit, 3... data bit memory cell array,
4...Check bit memory/recell array, 5...
... Read check bit generation circuit, 6 ... Syndrome generation circuit, 7 ... Syndrome decoder, 8
...Data correction circuit, 10...Y decoder, l
la, 11b...Sense amplifier, 12...X decoder, S3...Switch.

Claims (3)

[Claims] (1) On-chip ECC equipped with a write check bit generation circuit, a read check bit generation circuit, and a syndrome generation circuit for error detection and correction functions on the same board
A semiconductor memory device with a circuit includes a normal Y decoder for writing data from the outside and reading data to the outside independently without passing through each circuit for the error detection and correction functions, and Equipped with a sense amplifier for reading and rewriting data bit data and check bit data for correction, and error detection and correction.
An on-chip EC characterized in that the determined sense amplifier output is extracted without going through the normal Y decoder.
Semiconductor storage device with C circuit. (2) When writing data from outside, the sense amplifier performs ECC operation on the already stored memory cell information using the sense amplifier output before selecting the Y decoder, and performs error detection and error detection. 2. The semiconductor memory device with an on-chip ECC circuit according to claim 1, wherein new information is written into the memory cell array after the correction. (3) When writing data from the outside, the sense amplifier inputs the sense amplifier output, determined by the newly written information and the information already stored in the memory cell array, into the write check bit generation circuit. 2. A semiconductor memory device with an on-chip ECC circuit according to claim 1, wherein a write check bit written in a check bit is written into a check bit memory cell array.