JPS6269562A - Field effect transistor device and method for manufacturing the same - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a structure of a semiconductor device using a field effect transistor and a method of manufacturing the same.

[Conventional technology]

FIG. 3 is a cross-sectional structural diagram of a conventional field effect transistor device. In the figure, 1 is a silicon substrate, 2 is a thin insulating film formed on the surface of the silicon substrate 1, 3 is a gate electrode formed on the insulating film 2, and 4.5 is using the gate electrode 3 as a mask. The source and drain are formed by diffusion.

Next, the operation will be explained.

By applying a positive voltage to the gate electrode 3, an inversion layer is formed on the substrate surface under the gate electrode, and the source 4 and drain 5 are electrically connected.

[Problem that the invention seeks to solve]

Conventional field effect transistor devices are constructed as described below, and as the degree of integration of transistors increases and field effect transistors become smaller, the following problems arise.

(1) The threshold voltage decreases as the channel length decreases. Furthermore, the withstand voltage between the source and drain decreases, making punch-through more likely to occur (short channel effect).

(2) As the electric field near the drain increases, a phenomenon occurs in which some of the electrons generated by collision ionization of high-energy channel electrons enter the gate electrode. These electrons are trapped in the gate oxide film and cause problems such as fluctuations in threshold voltage (hot electron effect).

This hot electron effect can be reduced by relaxing the electric field near the drain, and a double-diffused drain has been proposed as one method.

As shown in FIG. 4, this is a method in which a lightly doped region (N-) is provided near the gate of a highly doped source/drain diffusion layer (N+). However, this method has the disadvantage of reducing the channel length and worsening the short channel effect.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a miniature field effect transistor device and a method for manufacturing the same, which reduce both the short channel effect and the hot electron effect. do.

[Means for solving problems]

A field effect transistor device and a method for manufacturing the same according to the present invention include forming a fine groove in a semiconductor substrate, forming a gate insulating film on the inner surface of the groove, and forming a gate electrode in the groove via the gate insulating film. Then, using the gate electrode as a mask, a diffusion layer having a gentle concentration gradient toward the inside of the substrate is formed.

[Effect]

In this invention, a gate electrode is formed in a groove of a semiconductor substrate, and source and drain diffusion layers having a concentration gradient are provided in the semiconductor substrate on both sides of the electrode, so that the following effects can be obtained.

+1) The substrate surface facing the sidewalls and bottom of the fine groove is used as a channel, so that even if the gate electrode width is shortened, the channel length can be made long;
Short channel effects can be suppressed.

(2) The direction in which channel electrons flow near the drain is perpendicular to the substrate surface, so the electric field near the drain is relaxed by the diffusion layer having a gentle concentration gradient toward the inside of the substrate, and the hot electron effect can be reduced. At this time, since the channel length is long as described above, the short channel effect will not be worsened.

(3) By forming the gate electrode in the groove of the semiconductor substrate, a field effect transistor device with excellent flatness can be realized.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view of a field effect transistor device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate in which a fine groove (trench) 6 is formed, and 2 is a semiconductor substrate in which a fine groove (trench) 6 is formed.
A gate insulating film is formed on the inner wall of the groove 6 and the surface of the semiconductor substrate 1, 3 is a gate electrode formed in the groove 6 via the gate insulating film 2, and 4.5 is a concentration gradient on the outer substrate portion of the groove 6. The source and drain diffusion layers are formed to have a source and drain diffusion layer.

As a feature of the present invention, the field effect transistor device shown in FIG. The channel length can be made larger than the electrode width.

Furthermore, since the diffusion layer has a gentle concentration gradient toward the inside of the substrate, the electric field near the drain 5 is relaxed and the hot electron effect is reduced.

In this example, variable energy ion implantation technology is used as a manufacturing method for the diffusion layer having the gentle concentration gradient. By changing the implantation depth and controlling the implantation amount at each depth, a diffusion layer having an arbitrary concentration gradient can be formed.

Next, the manufacturing process of the field effect transistor device of this example will be explained.

A trench 6 is formed in the semiconductor substrate 1 (FIG. 2(a)),
A gate insulating film 2 is formed on the inner wall of the trench 6 and the surface of the semiconductor substrate 1 (FIG. 2(b)). Next, the trench 6
A gate electrode 3 is formed inside the substrate (Fig. 2 tel), and a diffusion layer is formed so as to have a gentle concentration gradient toward the inside of the substrate by the variable energy ion implantation technique using the gate electrode 3 as a mask. (dl), manufacturing a field effect transistor device;

Since the device of this embodiment has the above-described configuration, by applying a positive voltage to the gate electrode 3, an inversion layer is formed on the substrate surface facing the sidewalls and bottom of the gate electrode 3, and the source The drain can be made conductive. Since the channel length at this time is longer than the gate electrode width, the short channel effect can be reduced. Furthermore, since the diffusion layer has a concentration gradient, it is possible to alleviate the electric rise near the drain and reduce the hot electron effect.

In the above embodiment, the energy variable ion implantation technique was used to form the diffusion layer with a gentle concentration gradient, but a double diffusion layer as shown in FIG. 5 may also be formed. Similar effects can be expected.

Further, in the above embodiment, the gate electrode is completely buried in the trench, but a structure in which a part of the gate electrode is exposed outside the trench as shown in FIG. 6 may be used, and the same effect can be expected.

〔Effect of the invention〕

As described above, according to the field effect transistor device and the manufacturing method thereof according to the present invention, the gate electrode is formed in the fine groove provided in the semiconductor substrate through the gate insulating film, so that the width of the gate electrode can be reduced. Even with miniaturization, the channel length can be made long, and the diffusion layer has a gentle concentration gradient toward the inside of the substrate, so the electric field near the drain can be relaxed, without worsening the short channel effect. This has the effect of reducing the hot electron effect.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing a field effect transistor device according to an embodiment of the present invention, FIGS. The figure is a cross-sectional view showing a conventional field effect transistor device, FIG. 4 is a cross-sectional view of a field effect transistor device equipped with a double diffusion layer conventionally proposed for reducing the pot electron effect, and FIG. FIG. 6 shows a cross-sectional view of a field effect transistor device according to another embodiment of the invention. In the figure, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode, 4 is a source, 5 is a drain, and 6 is a trench. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (4)

[Claims] (1) A semiconductor substrate having a groove on its main surface, a gate electrode formed inside the groove via a gate insulating film, and a gate electrode formed on the semiconductor substrate on both sides of the groove and having a concentration gradient downward. A field effect transistor device comprising a source and a drain diffusion layer. (2) a first step of forming a groove on the main surface of the semiconductor substrate; a second step of forming a gate insulating film on the inner surface of the groove; and a third step of forming a gate electrode inside the groove; A fourth step of performing diffusion into the semiconductor substrate on both sides of the groove so as to have a gentle concentration gradient downward using the gate electrode as a mask to form source and drain diffusion layers. A method of manufacturing a field effect transistor device. (3) The method for manufacturing a field effect transistor device according to claim 2, wherein the diffusion in the fourth step is performed by controlling an acceleration voltage and an ion current during ion implantation. (4) The method for manufacturing a field effect transistor device according to claim 2, wherein the diffusion in the fourth step is performed by double diffusion.