JPS6276772A - Manufacturing method of field effect transistor - Google Patents

Abstract

PURPOSE:To increase the diameter of crystal grain in a solid phase growth and to shorten the growing time by implanting inert ions to a channel region interposed between a source region and a drain region, then solid-phase growing at predetermined temperature, forming a gate electrodes, and then implanting an impurity to the source region and the drain region, and activating at predetermined temperature. CONSTITUTION:The main surface of a low melting point glass substrate 21 is coated with a polycrystalline Si layer (or a-Si:H)22, insularly formed, and removed except a predetermined region, Si<+> ions 26 are selectively implanted through a mask to the region which includes the channel region 23 of the layer 22 to convert the region to an amorphous region. Then, the region which includes the region 23 is solid-phase grown by annealing at 650 deg.C or lower. A polycrystalline Si gate electrode 27 is formed through a gate insulating film 26 on the region 23, n-type impurity ions (P<+>)28 are implanted to the electrode 27, source and drain regions 24, 25 to form an amorphous region to be activated at 650 deg.C or lower. After an interlayer insulating layer 9 is formed, source and drain electrodes 10, 11 are formed to obtain an FET30.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing field effect transistors, in particular thin film 1-transistors.

[Summary of the invention]

In the method for manufacturing a thin film transistor, the present invention involves implanting inert ions into the channel region of an amorphous or polycrystalline semiconductor layer, followed by heat treatment to achieve solid phase growth, and then implanting impurities into the source and drain regions at the gate electrode and self-alignment line. Each time the impurity is implanted and activated by heat treatment, the mobility μ is improved and the time for solid phase growth and impurity activation is shortened.

(Prior Art) In general, thin film transistors are made by depositing a semiconductor thin film such as silicon on an insulating substrate such as quartz glass, and forming a channel region, a source region, and a drain region on this semiconductor thin film to form a field effect transistor (FET). ).As such a thin film transistor, an ultra-thin film transistor has been proposed in which the thickness of the semiconductor thin film in the channel region is reduced by 100 to 800 times to improve characteristics (Japanese Unexamined Patent Publication No. 1989-1999). -136262).

In addition, although quartz glass with a high melting point is generally used as a substrate for thin (thin) simulated transistors, it is desirable to use inexpensive low-melting glass (e.g., alkali-free glass) for the substrate due to its commercial price. There is. When such relatively low melting point glass (softening point of 650° C. or lower) is used for the substrate, a low-temperature process is required in which the temperature during the manufacturing process of the thin film transistor is kept at 650° C. or lower.

FIG. 1 shows an example of a conventional thin film transistor manufacturing method.

. First, as shown in FIG. 2A, for example, an ``S+ simulated silicon layer'' of polycrystalline silicon (
2), the thin film silicon layer (2) is formed into island regions by etching away the rest while leaving a predetermined region), and then silicon ions St" are applied to the thin film silicon layer (2).
(Ion implantation of 31 (dose amount is, for example, 1.5X)
1015/1ffl) becomes amorphous. Note that either the island region formation or the St+ ion implantation may be performed first.

Next, heat treatment is performed at 600° C. for 15 hours to cause solid phase growth (see FIG. 2B).

Next, as shown in FIG. 2C, a gate insulating film (4) made of, for example, 5i02 or the like and a gate electrode (5) of polycrystalline silicon are deposited on the thin silicon layer (2).

Next, using the gate electrode (5) as a mask, an n-type impurity such as phosphorus ions (P'') (81) is implanted into the source region (6) and drain region (7) in the case of an n-channel FET. Phosphorus ions are also implanted into the gate electrode (5), resulting in low resistance.

Next, heat treatment is performed at 600°C for 7 to 8 hours to activate the source region (6) and drain region (7) (second
(see diagram).

After that, 5i02 by CVD (chemical vapor deposition) method.
After forming the glabellar insulation N (9), a contact window hole is formed, a source electrode (1o) and a drain electrode (11) made of Aβ are formed, and the 'f#BY transistor (12) is formed.
).

[Problem that the invention seeks to solve]

In the conventional manufacturing method described above, the larger the dose of silicon ions (St'') in the step shown in FIG. 2, the larger the crystal grain growth in the subsequent heat treatment, and the higher the mobility μ.

However, when the dose is increased, there is a problem that it takes a long time to grow the crystal grains. For example, if the Si+ dose is 2 x IQ'' cm -', the growth time will be 30 hours or more.

In view of these points, the present invention provides a method for manufacturing a field effect transistor that can increase the crystal grain size in solid phase growth and shorten the growth time.

[Means for solving problems]

The present invention relates to a method for manufacturing a field effect transistor in an amorphous or polycrystalline semiconductor 1m (22) formed on a substrate (21) whose surface is an insulator, the semiconductor Ji (
22) source region (24) and drain region (25)
After selectively injecting inert ions (26) into the channel region (23) centered at 1, heat treatment is performed at 650° C. or higher to achieve solid phase growth.

Next, the gate insulating film (26) is placed on the channel region (23).
) After forming a gate electrode (27) through a gate electrode (27), impurities (28) of the first conductivity type are implanted into the source region (24) and drain region (25), and activated by heat treatment at 650° C. or higher. After this, as usual, insulate between the eyebrows r@(9)
After forming a contact window hole in the j-j insulating layer (9), a source electrode (lO) and a drain electrode (step 1) made of Aβ, for example, are formed, and the desired field effect transistor is immediately connected. A thin film transistor (30) is obtained.

As the substrate (21), a low melting point glass that can be used in a low temperature process (for example, alkali-free glass), quartz glass, a substrate with an insulating film such as 5i02 coated on a semiconductor substrate, etc. can be used. As the inert ion (26), for example, silicon ion Si+ can be used when the semiconductor Jm (22) is silicon.

[Effect]

By implanting inert ions (26) into the channel region (23) of the semiconductor layer (22), the channel region (
23) is selectively amorphized. Next, a channel region (23) is grown in a solid phase by low-temperature heat treatment at 650° C. or higher, but this solid phase growth occurs in a source region (23) where ions are not implanted before random nucleation occurs in the channel region.
Since the crystal grains in the source and drain regions (24) and (25) are used as seeds to grow from both the source and drain regions, the solid phase growth time is shortened.

Therefore, even if the crystal grain size is increased by increasing the dose of inert ions (26), the solid phase growth time will be shortened.

Furthermore, the activation of the source region (24) and drain region (25) after implanting impurity ions is also performed at a low temperature (650°C or higher).
process). In this case, solid phase growth and impurity activation are performed under almost the same conditions (temperature, time).

〔Example〕

Hereinafter, an example of the method for manufacturing a field effect transistor of the present invention will be explained with reference to FIG.

First of all! @1 As shown in Figure A, a film thickness of 80 mm is applied to the main surface of a low melting point glass substrate (21) such as alkali-free glass.
Deposit a thin ultra-thin CVD polycrystalline silicon layer (or hydrogenated amorphous silicon a-Si:H) (22). Then, this polycrystalline silicon layer (22) is made into an island region, that is, a predetermined region is left and the rest is etched away. Next, silicon ions (Si'') (26) are selectively implanted into the region including the channel region (23) of the polycrystalline silicon layer (22) through a mask to form the region including the channel region (13). to amorphous.

Therefore, at this time, ions are not implanted into the source region (24) and drain region (25). -Silicon ion (2
The dose amount of 6) is, for example, about 2×1015c+a-2.

Next, as shown in Figure B of 'N41, annealing treatment is performed at 600° C. to grow a region including the amorphous channel region (23) in a solid phase. At this time, before random nucleation occurs, solid phase growth occurs from both sides of the source and drain regions using the crystal grains of the source region (24) and drain region (25) as ridges. Therefore, the solid phase growth time at this time is short, about 10 hours.

Next, as shown in the IC in Figure 1, the channel area (23)
A gate electrode (17) made of polycrystalline silicon is formed on the top through a gate insulating film (26) made of SiO2 or the like, and this gate electrode (27) and self-alignment line are used to form a source region (24) and a drain region (25). For example, in the case of an n-channel ET, n-type impurity ions (for example, phosphorus ions P">(2B) are ion-implanted. At this time, n-type impurities are also implanted into the polycrystalline silicon of the gate electrode (27), resulting in low A resistive silicon gate electrode (27) is formed.The source region (24) and drain region (25) are made amorphous by this ion implantation of n-type impurities.

Next, as shown in the first diagram, an annealing treatment is performed at 600° C. for 7 to 8 hours to grow and activate the source region (24) and drain region (25) in solid phase.

In this case, since the good channel region (23) has already been crystallized, the source region (24) and drain region (25) are crystallized using this as a seed.

After that, as shown in Fig. 1E, for example, PSG is applied to the entire surface.
After depositing an interlayer insulating layer (9) made of (phosphosilicate glass) or CVD5i (h, etc.), window holes for source and drain contacts are formed, and then source electrodes (lO) and drain electrodes (of Al, for example) are formed. 11) to obtain the desired field effect transistor, that is, a J[lQ) transistor (30).

According to this manufacturing method, the time required for solid-phase growth of the channel region in the annealing process shown in FIG. Significantly shortened.Moreover, Si
Since the dose of + can be increased, the crystal grain formation area in the channel region becomes larger, and the mobility μ improves.

In the solid phase growth of the channel region (23) (Fig. 1B
step), source region (24) and train region (24)
If crystal grain growth occurs from both sides of 5) and, for example, a grain boundary (29) is created under the gate, the mobility μ decreases somewhat, but this grain boundary (29) is perpendicular to the chamfer length direction. leakage current is hardly a problem.

In addition, although I talked about n-channel FET in Kamishio, P
The present invention can also be applied to the manufacturing method of channel FIE'.

〔Effect of the invention〕

According to the present invention, a channel region of an amorphous or polycrystalline semiconductor layer is selectively made amorphous by implantation of inert ions and then subjected to low-temperature heat treatment. By solid-phase growth of the region,
Even if the dose of inert ions is increased, the solid phase growth time of the channel region can be shortened. Therefore, by increasing the dose, the crystal grain size can be increased, and the mobility μ can be increased. , its solid phase growth time can significantly reduce asbestos;
Manufacturing of thin film transistors using this structure can be facilitated.

[Brief explanation of drawings]

1A to 1E are process diagrams for manufacturing a field effect transistor of the present invention, and FIGS. 2A to 2E are process diagrams for manufacturing a conventional field effect transistor. (21) is a base, (22) is an amorphous or polycrystalline semiconductor layer, (23) is a channel region, (24) is a source region,
(25) is the drain region, (26) is the gate insulating film, (
27) is a gate electrode.

Claims (1)

[Claims] In a method for manufacturing a field effect transistor in an amorphous or polycrystalline semiconductor layer formed on a substrate whose surface is an insulator, inert ions are added to a channel region sandwiched between a source region and a drain region. After implanting impurities, heat treatment is performed at 650 degrees Celsius or less to cause solid phase growth, and after forming the gate electrode, impurities are implanted into the source and drain regions, and heat treatment is performed at 650 degrees Celsius or less to activate. A method for manufacturing a field effect transistor.