JPS63177565A - Semiconductor integrated circuit device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO3 type semiconductor integrated circuit device and a manufacturing method thereof.

[Conventional technology]

Conventionally, silicon (Si) has been used as a three-dimensional device (three-dimensional device) to increase the degree of integration of integrated circuit devices.
There is an SOI technique in which an insulating film is formed on a substrate and a Si layer is formed on top of the insulating film. In addition, in order to reduce the area of element isolation regions and capacitors, we have developed a technology to dig trenches in the Si substrate and form isolation regions and capacitors there, as well as capacitors and M
OS) There is a technology to form transistors all at once.

[Problem that the invention seeks to solve]

Among the conventional techniques mentioned above, the SOI technique has not yet been able to form a high-quality, uniform Si single crystal on an insulating film, and it takes time to solve this problem. Additionally, the trenched transistor with a capacitor has the disadvantage that the source power source is not embedded.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit and a method for manufacturing the same, which eliminates such drawbacks, achieves higher integration and speed of the device, and shortens the manufacturing process.

[Means for Solving the Problems] The structure of the semiconductor integrated circuit device of the first invention is such that on the silicon substrate side that is in contact with the groove perpendicularly drilled inward from the surface of the silicon substrate, A drain impurity layer, a back gate, and a source impurity layer are provided, a source power supply impurity layer is provided on the bottom surface of the trench, a gate insulating film is provided on the surface of the back gate on the side surface of the trench, and a gate insulating film is provided on the surface of the back gate on the side surface of the trench. has a vertical structure in which a source power supply electrode, an insulating film, and a gate electrode metal are provided sequentially from below.
It is characterized by having an OS transistor.

The structure of the method for manufacturing a semiconductor integrated circuit device according to the second invention is as follows:
A first insulating film is formed on the surface of a silicon substrate, a predetermined region of the first insulating film is removed by vertical etching, and then a drain region is formed by doping impurities for a drain into the region. A vertical groove is formed in the vertical groove, the silicon substrate on the side surface of the vertical groove is used as a gate region, and the lower part of the vertical groove is doped with impurities for source and source power supply to form a source region. Vertical MOS transistors are manufactured by forming a high melting point metal film on the surface, causing a silicidation reaction through heat treatment, and then removing the unreacted high melting point metal film to form a self-aligned source electrode. It is characterized by

The structure of the method for manufacturing a semiconductor integrated circuit device according to the third invention is as follows:
After fabricating the vertical structure MOS transistor of the first conductivity type, the wafer surface is covered with a masking agent for vertical etching to a predetermined thickness, and a multi-order process is performed to fabricate the vertical structure MOS transistor of the second conductivity type. The method is characterized in that the film of the masking agent is used as a mask for vertical etching.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to (j) are sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a plan view of FIG. 1(j).

First, as shown in FIG. 1(a), a thin thermally oxidized 5i02 film 2 is formed on the surface of a P-type Si substrate 1 with a specific resistance of several ΩC, and As is ion-implanted into a desired region of this 5i02 film 2. After forming a highly concentrated N-type impurity layer 3 to a depth of about 3,000 layers and curing, a C layer with a thickness of about 1 μm is formed on the 5i02 film 2.
A VDSio2 film 4 is formed. This N-type impurity layer 3 is
This will become the drain lead-out portion of an N-channel MOS transistor in the future.

Next, as shown in FIG. 1(b), using a normal photolithography process, a photoresist is used as a mask.
By vertically etching the film 2, the CVD 5i02 film 4 and the thermal 5i02 film 2 are removed in a square shape of 1.2 μm on each side. Next, by doping with ^S, a high concentration of N to a depth of 3000 people was created.
A type impurity layer 6 is formed.

The impurity layer 6, which will become the drain of the N-channel MO transistor 8) in the future, is connected to the already formed impurity layer 2 to form a continuous high-concentration N-type impurity layer.

Next, as shown in FIG. 1(c), 5102M7 with a thickness of 2000 layers is formed on the exposed Si surface of the groove 5 by thermal oxidation, and after further depositing 3000 layers of CVD 5iO□ film, 5i02 vertical The sidewall 8 is formed by etching, and the bottom surface 5i027 is removed. Next, Figure 1 (
d), the Si substrate 1 is vertically etched to a depth of 1.8 μm.

Next, as shown in FIG. 1(e), a 5i02 film 9 with a thickness of 1000 is formed on the exposed Si surface by thermal oxidation, and then the 5i02 film 9 on the bottom surface is etched by 5i02 vertical etching.
Film 9 is removed, followed by an additional Si vertical etch.
Dig a trench 8 μm deep. The Si substrate 1 on the side surface of this groove corresponds to a back gate serving as a gate region.

Next, as shown in FIG. 1(f), As is diffused into the exposed portion of Si at the bottom of the trench to a depth of 300 mm, which will become the source region.
A high concentration N-type layer 10 of 0 is formed, and then an even higher concentration of B is doped by ion implantation and annealed to form a layer 10 with a depth of 5.
000 high concentration P-type layer 11 is formed, and these N-type layers 10. P-type layer 11 constitutes a power source.

Next, as shown in FIG. 1(g), the W layer 12 is formed to a thickness of 200
After forming by CVD, annealing is performed to form Si at the bottom of the groove.
The part in contact with the WSiz layer 13 is changed to the WSiz layer 13. Furthermore, as shown in FIG. 1(h), after removing the unreacted W layer 12, the 5i02 film 9 on the side surfaces of the trench is removed by isotropic etching. This isotropic etching also removes most of the sidewall 5i028.

Next, as shown in FIG. 1(i), a 5i02 film 14 with a thickness of 200 mm is formed on the side surfaces of the trench by thermal oxidation. At this time,
The surface of the WSi2 film 13 is also oxidized, and an oxide film 15 is formed. Next, as shown in FIG. 1(j), 5,000 layers of phosphorus-doped polysilicon 16 are deposited, the left half of the figure is masked with a resist, and vertical etching of the polysilicon is performed. The BPSG film 17 is completely removed, and a metal wiring 18 is formed on the surface of the drain lead-out portion 3 with a window for wiring contact formed therein.

In FIG. 1(j), the N-type impurity N6. is the drain,
Similarly, 10 is a source, the SiO□ film 14 is a gate insulating film, the phosphorus-doped polysilicon 16 is a gate electrode and a gate lead line, and one vertically structured N-channel MO 9).
It constitutes a transistor. The source 10 is held at the same potential as the P-type Si substrate 1 through the WSi2 layer 13 and the P-type impurity layer 11. FIG. 2 is a plan view of the structure of FIG. 1 (j>).

Although the above description has been made regarding an N-channel transistor, it is clear that the same thing can be applied to a P-channel transistor as well.

3(a) to 3(f) are cross-sectional views showing the second embodiment of the present invention in the order of steps, and FIG. 4 is a plan view of FIG. 3(f), which is an example applied to a CMO3 integrated circuit. It shows.

First, in FIG. 3(a), a 5000-thick 5i02 film 12 is formed on the surface of a P-type Si substrate 21 by thermal oxidation, and then a separation zone groove having a width of 1.2 μm and a depth of 7 μm is formed. The inside of the groove is formed with a thickness of 1,000 mm by thermal oxidation.
After forming the i02 film 23, the trench is filled with a CVD5iO□ film 24. Next, as shown in FIG. 3(b), an N-type well 25 with a depth of 6 μm is formed on the right side of the isolation zone.

Next, as shown in FIG. 3(c), after forming an N-type drain extraction part 26 with a depth of 3000mm and a P-type drain extraction part 27 with a depth of 5000mm, the 5i02 film on the surface of the Si substrate is completely removed. 5i02 film 2 of 1000 people by thermal oxidation
8 and a 1.2 μm CVD5iOz film 29 is formed.

Next, as shown in FIG. 3(d), after fabricating the N-channel transistor 30, a CV D S
iO□ film 31 total 31. Note that the method for manufacturing the transistor 30 is the same as that of the first embodiment.

The same is fine. However, the polysilicon gate electrode 32 does not have a lead portion formed therein.

Next, as shown in FIG. 3(e), a P-channel transistor 33 is manufactured. This is also almost the same as the manufacturing method of the N-channel transistor 30, except that the groove depth is different in order to adjust the gate length, that is, the distance between the source and drain. Note that the N-type region for power supply at the bottom of the P-channel transistor was formed by ion implantation of phosphorus, so that XJ was deep. Further, polysilicon becomes the gate electrode 34.

Next, as shown in FIG. 3(f>), the CVD SiO2 film 37 is removed, a phosphorus-doped polysilicon film 35 is formed, and the gate electrodes 32 of both channels are formed by vertical polysilicon etching after a photolithography process. Next, a BPSG film 36 with a thickness of 8000 mm is formed.FIG. 4 is a plan view of FIG. 3(f).

Although the above explanation has been given for an example in which an N-channel transistor is manufactured first, the same applies even if a P-channel transistor is manufactured first.

〔Effect of the invention〕

As explained above, in the present invention, a drain impurity layer is sequentially formed on the Si substrate side that is in contact with the groove drilled in the Si substrate, starting from the top.
A back gate, an impurity layer for the source, and an impurity layer for the source power supply are provided, and a gate insulating film is provided on the surface of the back gate on the sides of the trench. By providing metal for electrode, MO
Since the S transistors can be formed vertically, the surface area occupied on the integrated circuit chip is reduced, which has the effect of increasing the degree of integration of the integrated circuit. Furthermore, since the peripheral length of the trench determines the gate width of the transistor, a large gate width can be achieved with a small area, which is effective in increasing the speed of operation of the integrated circuit.

In addition, the present invention covers the surface of the Si substrate before starting trenching with an insulating film of sufficient thickness that has masking properties for Si vertical etching, so that the insulating film can be aligned in advance only when vertical etching is performed. Although it requires a process and a masking agent such as photoresist, during the subsequent vertical etching,
Since the insulating film itself serves as a masking agent, a MOS transistor can be formed without an alignment process. Therefore, the manufacturing process is shortened, and the button design can be performed without considering alignment errors, which has the effect of increasing the degree of integration of the integrated circuit. Further, although the thickness of the insulating film is reduced by several vertical etchings, a suitable thickness can be left after the gate metal formation is completed, so that it can be used as a field insulating film. If this insulating film is thin, after forming the gate electrode, it is necessary to grow an additional insulating film and perform a photolithography process again to open a window for the gate metal drawer and form a metal film for the drawer. From this point of view as well, forming the insulating film with a certain thickness before the groove trench etching has a great effect in shortening the manufacturing process.

Furthermore, in the manufacturing method of the present invention, by doping impurities for the drain after trenching the surface insulating film, the drain can be formed in contact with the trench with a self-line, thereby reducing the drain area and increasing the integration density of the integrated circuit. This has the effect of improving performance and speed of operation. In addition, after doping the outside of the lower part of the trench with impurities for the source and source power supply, a film of high melting point metal is formed, followed by a silicidation reaction, and the unreacted high melting point metal is removed. The electrode can be formed at a desired position by self-alignment, and the subsequent formation of the gate electrode can be facilitated.

Furthermore, the present invention provides a method for manufacturing a CMOS integrated circuit, in which after fabricating a first conductivity type MOS transistor, the wafer surface is coated with a sufficiently thick masking agent for vertical etching, thereby forming a second conductivity type transistor. It is possible to perform initial alignment and then manufacture without alignment, which has the effect of shortening the manufacturing process.

[Brief explanation of the drawing]

FIGS. 1(a) to (j> are cross-sectional views showing the first embodiment of the present invention in the order of manufacturing steps, FIG. 2 is a plan view of the embodiment shown in FIG. 1,
3(a) to 3(f) are cross-sectional views showing the second embodiment of the present invention in the order of manufacturing steps, and FIG. 4 is a plan view of FIG. 3. 1.21...Si substrate, 2,7.9.22,23゜2
8...5i02 membrane, 3,26.27...drain extraction part, 4.24,29.31...CV D 5i02
Membrane, 5... Groove, 6... Drain, 8...5i02
Sidewall, 10... Source (high concentration N-type layer),
11... Impurity layer for source power supply (high concentration P-type layer), 1
2... High melting point metal (W) layer, 13... Silicide for source electrode (WSi 2 layer), 14... Ge) Si02
Film, 15...Silicide oxide film, 16, 32.34
...Gate electrode, 17.36...BPSG film, 18
...Metal wiring, 25...N type well, 30...N
Channel MOS transistor, 33... P channel MOS transistor, 35... Gate electrode lead-out portion.

Claims (3)

[Claims] (1) A drain impurity layer, a gate region in the silicon substrate, and a source impurity layer are sequentially provided from the surface of the silicon substrate on the side of the silicon substrate that is in contact with a trench perpendicularly drilled inward from the surface of the silicon substrate. , a source power source impurity layer is formed on the bottom surface of the trench, a gate insulating film is formed on the surface of the gate region on the side surface of the trench, and a source power source electrode, an insulating film, and a gate are formed inside the trench in order from the bottom surface. A semiconductor integrated circuit device comprising vertically structured MOS transistors each provided with electrode metal. (2) forming a first insulating film on the surface of the silicon substrate, removing a predetermined region of the first insulating film by vertical etching, and then doping the region with a drain impurity to form a drain region; A vertical groove is formed in this drain region, the silicon substrate on the side surface of this vertical groove is used as a gate region, and the lower part of the vertical groove is doped with impurities for source and source power supply to form a source region. Vertical M
A method for manufacturing a semiconductor integrated circuit device, comprising manufacturing an OS transistor. (3) After fabricating a first conductivity type vertical structure MOS transistor, the wafer surface is covered with a masking agent for vertical etching to a predetermined thickness, and a second conductivity type vertical structure MOS transistor is fabricated.
A method of manufacturing a semiconductor integrated circuit, characterized in that the film of the masking agent is used as a mask for several orders of vertical etching for manufacturing a transistor.