JPS632198A - Dynamic ram - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to a dynamic random access memory (
The present invention relates to improvements in dynamic RAMJs (hereinafter referred to as dynamic RAMJs), and particularly relates to lower power consumption of dynamic RAMs.

[Prior Art] In the development of dynamic RAM as a semiconductor memory device, there are two issues: increasing capacity and increasing consumption during operation. Reducing the II flow has become an important issue. Of these, reducing current consumption! ! ! As an example, an example of a conventionally known technique is disclosed in the magazine "Electronic Materials J, January 1986, January issue." Below, in order to help understand the present invention, the contents disclosed in the above magazine will be described. Based on this, the conventional technology will be explained.

FIG. M3, vj44, and FIG. 5 are diagrams showing a memory cell array block configuration diagram of a conventional dynamic RAM and its operation timing.

FIG. 3 shows, for example, a 1M bit dynamic RAM.
FIG. 2 is a block diagram of a memory cell array block of FIG. In a 1 Mbit dynamic RAM, 1 Mbit address decoding is performed using 10 row address pits from RAO to RA9 and 10 column address pits from CAO to OA9.

For example, in the case of row address RAS-0, memory cell array block #1. #1 +, #3. #3-, #5.
#5-, #7. #7- is selected, and in the case of RAS-1, #2. #2-, #4, #4-, #6. #6-
, #8. #EM will be selected.

In FIG. 4, details of each memory cell array block are shown in block #1. #2 is shown as an example. Further, FIG. 5 shows the operation timing of the circuit of FIG. 4.

Referring to FIG. 4, memory cell array block #1. #
2 each have a memory cell array of 64K (-1M/16) bits, and these are ? ! It consists of several bit line pairs, a plurality of word lines that intersect with the plurality of bit line pairs, and memory cells arranged at these intersections. Figure 4 shows the column decoder to
Details of one pair of bit lines extending from memory cell array #1 to memory cell array #2 are shown. The circuit in Figure 4 is
A two-stage sensing method is used to detect and amplify the bit line potential.

In the case of a capacitor cell type dynamic RAM as shown in Figure 4, the signal voltage appearing on the bit line is determined by the memory cell capacity and the bit line stray capacitance l ratio; if this is large, the signal voltage becomes small, and the sense amplifier The operating margin becomes smaller. Therefore, in the circuit shown in FIG. 4, the bit line pair is divided into two parts, and sense amplifiers are provided in both parts.

More specifically, in FIG. 4, BLO-.

BLO- is a bit line pair belonging to memory cell array block #1, BLO, BLO is memory cell array block #1
This is a bit line pair belonging to 2, and both are trans? Connected via game 1-QTO, QTO. Bit line transfer signal φT is input to transfer gates QTO and QT0. SA1. SA2 is a sense amplifier that detects and amplifies the potential of the bit line pair B10'', BLO- or BLO, BLO, respectively.
The end of bit line pair BL0.8LO is gate QCO.

connected to data line I10.1/-0 via QCO,
These QCOs are selected by the output C80 of the column decoder. Zaranimata, φ,.

, φ, 2 are sense amplifiers SA1., φ, 2, respectively. This is an activation signal for SA2.

Next, the operation of the circuit shown in FIG. 4 will be explained according to FIG.

+) In the case of RAS-0 In this case, memory cell array block #1 is selected, and one 2-8 block in memory cell array block #1 becomes selected and starts up. As a result, a signal voltage from the selected memory cell appears on the bit line. Next, signal φ5. rises, the sense amplifier SA1 is activated, and the potential of the bit line pair BLO-, BLO- is detected and amplified. At this time, the signal φT is at the "L II level" and the transfer gates QTO, QTO are in a non-conducting state, so the bit line stray capacitance is
-, BLO- and the bit line pair BLO, BLO are connected to each other, the signal voltage appearing on the bit line pair is almost doubled, and the read operation margin of the sense amplifier is It is increasing.

After this, the signal φT becomes "H" level, and bit line pair B
LO-, BLO-,! =Bit line pair BLO.

When connected to BLO, the bit line pair BLO-.

The potential of BLO- is transmitted to the bit line pair BLO, BLO side. After this, the signal φ,2 rises, the sense amplifier SA2 operates, and the bit line pair BLO.

BLO(7)? BLO-, BLO-(
7) Depending on the potential, the level will be "High" or "High".

After this, when fj No. CAS falls, the column address is latched, and the column decoder operates, only the decoder output corresponding to the column address becomes "H level". For example, when C5O becomes "H+t level", bit line pair BLO , BLO and data line 110.17'O are connected to form data line pair I10. Data is stored in I10. According to this data, an external data output □out occurs.

ii) For RAS-1 In this case, memory cell array block #2, ie, the block closer to the column decoder, is selected. At this point, as in case i), memory cell array 1' block #2 performs the sensing operation, but since this is the block closer to the column decoder, memory cell array block #1 does not perform any operation. Therefore, the signal φ8 remains at the “L” level and the signal φ8.
” level remains. As a result, bit line pair 8LO
- and BLO- remain in the precharged state (potential VP&).

As is already clear from the above explanation, in FIG.
The signal timing shown by the dotted line shows the case of RAS-0, and the signal timing shown by the solid line shows the case of RAS-1.

Furthermore, a circuit that outputs a signal at the timing shown in FIG. 5 can be replaced with a circuit as shown in FIG. 6, for example.

In the case of I) RAS-0 explained above, 1i) RAS-
1, each memory cell array block #1
The operation of the memory cell array block #2 has been described, but considering the operation of the entire memory cell array block, it is as follows. That is, as is clear from FIG. 3, 1) In the case of RAS-0, memory cell array block #4. #4', #8. #8- is in non-operating state,
1i) In the case of RAS-1, memory cell array block #1. #1', #5. #5” is in non-operating state,
In either case, 1/4 of the entire memory cell array block is in a non-operating state, so the bit line charging current of 1m supplied from ta to the bit line is compared to when all memory cell blocks are in operation. It becomes 3/4. This has the advantage that current consumption during operation of the memory chip can be reduced.

[Problem to be solved by the invention 1 Next, the problems of the above-mentioned conventional example will be described.

For example, in the case of 1) RAS-0 above, bit line pair BL0.810 belonging to memory cell array block #2 also needs to operate. This is the bit line pair BL0,
8LO to bit line pair BLO-.

8LO- and data line pair I10. This is because it is used for connection with I10. However, although this operation is necessary in normal read and write operations, in a refresh cycle in which only memory cell data is refreshed, it is an operation without total <lIm. Therefore, in the above conventional example, during the refresh cycle, blocks that do not need to operate, that is, blocks that do not need to operate over 1, -' 4 of the total, are operating, and this causes an unnecessary increase in current consumption. This means that

As described above, conventional dynamic RAM includes a memory cell array block that operates unnecessarily during a refresh cycle.
! The problem was that the current was large.

The present invention has been made to solve these problems, and an object of the present invention is to provide a dynamic RAM that can reduce current consumption during refresh cycles.

[Means for Solving the Problems] The present invention provides a dynamic RA having a structure in which a plurality of memory cells, word lines, and bit lines are divided into bit line pairs connected to one column decoder.
In M, during the refresh cycle, only the portion of the divided bit line pair connected to the memory cell that requires refresh operation operates, and the other portion remains in an inactive state (precharged state). It is something.

[Operation] The internal refresh clock in the present invention controls the sense system so as to prohibit the operation of memory cell array blocks that do not require refresh operations only during refresh cycles.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a dynamic type R according to an embodiment of the present invention.
FIG. 2A and FIG. 2B show the operation timing diagram of AM.
The figure shows an example of a circuit for outputting each timing signal shown in FIG. 1. The configuration of the memory cell array itself that operates at the operation timing shown in FIG. 1 is as shown in FIGS. 3 and 4.
It is similar to the conventional one shown in the figure.

In FIG. 1, the dotted line shows the case of RAS-0, and the solid line shows the case of RAS-1. The timing in FIG. 1 shows the case of a CAS-before-RAS refresh cycle, which is one of the known refresh modes.

If the fall of CAS is earlier than the fall of RAS, the refresh mode starts and the internal signal REF becomes "H" level. An example of a circuit for generating the signal REF is shown in FIG. 2A. At this time, when RAS falls, the internal refresh address counter address (Qi, +
-0 to 8) are latched, and memory cell data at the corresponding row address is refreshed. That is, in this case, the memory block selection using RAS-0, 1 in the conventional example is performed in exactly the same way, only by setting RAS to 08.

However, unlike the conventional example, there is no need for memory cell array block #2 to operate following this. Therefore, in this case, the signal φrt3 and the signal φs2 are “
It remains at L'° level. By doing this, memory cell array block #2 does not operate, and therefore, the bit line pair BLO, BLO is in a precharged state (voltage VF
R) is maintained.

The concept just described can be described as follows for the entire memory cell array as shown in FIG. That is,
During the refresh cycle, if +>08-0, memory cell array block #2.62', #4゜#4-
．． #6. #6-, #8. #8- is in a non-vJ operation state, ii) When Q g = 1, memory cell array block #1. #1 ′, #3゜#3
-, #5. #5-, #7. #7- is in the non-operating state, and in either case, 1/2 of the entire memory cell array block is in the non-operating state. Therefore, bit line charging'! ? The lt current is 1/2 of that when the entire memory cell array block operates, and can be reduced to 2/3 of that in the normal mode cycle. Therefore, during the refresh cycle, it is possible to further reduce current consumption than during the normal mode cycle.

As already mentioned, FIG. 2B shows an example of a circuit that outputs a signal with the timing shown in FIG. 1.

In the above embodiments, the refresh cycle is a CAs before RAS refresh, but this is not limited to other refresh control methods, such as an external refresh control @signal input, or a constant refresh control such as a response refresh method. It should be pointed out that the present invention can be similarly applied to a system in which refresh is performed using an internally generated signal at a period of , and other systems. Therefore, the technical idea of the present invention can be applied regardless of the refresh control method.

[Effects of the Invention] As described above, according to the present invention, the dynamic RA
In M, by prohibiting the operation of memory cell array blocks that do not require operation during the refresh cycle,
Current consumption during refresh cycles can be reduced.

[Brief explanation of drawings]

FIG. 1 is an operation timing diagram of a dynamic RAM according to an embodiment of the present invention. Figures 2A and 2
FIG. B shows an example of a signal generation circuit for realizing the operation timing shown in FIG. FIG. 3 is a block diagram of a memory cell array block of a conventional dynamic RAM and an embodiment of the present invention. FIG. 4 is a circuit diagram showing details of the memory cell array block shown in FIG. 3. FIG. 5 is an operation timing diagram of a conventional dynamic RAM. FIG. 6 is a signal generation circuit diagram that outputs signals at the timing shown in FIG. In the figure, REF indicates a refresh signal, and Ql indicates a count value of a counter.

Claims (1)

[Claims] (1) In response to entering refresh mode in a dynamic random access memory that has multiple memory cells, word lines, and bit lines, and has a structure in which the bit line pairs connected to one column decoder are divided. a refresh signal generation circuit that generates a refresh signal; a refresh address counter circuit that performs a counting operation based on the refresh signal generated by the refresh signal generation circuit and sequentially designates memory cells that require refreshing; a refresh control circuit that responds to a refresh signal to refresh only a circuit portion including a memory cell designated by the refresh address counter circuit, and maintains other circuit portions in a non-operating state (precharged state) in which no refresh is performed; A dynamic random access memory comprising: