JPS63266494A - Operation control circuit for voice recorder/reproducer - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] (a) Industrial application field The present invention converts a recording signal obtained from a microphone into a digital signal and stores it in a semiconductor memory circuit, and also stores it in the semiconductor memory circuit during playback operation. The present invention relates to an audio recording and reproducing device that reads out a signal, converts it into an analog signal, and emits the sound through a speaker.

(b) Prior Art Cassette tape recorders, which use magnetic tape and are called cassette tapes, have become popular as devices for recording and reproducing audio. Devices such as cassette tape recorders that use magnetic tape as a means of recording audio signals have the advantage of being able to perform long recording operations, but they are difficult to miniaturize. Since it requires a mechanism to drive the magnetic tape, there is a problem in that the failure rate is high. As an improved device in this respect, the audio signal is converted into a digital signal and stored in a semiconductor memory, and during playback operation, the signal stored in the semiconductor memory is read out, converted into an analog signal, and then emitted through a speaker. Such advanced technology has been developed, and examples of such technology include
There is one disclosed in Japanese Patent No. 2800.

(c) Problems to be Solved by the Invention The technology disclosed in the above-mentioned publication uses a semiconductor memory as a means for recording audio signals, which eliminates the need for a drive mechanism such as a tape recorder, and the device It has the advantage of being smaller and lowering the failure rate. However, such a device has the problem of poor operability since it is necessary to perform a recording operation after specifying an address. The present invention aims to provide an audio recording/playback device that is improved in this respect.

(d) Means for Solving the Problems The operation control circuit of the present invention is capable of controlling the ADPC during recording and playback operations.
An ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis using the M method, a semiconductor memory circuit that is detachable from the main body and is provided with an index memory section, and an output from the ADPCM analysis and synthesis circuit. control the writing operation of digital signals to the semiconductor memory circuit, the reading operation of signals stored in the semiconductor memory circuit, and the writing operation of index data to an index memory section provided in the semiconductor memory circuit. It is comprised of an address control circuit, and a control circuit that controls the operations of the ADPCM analysis and synthesis circuit, semiconductor memory circuit, and address control circuit in response to recording, playback, and high-speed feed operations.

(*) Effect The present invention writes first data indicating the maximum recording end position during recording operation into an index memory section provided in a semiconductor memory circuit, and also writes second data indicating the current position during playback and high-speed forwarding operations. is written in the index memory section, thereby starting the recording operation from the recording end position based on the first data, and starting the playback and high-speed forwarding operations from the position based on the second data.

(F) Embodiment The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. In the circuit shown in Fig. 1, (1) is a microphone that is in an operating state during recording operation and converts an acoustic signal into an electrical signal; (2) is a microphone (1) that converts an acoustic signal into an electrical signal;
) is input with a recording signal converted into an electrical signal and amplifies the signal; (3) is a recording amplifier circuit into which the recording signal amplified by the recording amplifier circuit (2) is input and which also amplifies the signal; This is a low-pass filter that blocks high-frequency signals. (4) is A- which converts the analog signal passed through the low-pass filter (3) into a digital signal.
The D converter (5) is an ADPCM that performs digital processing using a method called adaptive differential pulse code modulation.
The analysis and synthesis circuit (6) is the ADPCM analysis and synthesis circuit (
A D-A converter (7) converts the digital signal processed by the D-A converter (5) into an analog signal;
) to which the reproduced signal converted into an analog signal is input, and a low-pass filter that cuts off unnecessary high-frequency signals; (8) receives the reproduced signal that has passed through the low-pass filter (7), and amplifies the signal. The reproducing amplifier circuit (9) is a speaker to which the signal amplified by the reproducing amplifier circuit (8) is applied and also emits the signal. (10) is the ADPCM analysis and synthesis circuit (5
), a control unit that controls the voice analysis operation and the voice synthesis operation;
(11) is a data I10 buffer circuit that controls the input/output operation of signals between an external circuit, which will be described later, and the control section (10) and ADPCM analysis/synthesis circuit (5). In such a circuit, an A-D converter (4), an ADPCM analysis and synthesis circuit (5), a D-A converter (6), and a control section (10).
The data I10 buffer circuit (11) constitutes an audio processing circuit (11), but such a circuit may be, for example, LSI'MSM625B manufactured by Oki Electric Industry Co., Ltd., and its details will be omitted. (13) is a data 110 buffer circuit (11) that constitutes the audio processing circuit (婬).
A RAM (14) is a semiconductor memory that stores digital signals output from the RAM (14) and is equipped with an index memory section in which the usage position of the memory, that is, the consumption time is written as index data. This is an address control circuit that controls operations, read operations, and index data write operations, and is built into a card-type container together with the RAM (13). The container is removably attached to the main body of the audio recording and playback device, and the RA is contained inside the container.
A backup battery (not shown) is incorporated to maintain the memory operation of M(13). (16) is the audio processing circuit (Tsubo), RAM (13) and address control circuit (
This is a control circuit that controls operations such as 14). Reference numeral (17) denotes a recording operation switch that is pressed and closed by a recording operation, and when the recording operation switch (17) is closed, the audio signal is stored in the RAM (13). (18) is a regeneration operation switch that is pressed and closed by the regeneration operation, and the regeneration operation switch (18)
When the RAM (13) is closed, signals stored in the RAM (13) are read and reproduced. (19), (2
0) and (21) are a fast-forward operation switch, a rewind operation switch, and a stop operation switch, which are pressed and closed during a fast-forward operation, a rewind operation, and a stop operation. In such a configuration, an audio signal is stored in the RAM (13) by the recording operation, but at this time, first data indicating the maximum recording end position of the memory, that is, the maximum usable position of the memory is written to the index memory section, and the corresponding The first data is not erased until an erase operation is performed. Also,
When the recording operation is further performed beyond the maximum recording end position of the memory, new first data is written to the index memory section. Then, when a playback operation, fast forward operation, or rewind operation is performed, second data indicating the current position where the memory read operation is being performed is stored in RAM (13).
It is configured so that it is written to the index memory section provided in the index memory section. (22) is a clock circuit, (23
) is a display selection circuit that selects the clock display signal output from the clock circuit (22) and the display signal output from the control circuit (16), and (24) is the display selection circuit (2).
3) based on the display signal selected by the display (25).
). (26) is the indicator (
This is a display selection switch that selectively changes the content displayed on the display (25), and each time it is pressed and closed, the content displayed on the display (25) changes from clock display → counter display → remaining amount time display → consumption time. It has the function of switching the display in the order of one clock display. Reference numeral (27) is a correction/reset operation switch which acts as a time adjustment switch when the clock is displayed and also functions as a reset switch when the counter is displayed. (28) is an erase operation switch, and the rewind operation switch (
RAM (
13) is configured to be erased while performing a rewinding operation. (29) is a battery built into the main body of the audio recording/playback device; (30) is a power switch; when in the open state, the control circuit (1)
6) etc. from the battery (29). In addition, a clock circuit (22), the clock circuit (2
2) The circuit for displaying the time on the display (25) using the signal output from the power switch (30)
The structure is such that power is supplied from the battery (29) regardless of whether the battery (29) is opened or closed.

The present invention is constructed as described above, and its operation will be explained next. If the sampling frequency in the audio processing circuit (frustration) is 8 KHz and the number of quantization bits is 4, the bit rate will be 32 bits/second, and if the capacity of the RAM (13) is 4 Mbits, it will be stored for about 128 seconds. I can do it. In the present invention, the speech analysis and synthesis processing by the ADPCM analysis and synthesis circuit (5) and the write operation to the RAM (13) accompanying the processing are performed in phrases of 250 milliseconds. That is, the audio processing circuit (tsubo)
The analysis and synthesis operation by the ADPCM analysis and synthesis circuit (5) is started by a start signal output from the control unit (10) incorporated in the control unit (10), and after 250 milliseconds, the control unit (
10) The speech analysis and synthesis operation is stopped by the stop signal outputted from. When a signal is written to the RAM (13), that is, during a recording operation, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) for the aforementioned 250 milliseconds is sent through the data I10 buffer circuit (11) to the R
AM (13) and address control circuit (1
By the control operation 4), the data is written into the RAM (13) while specifying the address. Also, RAM (13)
At the time of readout operation, that is, reproduction operation, of the signal from the ADPCM analysis and synthesis circuit (5),
The synthesized signal is input to the DA converter (6) and converted into an analog signal. In this way, the RA by the audio processing circuit (婬) and the address control circuit (14)
The control operation of M(13) is performed, and each operation in this embodiment will be explained next with reference to FIG.

When the user performs a recording operation after closing the power switch (30), power is supplied to the recording amplifier circuit (2), and the recording operation switch (17) is pressed and closed, and the control circuit (16) Control operations for recording are performed. A recording signal converted into an electric signal by a microphone (1) is manually input to a recording amplifier circuit (2), amplified, and then input to an audio processing circuit (婬) through a low-pass filter (3). The recorded signal input to the audio processing circuit (processor) is converted into a digital signal by the A-D converter (4), and analyzed by the ADPCM analysis and synthesis circuit (5) for 250 milliseconds each. It is done.

Further, the signal analyzed and processed by the ADPCM analysis and synthesis circuit (5) is outputted to the RAM (13) through the data I10 buffer circuit (11) and is sent to the address control circuit (
14) is written to RAM (13). Then, while the recording operation is being performed, the above-mentioned A
Analysis operation and RAM by DPCM analysis and synthesis circuit (5>)
(13) Until the write operation is stopped,
Alternatively, the process is repeated until the capacity of the RAM (13) is used up. FIG. 2(a) explains such a recording operation, and the signal that has been subjected to voice analysis processing using the ADPCM method is a phrase (a).

Separate them like (b), (c)... and store them in RAM (
13). ADPC at point (A) of each phrase
The analysis operation by the M analysis and synthesis circuit (5) is started, and (B
The analysis operation stops at point ), and the period between (A) and (B) is 250 milliseconds. The recording operation is performed in this way, but each time the recording operation of each phrase is performed, the RAM is
First data indicating the maximum usage position of the memory is written into the index memory section provided in (13). The first data will be retained together with the audio signal by the backup battery even if the container (long) is removed from the main body of the audio recording/playback device. For example, in Figure 2 (a), phrases (a), (b), (c)
When recording and (d)′ Press the stop operation switch (
21) is suppressed and the recording operation is canceled, the phrase (
First data, which is index data indicating the position where d) is written, is written into the index memory section.

In such a state, if the power switch (30) is opened, the power supply to the control circuit (16) etc. will be cut off.
The signal and first data written to AM (13) are stored and held by a backup battery. When the power switch (30) is closed after the RAM (13) in which the audio signal has been recorded in this manner is installed in the main body, power is supplied to the control circuit (16) and the like as described above.
16), the first data written in the RAM (13) is read. If you perform a recording operation in such a state, the recording operation described above will start, but the RA
The operation of writing the audio signal to M(13) is performed from phrase (ne), which is the next phrase after the aforementioned recording end position, and the first data written in the index memory section is rewritten one after another. It turns out.

The recording operation in this embodiment is performed as described above, but
Next, the playback operation will be explained. When the power switch (30) is closed after the RAM (13) is installed in the main body, power is supplied to the control circuit (16), etc., and the control circuit 1
6), the first data written in the RAM<13) is read. For example, by recording operation, as shown in Fig. 2(a).
When the RAM (13) in which the audio signals from phrases (A) to (E) shown in the figure are written is installed, the control circuit (16)
), it is recognized that the audio signal has been written up to the position of phrase (ne), that is, the maximum usable position of the memory. In such a state, when a regeneration operation is performed, power is supplied to the regeneration amplifier circuit (8), the regeneration operation switch (18>) is pressed and closed, and the control circuit (16) performs a control operation for regeneration. In this case, since the second data indicating the current position is not written in the RAM (13), the reproduction operation will be performed from the beginning of the memory, that is, from the phrase (A).
The signal described in 3) is the address control circuit (14
) and the data I1
The signal is input to the ADPCM analysis and synthesis circuit (5) through the 0 buffer circuit (11). The ADPCM analysis and synthesis circuit (
The digital signals input to 5) are synthesized by the ADPCM analysis/synthesis circuit (5) for 250 milliseconds each, and then applied to the DA converter (6) to be converted into an analog signal. The signal converted into an analog signal by the DA converter (6) is input to a reproduction amplifier circuit (8) through a low-pass filter (7), amplified, and then emitted by a speaker (9). While this reproducing operation is being performed, second data indicating the current position is written into the index memory section provided in the RAM (13). For example, the phrase (
When phrases (a), (b), and (c) are played, press and close the stop operation switch (21) to cancel the playback operation, and index data indicating the position where the playback operation of phrase (c) was performed is displayed. Certain second data is written to the index memory section. In such a state, when the power switch <30) is opened, the power supply to the control circuit (16) etc. is cut off, but the audio signal, first data and second data written in the RAM (13) are , is stored and retained by a backup battery. When the power switch (30) is closed after the RAM (13) is installed in the main body, power is supplied to the control circuit (16) etc. as described above, and the control circuit (16) supplies power to the RAM (13). The written first data and second data are read out. If a playback operation is performed in such a state, the above-mentioned playback operation is performed, but the readout operation of the audio signal from the RAM (13) is based on the second data, that is, the phrase (
It will be performed from phrase (d), which follows c). The playback operation starts like this, but the phrase (E)
When the audio signal is reproduced up to that point, since no audio signal has been recorded beyond that point, the reproduction operation is automatically canceled and becomes stopped, and the first data and the second data become the same. Second
Figure (b) shows such a reproduction operation, in which the synthesis operation by the ADPCM analysis and synthesis circuit (5) starts at point (A) of each phrase, and the synthesis operation stops at point (B).
The period between (A) and (B) is 250 milliseconds.

The recording and reproducing operations are performed as described above, but the operations when fast forwarding and rewinding operations are performed will now be described. When the fast-forward operation is performed, the "fast-forward" operation switch (19) is closed and power is supplied to the reproduction amplifier circuit (8). When the fast-forward operation switch (19) is closed, the control circuit (16) performs a control operation to read signals from the RAM (13) and ADPCM.
The synthesis operation by the analysis and synthesis circuit (5) is performed as shown in FIG. 2(c). As is clear from the figure, the beginning of each phrase <A) to (C
) The readout and synthesis processing operations are performed only during the period ( ) and the sound is emitted from the speaker (9). If the period between (A) and (C) is set to 174, or 62.5 milliseconds, between each phrase (A) and (B), it will be played back at four times the speed as compared to the playback operation described above. However, unlike a tape recorder, the frequency of the signal emitted from the speaker (9) does not become high, so the reproduced signal can be heard, albeit fragmentarily. The operation when performing the fast forward operation is performed in this way, but the operation when the rewind operation is performed will be explained next. When the rewinding operation is performed, the rewinding operation switch (20) is closed and power is supplied to the reproducing amplifier circuit <8>. When the rewind operation switch (20) is closed, the control circuit (1
6), the signal reading operation from the RAM (13) and the synthesis operation by the ADPCM analysis and synthesis circuit (5) are performed as shown in FIG. 2(d). As is clear from the figure, only the beginning parts (A) to (C) of each phrase analyzed during the recording operation are read out and synthesized, and the sound is emitted from the speaker (9). The order of the phrases in which the reading operation is performed is in the opposite direction to the direction during the recording operation. This way (A) ~ (
C) If the interval between each phrase (A) and (B) is set to 174, or 62.5 milliseconds, the rewinding speed will be four times that of the playback operation described above.
Unlike a tape recorder, the frequency of the signal emitted from the speaker (9) not only does not increase in frequency, but also becomes distorted as words, so the reproduced signal can be heard, albeit in fragments.The fast-forward operation described above The signal recorded in the RAM (13) can be found by performing a rewind operation, but when such an operation is performed, the second data indicating the current position is stored as in the playback operation described above. This will be written to the index memory section. Therefore, when the fast forward or rewind operation is performed again after returning to the stopped state, the fast forward or rewind operation will start from the position based on the second data mentioned above. When the fast-forward operation reaches the maximum memory usage position, that is, the position specified by the first data, the fast-forward operation is automatically canceled and becomes a stopped state.Then, the fast-forward operation state and the rewind operation state At times, the stop state can be switched to by pressing the stop operation switch (21) to close it.

Recording, playback, fast-forwarding, and rewinding operations are performed as described above, but the erasing operation will be explained next. Such an erasing operation is performed by pressing and closing the rewinding operation switch (20) and the erasing operation switch (28). If you perform an erase operation, the RAM (
13) It is possible to erase the audio signal stored in . Also, when such an erase operation is performed, the RAM (13)
The first data and second data written in the index memory section provided in the index memory section will also be erased. In this way, the erasing operation is performed from the position of the first data, but it is also possible to perform the erasing operation from the middle of the memory, and in this case, the first data is not erased. Furthermore, if the erase operation is performed from the first data position and the erase operation is canceled in the middle, the RAM (13
) The first data and the second data are written to the index memory section provided in the key.

Each operation in this embodiment is performed as described above, and next, the display operation will be explained with reference to FIG. 3. FIG. 3 shows an example in which a liquid crystal is used as the display (25). First, the clock display operation will be explained. Such display operation is
This is done by operating the display selection switch (26), and when the clock display state is entered, the display section (31) provided corresponding to the position where "clock" is printed becomes operational.

When the clock display becomes operational, the AM display section (32),
Afternoon display section (33), first display section (34) that displays the time
, a second display section (35) that displays minutes, and a colon section (36) that blinks every second are activated to display the time. In this state, a signal from the clock circuit (22) is input to the drive circuit (24) through the display selection circuit (23), and the time is displayed on the display (25) by the drive operation of the drive circuit (24). Is displayed. In addition, in such a state, the time can be corrected by operating the correction/reset operation switch (27). Although the display operation as a clock is performed in this way, other display operations will be explained next. When a recording operation and a playback operation are performed, the above-mentioned recording operation and playback operation are performed, but in such a state, the recording display section (37) and the playback display section (38) are in the operating state and each operation is performed. display that the When the display selection switch (26) is operated to display the counter during such recording and playback operation, the display section (39) provided corresponding to the position where the counter is printed will be displayed.
becomes operational. When the counter display operation is performed, the number display elements forming the first display section (34) and the second display section (35) display the count value. When the counter display is in the operating state, a count signal output from the control circuit (16) is input to the drive circuit (24) through the display selection circuit (23), and the count value is changed by the drive operation by the drive circuit (24). is displayed on the display (25). The count signal output from the control circuit (16) is
Write operations to the AM (13) and read operations from the RAM (13) are performed based on controlled address signals.

For example, during the recording operation, the address control circuit (1) is used when writing the phrase (A) and when writing the phrase (E).
If the count value is increased by one based on the address signal controlled by 4), the count value displayed on the display (25) will change every second. In other words, if the count signal output from the control circuit (16) is set to change every second, the display (25)
The count value displayed in > indicates the recording time. In addition, during the playback operation, the count value is similarly increased by one based on the address signal controlled by the address control circuit (14) during the readout operation of the phrase (A) and the readout operation of the phrase (E). vessel(
The count value displayed in 25) changes every second. That is, if the count signal output from the control circuit (16) is set to change every second as described above, the count value displayed on the display (25>) will indicate the playback time. The counter display operation is performed during the recording operation and the playback operation as shown in FIG. The operation shown in FIG. When the count value is increased by 1, the count value displayed on the display (25) becomes 17.
It will change every 4 seconds. That is, as mentioned above, the fast-forward operation is played back at four times the speed as compared to the recording and playback operations, but the count value displayed on the display (25) also increases at four times the speed, so it is in the fast-forward operation state. The counter display operation can be performed. Further, the counter display operation during the rewinding operation is performed in the same manner as during the fast forwarding operation, although the count value decreases, so a description thereof will be omitted.

The display operation as a counter is performed as described above, but next, the display operation of the remaining amount time will be explained. When the container is attached to the main body of the audio recording and playback device, if you operate the display selection switch (26) to display the remaining amount, the remaining amount and the position where the print is finished will be displayed. The provided display section (40) becomes operational. In such a state, the display selection circuit (2) is switched from the control circuit (16).
The signal output to 3) is output based on the signal obtained from RAM (13). That is, RAM (13)
The remaining time is calculated by the control circuit (16) from the first data indicating the maximum memory usage position written in the memory, the second data indicating the current usage position, and the capacity of the memory, and the remaining time is calculated based on each data. The signal representing the display selection circuit (
23>. The signal representing the remaining amount of time is
The voltage is applied to the drive circuit (24) through the display selection circuit (23), and the remaining time is displayed on the display (25) by the drive operation of the drive circuit (24). In this case, the first display section (34> and the second display section (34) constituting the display device (25)
The display section (35) displays the second data, that is, the remaining amount of time based on the current usage position, and the third display section (41) and the fourth
The display section (42) displays the first data, that is, the remaining time based on the memory maximum usage position.

In addition, when such a display operation is being performed, the minute display sections (43) and (44) provided on the lower right side of the first display section (34) and the third display section (41), and the second display section ( 35) and the seconds display sections (45) and (46) provided on the lower right side of the fourth display section (42) are in operation to make the user aware that minutes and seconds are being displayed. . and,
When recording, playback, fast-forwarding, or rewinding operations are performed while in such a display state, the second display section (35) and the first display display the remaining time based on the current position of use in response to the operations. The value of the third display section (34) changes, but the value of the third display section (41), which displays the remaining amount of time based on the maximum memory usage position, changes.
) and the values of the fourth display section (42>) do not change until the first data is rewritten by the recording or erasing operation described above.

The operation of displaying the remaining amount time is performed as described above, but next, the operation of displaying the consumed time will be explained.

When the container is attached to the main body of the audio recording and playback device, operate the display selection switch to display the consumption time. The display section (47) becomes operational. In this state, the signal output from the control circuit (16) to the display selection circuit (23) is output based on the signal obtained from the RAM (13).

That is, the first data indicating the maximum memory usage position written in the RAM (13) and the second data indicating the current usage position are read by the control circuit (16), and the consumption is determined based on the read signal. A signal representing time is output to a display selection circuit (23). A signal representing the time consumed is sent to the drive circuit (24) through the display selection circuit (23).
is applied to the drive circuit (24), and the consumed time is displayed on the display (25) by the drive operation by the drive circuit (24). Also in this case, the first display section (34) constituting the display device (25)
), the second display section (35), the minute display section (43), and the second display section (45) display the consumed time at the current use position, and the third display section (41) and the fourth display section (42
), the minutes display section (44), and the seconds display section (46) operate to display the time consumed at the maximum memory usage position. In addition, when recording, playback, fast-forwarding, and rewinding operations are performed in this display state, a second display section (
35) and the first display section (34), but the values of the third display section (41) and the fourth display section (42), which display the consumed time based on the maximum memory usage position, are as described above. The first data does not change until it is rewritten by a recording or erasing operation.

As described above, the clock display operation, counter display operation, remaining amount time display operation, and consumption time display operation are performed by the display device (25).Next, the operation when the above-mentioned erasing operation is performed will be explained. Rewind operation switch (20
) and the erasing operation switch (28) are pressed and closed to enter the erasing operation state, but when in such a state, the display section (
48) flashes to indicate that the erase operation is being performed. In addition, when in such a state, the first display section (34
>, second display section (35), third display section (41) and fourth display section
The value on the display section (42) will change in response to the rewinding operation for erasing.

As described above, since the usage status of the RAM (13) is displayed as various data on the display (25), mistakes in recording can be prevented by performing operations such as recording and playback while checking the data. I can do it.

Note that the recording and playback time can be increased by increasing the capacity of the RAM (13) or by setting the sampling frequency low. Furthermore, the analysis and synthesis time during recording and playback operations is set to 250 milliseconds, and the synthesis time during fast forward and rewind operations is set to 62.5 milliseconds, but the times are not limited. Although the count value is set to change every second during the counter display operation, it is possible to make various changes such as changing every 0.5 seconds. Further, although the display device (25) is provided with a display section to indicate that the recording operation and the playback operation are in progress, it is also possible to provide a display section or the like to indicate that fast forwarding or rewinding operation is being performed. Furthermore, although the erasing operation is performed while rewinding, it is also possible to perform the erasing operation while fast forwarding.

(g) Effects of the Invention The recording control circuit of the present invention converts a recording signal obtained from a microphone into a digital signal, stores it in a semiconductor memory circuit that is detachable from the main body, and also stores it in a semiconductor memory circuit that is detachable from the main body. In an audio recording/playback device that is configured to read out a stored signal, convert it into an analog signal, and emit the sound through a speaker, the maximum memory capacity is stored in the index memory section provided in the semiconductor memory circuit during recording operation. First data indicating the recording end position is written, and second data indicating the current position during playback and high-speed forwarding operations is written in the index memory section, so that the recording operation is started from the recording end position based on the first data. Since the playback and high-speed forwarding operations are started from the position based on the second data at the same time as the start, it is possible to perform the recording operation by efficiently utilizing the memory capacity, and it is possible to perform the playback operation again after temporarily interrupting the playback operation. When this is done, the playback operation starts from the signal that was played back and listened to previously, so the operability is very good.

[Brief explanation of the drawing]

The circuit shown in FIG. 1 is an embodiment of the present invention, FIG. 2 is a diagram for explaining the invention in detail, and FIG. 3 is an embodiment of a display. Explanation of main drawing numbers (1)... Microphone, (2)... Recording amplifier circuit, (5)... ADPCM analysis and synthesis circuit, 8)
... reproduction amplifier circuit, (9) ... speaker,
(Ear)...Audio processing circuit, (13)...RAM,
(14)...address control circuit, (16>...
・Control circuit, (22>...clock circuit, (25)・
··display.

Claims (1)

[Claims] (1) Convert the recording signal obtained from the microphone into a digital signal and store it in a semiconductor memory circuit that is removably attached to the main body. During playback operation, the signal stored in the semiconductor memory circuit is read out and then converted into an analog signal. In an audio recording/playback device configured to convert the ADPCM into sound and emit the sound from a speaker, during recording and playback operations, the ADPCM
an ADPCM analysis and synthesis circuit that performs speech analysis and speech synthesis according to a method, a write operation of a digital signal output from the ADPCM analysis and synthesis circuit to the semiconductor memory circuit, and a read operation of the signal stored in the semiconductor memory circuit. and an address control circuit that controls the writing operation of index data to the semiconductor memory circuit, and the ADPCM according to the recording operation, playback operation, and high-speed feed operation.
It consists of a control circuit that controls the operations of an analysis and synthesis circuit, a semiconductor memory circuit, and an address control circuit, and writes first data indicating a maximum recording end position in an index memory section provided in the semiconductor memory circuit during recording operation. At the same time, second data indicating the current position during playback and high-speed forwarding operations is written into the index memory section, thereby starting the recording operation from the recording end position based on the first data, and starting from the position based on the second data. An operation control circuit for a voice recording/playback device, characterized in that it starts playback and high-speed forwarding operations.