JPS6327062A - Mis field-effect transistor - Google Patents

Abstract

PURPOSE:To improve the ON breakdown strength of an MIS type field effect transistor by so forming an impurity diffused layer having the same conductivity type as that of a substrate and a higher impurity density than the substrate on the bottom of an MIS FET source diffused layer as to extend in a drain direction. CONSTITUTION:An N-type drain low density layer region 7 and a high density source diffused layer region 5 are formed on a gate electrode 4 in a self-aligning manner on a P-type silicon substrate 1. An impurity diffused layer 8 having the same conductivity type as that of the substrate 1 and higher impurity density than the substrate is so formed on the bottom of the region 5 as to extend in a direction of the drain 7. Thus, since it can suppress a substrate current in the ON state of the MIS FET and an increase in a punch-through current, the ON breakdown strength of the MIS FET can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS type field effect transistor, and particularly to a MIS type field effect transistor having a high breakdown voltage structure.

[Conventional technology]

MIS field effect transistor (hereinafter referred to as MIS/FE)
The drain breakdown voltage of T is determined by the avalanche breakdown that occurs directly under the gate near the drain due to electric field concentration between the drain and source and between the drain and gate. Therefore, various means have been conventionally taken to increase the withstand voltage of MIS field effect transistors.

FIG. 2 is a cross-sectional view of a conventional high-voltage MIS field effect transistor, in which the highly doped drain region 6 is located several μm from the gate electrode 4.
m and has the same conductivity type as this high concentration drain region 6 and has a low concentration <21017. , -3) drain layer region 7
is formed so as to surround the highly doped drain layer region 6, and is designed to prevent avalanche breakdown directly under the gate.

Here, 1 represents a P-type silicon substrate, 2 represents a field oxide film, and 3 represents a gate vif film.

[Problem that the invention seeks to solve]

However, in this conventional high voltage MIS field effect transistor, when the gate bias is common to the source,
The breakdown voltage is determined by the avalanche breakdown voltage that occurs near the drain under the channel due to the electric field between the gate and drain.

That is, FIGS. 4 and 5 are diagrams comparing the extension of the depletion layer in the ON and OFF states of MIS type field effect transistors for the conventional structure and the structure of the present invention. The breakdown voltage of the MIS-FET structure is determined by the avalanche breakdown voltage at point A in FIG. Here, when the gate bias is increased to a voltage at which the channel is turned on (VG>O in the case of an N-channel MISFET), holes flow into the substrate due to impact ionization and a substrate current I sub is generated. At this time, since the voltage between the gate and the drain in the drain depletion layer becomes small, the depletion layer curves gently, especially under the channel. That is, when the depletion layer contacts the source as shown in FIG. 4, punch-through occurs at point B, and a punch-through current I9 flows. Therefore, the gate bias V o
The substrate current I at a voltage lower than the withstand voltage B'Jos when = 0
The drain current increases due to tub and punch-through current (2). Figure 3 is a comparison diagram of the current-voltage characteristics of high-voltage MIS field effect transistors with a conventional structure and the structure of the present invention, and the characteristic curve (A) shows how the conventional structure increases the drain current in the on state. It is something that

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a high voltage MIS field effect transistor that solves the problem of increase in substrate current and punch-through current in the on state.

[Means for solving problems].

According to the present invention, the MIS type field effect transistor is a MIS type field effect transistor in which a low concentration drain diffusion layer is formed on the -1 plane of a semiconductor substrate having one conductivity type so as to surround a high concentration drain diffusion layer region. An impurity diffusion layer having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate is formed directly below and adjacent to the source diffusion layer region and extending toward the drain side.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention.

Here, on the P-type silicon substrate 1, an N-type drain low concentration layer region 7 is formed in a self-aligned manner with the polycrystalline silicon gate electrode 4, and furthermore, a high concentration source diffusion layer region and the like are formed self-aligned with the polycrystalline silicon gate electrode 4. Consistently formed. In addition, the highly doped drain 6 is several μm away from the polycrystalline silicon gate electrode layer 4.
It has an offset length of m and is formed in the lightly doped drain layer region 7. Further, a concentration layer 10 adjacent to the lower part of the high concentration source diffusion layer region 5 and extending approximately 1 μm in the drain direction is provided.
P-type impurity diffusion layer 8 of about 17 cm-3 is 200 keys
It is formed using a high energy ion implantation process. The MIS-FET with such a structure has a high concentration source diffusion layer region 5.
Since a low concentration P-type impurity diffusion layer 8 is provided below,
When the drain is in the OFF state, a high voltage is applied to the drain, and the hole substrate current generated by impact ionization acts to forward bias the junction between the substrate and the source and suppress the injection of electrons flowing from the source to the substrate.

Furthermore, since the low concentration P-type impurity diffusion layer 8 is formed extending from the source side to the drain side, even when it is in the on state and the drain voltage is high, it does not extend from the drain as is clear from FIG. This makes it possible to reduce the elongation of the depletion layer and suppress the occurrence of punch-through between the source and drain. Characteristic curve <B> in Fig. 3
indicates this state, and the increase in drain current is suppressed. - That is, the on-breakdown voltage of the transistor can be improved. Furthermore, since the low concentration P-type impurity diffusion layer 8 is formed under the channel region, the MIS-FE
It does not affect the TL threshold voltage V↑. Although the above description has been made of the case where the present invention is applied to an N-channel type MOSFET, it is obvious that the present invention can also be applied to a P-channel type MOSFET.

〔Effect of the invention〕

As explained in detail above, according to the present invention, MIS-
By providing an impurity layer on the bottom of the source diffusion layer of the FET that has the same conductivity type as the semiconductor substrate extending toward the drain side and has a higher concentration than the semiconductor substrate, a gate voltage of 7 or more threshold voltages can be applied to the MIS-FET. Even in the on state, the substrate current I1lub and punch-through current generated when a high voltage is applied to the drain can be suppressed, so the on-state withstand voltage of the MIS-FET can be significantly improved.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a high voltage MIS field effect transistor showing an embodiment of the present invention, and Fig. 2 is a cross-sectional view of a conventional high voltage MIS field effect transistor.
Figure 3 is a comparison diagram of current-voltage characteristics of high voltage MIS type field effect transistors in the conventional structure and the structure of the present invention, and Figures 4 and 5 are cross-sectional views of MIS type field effect transistors. FIG. 4 is a diagram comparing the growth of the depletion layer in the on and off states for the conventional structure and the structure of the present invention, respectively. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Field oxide film, 3... Gate oxide film, 4... Polycrystalline silicon gate electrode, 5... N-type source diffusion layer region, 6... N-type drain diffusion layer region, 7... N-type drain low concentration layer region, 8... P-type paper concentration diffusion layer. I cut 'L (power H=V.

Claims (1)

[Claims] In a MIS type field effect transistor in which a low concentration drain diffusion layer is formed on one principal surface of a semiconductor substrate having one conductivity type so as to surround a high efficiency drain diffusion layer region, the semiconductor substrate has the same conductivity type as the semiconductor substrate and has a low concentration drain diffusion layer. A MIS type field effect transistor characterized in that an impurity diffusion layer having an impurity concentration higher than that of a substrate is formed directly below and adjacent to a source diffusion layer region and extending toward the drain side.