JPS63301566A - Nonvolatile semiconductor memory and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a non-volatile semiconductor memory and a method for manufacturing the same, and particularly relates to a control boot, a rotating boot, and a method for rewriting the information contained in the memory. The present invention relates to a possible bladder extraction-only memory cell and a method of forming the same.

(Prior Art) Non-volatile semiconductor memory, such as EPROM (Erat
sabl@Programmable@Read Onl
When writing information into a memory cell (Memory), the control boot is set to a positive high potential to form a channel on the substrate surface, and a positive voltage of 1 voltage is applied to the drain.

At this time, the magnetons traveling in the channel receive high energy p due to the high electric field generated especially near the drain, and the M! 3 So that the electron raft is injected into the 7 rotating guts over the energy barrier caused by the membrane? -The state in which this injection is performed is the write state.

By the way, in order to miniaturize the structure of the memory cell mentioned above, the channel length is shortened, and when the channel length is formed in the Saramicron region, it is necessary to shorten the channel length. In addition, a high electric field is generated near the drain even during a read operation performed at a relatively low voltage. Due to the generation of a high electric field during such a read operation, electrons may be erroneously inserted into the 7-rotating r-}, which may destroy stored data and reduce reliability during long-term operation. There are problems such as

Therefore, in order to avoid such a malfunction during a read operation, a memory cell having a structure as shown in FIG. 7 has been proposed. That is, in the figure, 71 is a P-type silicon substrate, 72 and 73 are N-type M which serve as sources and drains, 74 is a dirt insulating film, 75 is a floating dart, 76 is a control boot 9, and the drain and the drain are connected to each other. There is an N− diffusion layer 77 on the channel side of the N1 loss layer 73.
are formed in contact with each other. Due to the presence of the N- diffusion layer 77, the electric field in the drain chain acid can be relaxed, so that it is possible to prevent malfunctions during the read operation as described above.

However, impurity +1 as mentioned above! The cell structure using a low density region (N-diffusion layer 77) with low IJ yield has a serious drawback of poor insertion characteristics. That is, since the drain electric field is lowered by the N″″ diffusion layer 77, sufficient energy cannot be given to the electrons traveling in the channel region, and the efficiency of injection of adult atoms into the 7-rotating Y-t 75 decreases. It is from.

In order to solve the above-mentioned problems, the applicant of the present application has already made a proposal in Japanese Patent Application No. 308610 of 1988.

In this proposal, by forming an N+ region in the surface region of the N- diffusion layer 77, the current is
+ Floating dart 75 now flows in the territory area
This makes it possible to increase the efficiency of electron injection into.

However, during the above-mentioned implantation operation, channel passes are likely to occur deep in the channel region, making it difficult to generate a sufficiently high electric field in the drain region, which does not necessarily reduce the injection efficiency of the 7-rotating gate. cannot be said to be sufficiently high.

(Problems to be Solved by the Invention) As mentioned above, in the conventional non-volatile memory cell having 7 rotations, if an attempt is made to prevent malfunction during a read operation, the write stability deteriorates. The object of this invention is to provide a nonvolatile semiconductor memory that can prevent malfunctions during read operations and also has good write characteristics, and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) The nonvolatile semiconductor memory of the present invention has a nonvolatile semiconductor memory having a floating gate on the side of the channel region of the drain (or at least one of the sources) than the above region. a low concentration region having a low concentration, a high concentration region having a higher concentration than the low concentration region on the surface of the low concentration region, and further having a high concentration region having a higher concentration than the low concentration region; The semiconductor device is characterized in that a region having the same conductivity type as the semiconductor substrate and having a higher pitch than the semiconductor substrate is formed in a region deeper into the substrate side than the semiconductor substrate.

Further, in the method for manufacturing a non-volatile semiconductor memory of the present invention, after forming a floating dart of a memory cell, a region having a higher concentration than the semiconductor substrate is formed using at least a 70-meter dirt as a mask. A first impurity ion of the same type is implanted into the semiconductor substrate, and then a second impurity ion of a quaternary electric type opposite to that of the semiconductor substrate is implanted into the semiconductor substrate, and then a second impurity ion is implanted at a different dose.
implanting impurity ions into the semiconductor substrate, then depositing a silicon oxide film on the side surface of the floating dart,
The method is characterized in that second impurity ions are implanted into the semiconductor substrate to completely form the source or drain using at least the floating dart as a mask.

(Function) According to the non-volatile memory cell having the impurity concentration distribution as described above, during a read operation, the drain electric field is low due to the presence of the low concentration region, and the p1 channel direct current is separated from the low concentration region. Therefore, the efficiency of electron injection into the 70-teinggut is reduced, and the incidence of -1 injection is reduced. In addition, during the input operation in which a high voltage is applied to the drain/control gate, a high drain electric field is generated in the highly doped region adjacent to the drain, and the channel current passes through the highly doped region, resulting in hot water. The occurrence of carriers increases. Furthermore, the same 4″r!L as the semiconductor substrate
The presence of the high concentration region of ffi makes it possible to suppress the generation of channel noise in the deep part of the channel region between the source and drain when a high dielectric pressure is applied to the drain. A high electric field is likely to be generated in the area.

(Implementation Series) Hereinafter, a case in which one embodiment of the present invention is applied to an N-channel EPROM (C) will be described in detail with reference to the drawings.

FIGS. 1(a) to 1(g) show a cross-sectional structure of a portion of a semiconductor wafer in the manufacturing process of an EPROM. In this manufacturing process, first, as shown in FIG. 1(a), a desired element isolation region 2 is formed on a semiconductor substrate 1 by a normal cable separation method, and an insulating film 3 is formed in the element region. do. Next, the cell d I['+
After performing ion implantation for 5-pressure control, Figure 1 (
As shown in b), a first polycrystalline silicon film 4 is deposited on the entire surface of the substrate by LPCVD (low pressure vapor deposition) at 2000X.
A silicon oxide film 5 is formed on the polycrystalline silicon film 4 to a thickness of 150× by thermal oxidation. Furthermore, after forming a di-silicon nitride film to a thickness of 611soX by the LPCVD method, a desired 72-turn resist pattern and a turn 7fjr are formed to form a floating dart of an EPROM cell (memory cell). Using pattern 7 as a mask, the silicon oxide film 6, silicon oxide film 5, and first polycrystalline silicon film 4 are etched. The cross-sectional structure of the memory cell area for forming memory cells is shown in Figure 1 (
The Ffr plane fabrication of the peripheral region for forming the n1 memory peripheral circuit, which is representatively shown by the left part of FIG. 4, silicon oxide film 5, silicon nitride film 6
It has been removed. Next, the resist pattern 7 is removed and the MIS FET used for the peripheral circuit is removed.
After performing ion implantation of a desired impurity for threshold control according to class d of (insulated dart type field effect transistor),
The dirt oxide film 3 in the peripheral area is removed and the substrate 1 is cleaned. Next, the entire substrate is thermally oxidized to form a silicon oxide film 3' with a thickness of 300X on the substrate as shown in FIG. Silicon nitride M formed on the silicon film 4
A silicon oxide film 8 is formed on the silicon oxide film 6 to a thickness of 10 to 15X.

At this time, a silicon oxide film 9 is formed on the side surface of the first polycrystalline silicon film 4 by oxidation thereof.

Next, a second polycrystalline silicon film 10 is formed to a thickness of 3000× over the entire surface of the substrate by LPCVD. Next, as shown in FIG. 1(d), a p-oxynitride film is formed on the second polycrystalline silicon PIX10 by the LPCVD method to a thickness of 1zylooOX.

The processing conditions at this time were a vacuum degree of 200 Pa, a reaction gas of 5ia2cz2, and a flow rate ratio of N20 and NH3i of 100.
The ratio was 250:500, and the temperature was 800°C. Here, in the cross section shown in FIG. 1(d), the memory cell area is a cross section taken along line A-A'i in the cross section shown in FIG.
A cross section taken in the same direction as figure (d) is shown. Next, a desired T1/-) Stino 4' main (not shown) is formed using a well-known exposure technique, and a resist non-turn for the word line in the memory cell area and a polycrystalline silicon gate for the peripheral circuit FET are formed. and Sost pattern at the same time, and use this Renost pattern as a mask.
As shown in FIG. 1(,), the oxynitride film 11
Then, the second polycrystalline silicon film 10, silicon oxide MXs, silicon oxide film 6, and silicon oxide film 5 are selectively etched. Next, after removing the Renost pattern and cleaning the substrate, the peripheral area is covered with resist, and the first polycrystalline silicon film 4 in the memory cell area is selectively etched using the oxynitride film as a mask. do. In this way, the second polycrystalline silicon BII
A memory cell area word gate (control gate) consisting of O, a peripheral area/gate electrode, and a memory cell area floating gate consisting of the first polycrystalline silicon film 4 are formed. Next, the control dirt and the 70-tain rl'-to 4f mask are applied to the memory cell area.
Boron (B) ions were implanted at a do/l" amount of 5 x IQ" cm at an accelerating voltage of k@V, followed by arsenic (As) ions at a dose of 2 x lOcm at 40 keys, and then 50 1×10 cln at keV
Implantation of As (As) ions is performed. At this time, ion implantation can also be performed in the N-channel MO8FET forming portion in the peripheral region in the same manner as in the memory cell region. Next, after etching the second and first polycrystalline silicon gxops 4, the exposed silicon films 3 and 3' are completely removed and the entire surface of the substrate is cleaned. Next, as shown in FIG. 1(f), a silicon oxide film 12 is deposited on the surface of the silicon substrate at a
Formed at 950°C in 02 atmosphere to a thickness of
A silicon oxide film 13 is formed on the substrate surface by LPCVD method.
It is formed to have a thickness of 000X. Next, the silicon oxide film 12 is etched by an anisotropic dry etching method to leave silicon oxide M13 on the side surfaces of the polycrystalline silicon turns. Next, after cleaning the substrate, the source region and drain region of the N-channel MO8FET in the peripheral region and the source region and drain region of the memory cell transistor in the memory cell region are coated with a 5×1
0153-2, arsenic ions (or phosphorous ions) of 0153-2 are implanted.Next, a 5TOZ film with a thickness of 3000X is formed by CVD as a covering insulating film over the entire substrate, and then PSG ( A phosphosilicate film was formed to a thickness of 100,007 mm, annealed at 950°C for 30 minutes for activation, and contact holes for electrode wiring were formed to form desired aluminum wiring to form an EPROM. The EPROM cell in the EPROM thus formed is shown in FIG.
) It has a cross-sectional structure as shown in (). That is, two types of N- diffusion layers 14 and 15 with different diffusion depths and different impurity concentrations overlap in the substrate below the source side part, the drain part, and the drain side part of the floating f-)4. It is formed. The N- diffusion layers 14, 15 have a lower concentration than the N diffusion layers 16, 17 in the source/drain regions, and are in n contact with the source/drain regions, respectively.

In this case, the impurity concentration of the upper N-diffusion #15 (on the substrate surface side) is higher than that of the lower N-diffusion layer 14. Further, a P+
A diffusion layer I8 is formed.

In the above structure, the typical impurity concentration distribution under the r-edge on the drain side is as shown in Figure 2 (1), where the depth of the substrate is represented by The horizontal direction is shown in FIG. 2(b), and the horizontal direction is shown in FIG. 2(c). N-type impurity in the depth direction above? As shown in FIG. 3, the rate of change in rockiness gradually increases as the depth of the substrate increases, and has a maximum value P at a certain depth. Also, Figure 2 (
b) In CC), P-type impurity (boron) #'
The concentration decreases as the depth of the i-substrate increases, and the concentration decreases from the drain toward the channel side.

According to the EPROM cell having the above structure, the source 16
Since a highly concentrated P- diffusion layer 18 is formed between the drain 15 and the channel region, even if a high drain voltage is applied, electrons do not flow deep into the substrate, which is called "gunchi through". This phenomenon is unlikely to occur.

Therefore, it is possible to apply a high voltage to the drain during a write operation, and it is possible to increase the drain electric field, thereby increasing the efficiency of electron injection into the drain 4. Further, on the channel side of the source/drain, an N- diffusion layer 15 with a slightly higher concentration exists inside the N- diffusion layer 14 with a lower concentration. As a result, during a read operation with a low r-to voltage, the influence of the dirt potential on electrons traveling through the channel is weakened at the dirt edge portion, and the electrons fall deeper into the substrate at the low-concentration N-diffusion layer 14. It comes to pass through this N- diffusion layer 14. Therefore, in addition to lowering the drain electric field, more hot electrons are generated deep in the substrate, and the rate of electrons reaching the 70-teinggut 4 is reduced. On the other hand, during a write operation, since a high dart voltage is applied, electrons traveling through the channel are more strongly affected by the f−) potential under the dart edge, so they continue to flow on the substrate surface, resulting in a high concentration. passes through the N- diffusion layer 15. As a result, electrons pass through areas with a higher electric field, and hot electrons are generated closer to the surface. Therefore, floating gate J
The efficiency of electron injection into the memory increases, and the write characteristics improve.

Further, by using the manufacturing process as described above, an EPROM cell having the above-mentioned effects can be realized by combining existing manufacturing techniques. Moreover, in the process shown in FIG. 1(,), when selectively etching the polycrystalline silicon film 4 of 'fJl, it is used as an oxynitride m1lk mask, so for example, a 5to2 film can be used as a mask. There are advantages in that the side etch marks of the polycrystalline silicon film 4 can be reduced and the processability is the same as in the case where the polycrystalline silicon film 4 is used.

Note that the present invention is not limited to the above embodiments, and
- In the above embodiment, arsenic and arsenic ions are implanted as a step for forming the diffusions 1@14 and 15, but phosphorus CP) arsenic ions may be implanted as shown in row 5. In this case, the typical impurity content under the dart edge on the drain side; f5 is
The direction is as shown in FIG. 4, and the Y direction is the same as that shown in FIG. 2(c). In addition, in the above case, the @-plane structure of the EPROM cell becomes as shown in FIG. The depth relationship between the two and the distribution of the impurity degree in the depth direction under the dart edge are slightly different, but the other parts are the same and are therefore given the same reference numerals.

Further, in the above embodiment, the N'''' diffusion layers 14.15 were provided on each of the drain side and the source side, but they may be provided only on the drain side as shown in FIG. In this case, as a manufacturing process, a 5t
Add a layer of mask to form the O2 film 13, and add arsenic, for example 40 ml, to only the source side of the memory cell area.
This can be achieved by ion implantation at a high dose of k@V, 2X 10' 5 cm-2. E like this
Since there is no N'''' diffusion layer 14, 15 on the source side of the PROM cell, there is an advantage that the parasitic resistance caused by it is reduced and the memory cell current is increased.

In addition, the source and drain are used reversely for writing and reading (with N-diffusion on the source side during storage) fjl16 is used as the drain, and N-diffusion layers 14 and 15 are provided during reading. It is possible to use the N1 dispersion layer 17 on the drain side as a drain, improving the reliability of the EPROM cell.

(9) The nonvolatile semiconductor memory of the present invention can be used not only for memory integrated circuits but also for on-chip devices such as memory-embedded devices.
It goes without saying that the invention can also be applied to memories, and can be applied not only to EPROMs but also to batch erase type E2FROMs and the like.

[Effects of the Invention] As described above, according to the present invention, malfunctions can be prevented during read operations, and increase in hot carriers and generation of channel gas in deep portions of the channel region can be suppressed during commit operations. Accordingly, it is possible to provide a nonvolatile semiconductor memory with good write characteristics and a method for manufacturing the same.

[Brief explanation of the drawing]

1(a) to (2)] are views showing a part of a wafer cross section at each step in an embodiment of the nonvolatile semiconductor memory manufacturing method of the present invention, and FIG. 2(a) l (b) ) l (c
) dA diagram showing the impurity concentration distribution in the depth direction of the substrate and along the substrate surface below the f-) edge of the drain in the EPROM cell in Figure 1 (g), Figure 3 is the same as Figure 2 (a)
FIG. 7 is a cross-sectional view showing an EPROM cell according to another embodiment of the present invention. FIG. The sixth factor is a cross-sectional view showing an EPROM cell according to still another embodiment of the present invention, and FIG. 7 is a cross-sectional view showing a conventional EPROM cell. 1... P-type conductor substrate, 3, 5, 6.8... Insulating film, 4... 70-tin 1"l'-to, 10... Control r-to, 11... Oxynitride #l
2113...Silicon oxide layer, 14.15...N-
Diffusion layer, 16.17...Nt scattering layer, 18...P Asahi scattering layer

Claims (4)

[Claims] (1) A semiconductor substrate of a first conductivity type, and a second conductivity type opposite to the first conductivity type formed in a surface region of the semiconductor substrate at positions apart from each other and serving as source or drain regions, respectively.
A floating gate and a control provided on first and second conductive type semiconductor regions and an insulating film formed on a channel region between the first and second semiconductor regions, separated from each other by an insulating film. a gate; a third semiconductor region of a second conductivity type formed on the channel region side of at least one of the first or second semiconductor region and having a lower concentration than the first or second semiconductor region; A fourth semiconductor region of the second conductivity type formed in the surface region of the third semiconductor region and having a higher concentration than the third semiconductor region; A non-volatile semiconductor memory comprising a fifth semiconductor region formed in a region deeper from the surface of the substrate than the semiconductor region No. 3, and having the same conductivity type as the semiconductor substrate and a higher impurity concentration than the substrate. . (2) forming a polycrystalline silicon gate pattern to serve as a floating gate of a nonvolatile memory cell on an insulating film on a semiconductor substrate; and using at least the polycrystalline silicon gate pattern as a mask, A first ion implantation step in which ions of a first impurity are implanted, a second ion implantation step in which ions of a second impurity having a conductivity type opposite to that of the semiconductor substrate are implanted, and then the second ions are implanted. The second implantation process has a different dose than the implantation process.
a third ion implantation step of implanting impurity ions;
Next, a step of forming a silicon oxide film on the side surface of the floating gate, and a second step using at least the polycrystalline silicon gate pattern as a mask after this step.
a fourth ion implantation step of implanting impurity ions. (3) The ion implantation amount in the second ion implantation step is higher than the ion implantation amount in the third ion implantation step, and the ion implantation amount in the fourth ion implantation step is higher than the ion implantation amount in the second ion implantation step. 3. The method of manufacturing a nonvolatile semiconductor memory according to claim 2, wherein the ion implantation dose is higher than that of the ion implantation amount. (4) Boron ions are implanted in the first ion implantation step, arsenic ions are implanted in the second ion implantation step, arsenic ions or phosphorus ions are implanted in the third ion implantation step, and 4. The method of manufacturing a nonvolatile semiconductor memory according to claim 2, wherein in the ion implantation step, arsenic ions or phosphorus ions are implanted.