JPS6381974A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a technique that is effective when applied to a semiconductor integrated circuit device, particularly a semiconductor integrated circuit device equipped with an SRAM (static random access memory). be.

[Conventional technology]

Semiconductor integrated circuit devices such as microprocessors are equipped with SRAMs and mask ROMs as storage functions.

SRAM is a volatile memory in which information can be written and read freely. An SRAM memory cell is composed of a memory cell selection MISFET and a flip-flop circuit. The flip-flop circuit is, for example, n
It is composed of a complete CMO3 consisting of a channel (for load) MISFET and an n-channel (for drive) MISFET.

Further, the mask ROM has a nonvolatile storage function that allows information to be read. The memory cells of the mask ROM are M I
It is composed of SFET.

SRAM memory cells and mask ROM memory cells are
Since the configurations are significantly different, each has its own dedicated area and SR
AM, masks R, and OM are mounted on a semiconductor integrated circuit device.

Regarding microprocessors, for example, published by Nikkei McGraw-Hill, Nikkei Electronics.

It is described in the January 28, 1985 issue, Pρ 283-290.

[Problem that the invention seeks to solve]

In semiconductor integrated circuit devices having a memory function, such as the aforementioned microprocessor, in response to user requests,
It becomes necessary to expand the amount of information (capacity) of SRAM and mask ROM. In other words, the mask ROM is placed in the SRAM dedicated area.
Furthermore, it becomes necessary to form an SRAM in the area dedicated to the mask ROM. this is.

It is necessary to significantly change the layout and the manufacturing process starting from the 11th floor where memory cells are formed.

This not only complicates the design of the microprocessor but also increases the time required to commercialize it.

An object of the present invention is to
To provide a technology that can easily change three functions and shorten the time required to commercialize the product (shorten the time by one). In particular, it is an object of the present invention to
It is an object of the present invention to provide a technology that can easily change the SRMA to a ROM in a semiconductor integrated circuit device having an AM, and can further shorten the number of units by one.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[Means for solving problems]

A brief summary of one typical invention disclosed in this application is as follows.

In a semiconductor integrated circuit device having SRAM, SRA
M constituting a flip-flop circuit of M memory cells
Impurities of a predetermined conductivity type are introduced into the channel forming region of the I S FET through the gate electrode, and at least one MISFET in the flip-flop circuit is set to a depression type threshold voltage.

[For production]

According to the above-described means, an SRAM memory cell can be easily converted into a ROM by introducing impurities of a predetermined conductivity type in the final stage of the manufacturing process.
Since the memory cell can be changed to one memory cell, the semiconductor integrated circuit device can be completely shortened by one.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention will be described below along with an embodiment in which the present invention is applied to a microprocessor having an SRAM and a mask ROM.

It should be noted that in all the examples, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

〔Example〕

A microprocessor which is an embodiment of the present invention is shown in FIG.
Schematic configuration diagram).

As shown in FIG. 1, a microprocessor composed of one chip is equipped with a CPU unit, a ROM unit, a RAM unit, an I10 unit, and the like. The CPU unit is provided with an arithmetic logic (ALU) section, a shift register (SL) section, and the like. The ROM unit is composed of a mask ROM. Mask ROM
Although not shown, the memory cell is composed of one n-channel MISFET. The RAM unit is S
It is composed of RAM. The I10 unit is configured to process input and output signals.
As shown in FIG. 2 (equivalent circuit diagram), M memory cells are provided at the intersection of a pair of data @DL, DL and word line WL.

The memory cell includes a flip-flop circuit having a pair of input/output terminals, and a transfer (memory cell selection) MISFET QsIt connected to the word line WL and data line DL.
Q10. The flip-flop circuit is
2 load (p channel type) MI 5FETQpt
t For driving QP2 and two (n channel type) M I
It is composed of S F E T Q n s * Q n 2. The load MISFET QP has a source region connected to the power supply voltage wiring Vce, and a drain region connected to the drain region of the drive MISFET Qn. The source region of the drive MI S FETQn is connected to the reference voltage wiring Vss.

The flip-flop circuit consists of MISFETQd+ and Q
Complete CMO8 consisting of n I.

It is composed of a complete CMO8 consisting of M I S F E T Q P 2 and Q n 2. In the flip-flop circuit, the output of one 0MO8 and the input of the other 0MO3 are connected, and the output of the other 0MO3 and the input of one 0MO3 are connected.
It is connected to the input of O3. In other words, the SRAM memory cell has six M I S F E T Q s
.

Tail consisting of Qp and Qn (6MOS type).

For example, a circuit operating voltage of 5 [V] is applied to the power supply voltage wiring Vcc, and the reference voltage wiring Vss is
For example, it is configured such that a circuit ground voltage of 0 [V] is applied.

The memory cell of the SRAM is specifically constructed as shown in FIG. 3 (a plan view of essential parts) and FIG. 4 (a sectional view taken along line IV--IV in FIG. 3). Note that FIG. 3 and FIG. 5, which will be described later, are shown in order to make the configuration of this embodiment easier to understand.
1i except for the field insulating film provided between each conductive layer
The It film is not shown.

In FIGS. 3 and 4, 1 is a p-type semiconductor substrate made of single crystal silicon, and 2 is an n-type well region. 3 is a field insulating film, and 4 is a p-type or n-type channel stopper region.

MISFETQs for transfer,! If active MISFETQn
are formed on the main surface of the semiconductor substrate 1, as shown in detail in FIG. 5 (a plan view of main parts in a predetermined manufacturing process). That is, each of MISFETQs and Qn includes a gate insulating film 5, a gate electrode 6. It is composed of a pair of n0 type semiconductor regions 7 which are source regions or drain regions.

The load MISFET QP is formed on the main surface of the well region 2. In other words, MISFETQp has a gate insulating film S, a gate f! ! It consists of a pole 6 and a pair of 29-type semiconductor regions 8 which are source or drain regions.

The gate insulating film 5 is formed of, for example, a silicon oxide film.

The gate electrode 6 is doped with n-type impurities (As,
It is formed of a polycrystalline silicon film into which P) is introduced.

Further, the gate electrode 6 is made of a single layer of high melting point metal (M or
T a * T l l W ) film or high melting point metal silicide (MoSiz, TaSi2.TiSi2
．． It may also be composed of a WSi2) film. In addition, the gate electrode 6
may be composed of a composite film in which a high melting point metal film or a high melting point metal silicide film is provided on top of a polycrystalline silicon film. , a word line (WL
)6A is connected.

Each of the semiconductor regions 7.8 can be formed by introducing n-type and p-type impurities by ion implantation using the gate electrode 6 as a mask. Each of the semiconductor regions 7.8 is formed in a self-aligned manner with respect to the gate electrode 6. Moreover, especially the semiconductor region 7.

LDD where the channel forming region side has a low impurity concentration
It may also consist of a structure.

Data m(DL) 11 is connected to one semiconductor region 7 of the transfer MISFETQs. The data line 11 extends over the interlayer insulating film 9
It is connected to the semiconductor region 7 through a connection hole 10 formed in the semiconductor region 7 . A connection wiring 11 in the memory cell is connected to the other semiconductor region 7 of the MISFETQs.

The semiconductor region 7, which is the drain region of the drive MISFETQd, is the other semiconductor gAha7 of the MISFETQs.
It is integrated with. In the semiconductor region 7, which is the source region of MISFETQd, there is a reference voltage wiring (Vss).
11 are connected.

These data lines 11, connection wiring 11. The reference voltage wiring 11 is formed in the same process and made of the same conductive material, such as an aluminum film.

The semiconductor region 8 that is the source region of the load MISFET QP is configured integrally with the semiconductor region 8 that is the source region of another adjacent load MISFET Qp, and forms a power supply voltage wiring @V e c. This power supply voltage wiring Vce is made of a low resistance wiring material (
For example, it is connected to the power supply voltage wiring Vcc made of the same conductive material as the reference voltage wiring #111.

In order to form the SRAM configured in this way, the driving MI5FETQnt, Qn2, which constitutes the flip-flop circuit of the memory cell, and the load MTS
Each of F ET Q p i *Q P 2 is set in advance to an enhancement type threshold voltage.

and at least one M in the flip-flop circuit.
ISFET, in this example, MISFET for load
A p-type impurity (for example, B) 13 is introduced into the channel formation region (well region 2) of Q P 2 through the gate electrode 6, and this M I S F E T Q p 2 is set to a depression type threshold voltage. It is set.

The p-type impurity 13 is indicated by the symbol 12 in FIGS. 3 and 4.
Then, it is introduced by ion implantation using a mask (for example, a photoresist film) shown by a dashed line. p-type impurity 13
is between the source region and drain region (between semiconductor regions 8)
What is necessary is to introduce it into at least a part of the channel forming region so that a short circuit occurs.

When the p-type impurity 13 is introduced after forming the data line 11, it can be introduced with low energy.

It is preferable to avoid areas where data lines 11 extend.

The P-type impurity 13 may be introduced after forming the gate electrode 6 or forming the interlayer insulating film 9 at the final stage of the II manufacturing process, but as shown in FIGS. It is introduced after forming the wire 11 and the like. Furthermore, the p-type impurity 13 may be introduced after forming a passivation film (not shown) over the data line 11 and the like.

The load MI in the flip-flop circuit of the SRAM
By setting S F E T Q P 2 to the depletion type threshold voltage, MISFETQp2
and Q n 2 drain region to high level, MI S
Since the drain regions of FETQP1 and Qnt can be fixed at low level, SRAM
The memory cell can be changed to a ROM memory cell in which information is written. Moreover, since the change can be easily made at the final stage of the 112 manufacturing process, it is possible to achieve a complete reduction in the length of the semiconductor integrated circuit device.

Furthermore, the present invention introduces the p-type impurity 13 after the step of forming the data line 11 and the like.

It is possible to further reduce the number of completions by one.

Furthermore, when the present invention has a RAM unit and a ROM unit, the p-type impurity 13 can be introduced in the same process as writing information in the ROM unit, so the manufacturing process can be reduced.

In addition, one aspect of the present invention is a driving MI in a flip-flop circuit.
SFETQd may be set to a depression type threshold voltage. In addition, the present invention provides one 0MO3 load MTSFETQf) in the flip-flop circuit.
, and the other 0MO8 driving MISFETQn may be set to a depression type threshold voltage. Furthermore, one aspect of the present invention is a MISFET in a flip-flop circuit.
may be set in advance to a depletion type threshold voltage, and then a predetermined MISFET may be set to an enhancement type threshold voltage.

The invention made by the present inventor has been specifically explained above based on the above embodiments, but the present invention is not limited to the above embodiments, and may be modified in various ways without departing from the gist thereof. Of course there is C.

For example, in the present invention, a flip-flop circuit of an SRAM memory cell may be configured with a driving MISFET and a high resistance load element made of a polycrystalline silicon film.

Furthermore, the present invention is not limited to microprocessors, but is applicable to S
It can be widely applied to semiconductor integrated circuit devices having RAM.

〔Effect of the invention〕

Among the inventions disclosed in this application, the effects that can be obtained by typical ones are briefly explained below.

In a semiconductor integrated circuit device having SRAM, SRA
M constituting a flip-flop circuit of M memory cells
By introducing impurities of a predetermined conductivity type into the channel formation region of the IS FET through the gate insulating film and setting at least one MISFET in this flip-flop circuit to a depression type threshold voltage, the final stage of the manufacturing process can be completed. By introducing impurities of a predetermined conductivity type, SRAM can be easily created.
Since the memory cells can be replaced with ROM memory cells, the semiconductor integrated circuit bag can be completely shortened by 1.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a microprocessor that is an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram of an SRAM memory cell mounted on the microprocessor shown in FIG. 1, and FIG. , second
FIG. 2 is a plan view of essential parts of the memory cell shown in the figure. Figure 4 is a sectional view taken along the TV-TV line in Figure 3;
The figure is a plan view of a main part in a predetermined manufacturing process of the memory cell shown in FIG. 3. In the figure, DL...data line, WL...word line, Q
s tQ P , Q n ・- M I S F E
T, 1-semiconductor substrate, 2... well region, 5...
- Gate insulating film, 6... Gate electrode, 7, 8... Semiconductor region, 11... Data line, connection wiring, reference voltage wiring, 12... Mask, 13... Impurity. . Figure 1 Figure 3 Wi Figure 4 Figure 5

Claims (1)

[Claims] 1. In a method for manufacturing a semiconductor integrated circuit device equipped with an SRAM in which a memory cell is configured by a flip-flop circuit including a MISFET, a channel formation region of a predetermined MISFET in a flip-flop circuit of the memory cell is provided. , introducing an impurity of a predetermined conductivity type through the gate electrode, setting at least one MISFET in the flip-flop circuit to a depletion type threshold voltage, and setting the other MISFETs to an enhancement type threshold voltage; A method for manufacturing a semiconductor integrated circuit device, characterized by: 2. The flip-flop circuit of the memory cell includes a load MISFET or a high resistance load element and a driving MISFET.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1, comprising: 3. The introduction of impurities of a predetermined conductivity type fixes the information in the SRAM memory cell and forms a ROM memory cell in which information is written. A method for manufacturing a semiconductor integrated circuit device according to paragraph 1. 4. The impurity of the predetermined conductivity type is introduced after forming the gate electrode of the MISFET and before or after forming the data line. A manufacturing method for each semiconductor integrated circuit device.