KR0161876B1 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents
Manufacturing method of nonvolatile semiconductor memory device Download PDFInfo
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- KR0161876B1 KR0161876B1 KR1019950025941A KR19950025941A KR0161876B1 KR 0161876 B1 KR0161876 B1 KR 0161876B1 KR 1019950025941 A KR1019950025941 A KR 1019950025941A KR 19950025941 A KR19950025941 A KR 19950025941A KR 0161876 B1 KR0161876 B1 KR 0161876B1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
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- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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Abstract
본 발명은 비휘발성 반도체 메모리소자의 제조방법에 관한 것으로, 공정이 용이하여 제조원가를 줄일 수 있고, 칩 크기를 줄일 수 있도록 한 것이다.The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, which is easy to process, thereby reducing manufacturing costs and reducing chip size.
본 발명은 제1도전형 반도체기판상에 산화막을 형성하는 공정과, 제1도전형 불순물이온을 주입하는 공정, 상기 산화막상에 게이트 형성을 위한 도전층을 형성하는 공정, 상기 도전층 및 산화막을 소정패턴으로 패터닝하여 게이트를 형성하는 공정, 기판 전면에 절연막을 형성하는 공정, 상기 절연막상에 금속막을 형성하는 공정, 건식식각에 의해 상기 금속막을 식각하여 상기 게이트 측면에 금속측벽을 형성하는 공정, 제2도전형을 이온주입하여 기판 소정영역에 소오스 및 드레인영역을 형성하는 공정, 기판 전면에 층간절연막을 형성하는 공정, 상기 층간절연막을 선택적으로 식각하여 상기 게이트와 소오스 및 드레인 영역을 노출시키는 콘택홀을 형성하는 공정, 상기 콘택홀을 통해 상기 게이트와 소오스 및 드레인영역에 각각 접속되는 전극을 형성하는 공정을 포함하는 비휘발성 반도체 메모리소자의 제조방법을 제공한다.The present invention provides a process of forming an oxide film on a first conductive semiconductor substrate, a process of implanting a first conductive impurity ion, a process of forming a conductive layer for forming a gate on the oxide film, the conductive layer and an oxide film. Forming a gate by patterning a predetermined pattern, forming an insulating film on the entire surface of the substrate, forming a metal film on the insulating film, etching the metal film by dry etching, and forming a metal side wall on the side of the gate; Forming a source and drain region in a predetermined region by ion implantation of a second conductivity type, forming an interlayer dielectric layer on the entire surface of the substrate, and selectively etching the interlayer dielectric layer to expose the gate, source and drain regions. Forming a hole, the electrode being connected to the gate, source and drain regions respectively through the contact hole It provides a method of producing the nonvolatile semiconductor memory device including the step of.
Description
제1도는 종래의 EPROM 단면구조도.1 is a cross-sectional view of a conventional EPROM.
제2도는 본 발명의 EPROM 제조방법을 도시한 공정순서도.2 is a process flowchart showing the EPROM manufacturing method of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체기판 22 : 산화막21 semiconductor substrate 22 oxide film
23 : 게이트 24 : CVD산화막23 gate 24 CVD oxide film
25 : 금속측벽 26 : 소오스 및 드레인영역25 metal side wall 26 source and drain regions
27 : 층간절연막 28 : 전극27 interlayer insulating film 28 electrode
본 발명은 비휘발성 반도체 메모리소자의 제조방법에 관한 것으로, 특히 공정이 용이하여 제조원가를 줄일 수 있고, 칩(chip) 크기를 줄일 수 있도록 한 비휘발성 반도체 메모리소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method of manufacturing a nonvolatile semiconductor memory device which can reduce manufacturing costs and reduce chip size.
EPROM(Electrically Programmable Read Only Memory) 제조시 플로팅 게이트(Floating gate)와 컨트롤 게이트(control gate)를 2층으로 한 적층구조를 형성하여 프로그램시 플로팅 게이트에 전자를 포획하여 채널 반전(channel inversion)에 필요한 문턱전압(VT)을 높이는 역할을 하고, 리드(read)시 바이어스 상태에서 전류 흐름을 센싱(sensing)하여 1, 0을 읽도록 되어 있다. 따라서 채널이 온(on)되려면 VT보다 높은 게이트전압이 필요하다. 이와 같은 메카니즘으로 전기적으로 데이터를 읽을 수 있도록 EPROM은 형성되어 있다.When manufacturing EPROM (Electrically Programmable Read Only Memory), a stacked structure consisting of two layers of floating gate and control gate is formed, which traps electrons in the floating gate during programming, which is necessary for channel inversion. It serves to increase the threshold voltage V T , and reads 1 and 0 by sensing current flow in a bias state during read. Therefore, the high gate voltage greater than V T is required to become the channel is turned on (on). The EPROM is formed so that data can be read electrically by such a mechanism.
종래의 EPROM소자를 제1도에 단면도로 나타내었다.A conventional EPROM device is shown in cross section in FIG.
종래의 EPROM소자는 도시된 바와 같이 반도체기판(1)상에 게이트절연막(10)을 개재하여 플로팅 게이트(11)와 층간산화막(12) 및 컨트롤게이트(13)가 차례로 적층되고, 상기 게이트 측면에는 산화막측벽(14)이 형성되고, 게이트 양단의 반도체기판 표면부위에는 n+소오스 및 드레인영역(15)이 형성되고, 상기 게이트와 소오스 및 드레인영역(15) 각각의 상부에 절연막(16)을 개재하여 금속배선(17)이 형성된 구조로 되어 있다.In the conventional EPROM device, the floating gate 11, the interlayer oxide film 12, and the control gate 13 are sequentially stacked on the semiconductor substrate 1 via the gate insulating film 10, and the gate side surface An oxide film side wall 14 is formed, n + source and drain regions 15 are formed on the surface of the semiconductor substrate at both ends of the gate, and an insulating film 16 is interposed between the gate and the source and drain regions 15, respectively. As a result, the metal wiring 17 is formed.
이와 같은 구조의 EPROM의 동작을 살펴 보면, 상기한 바와 같이 플로팅게이트(11)에 전자를 포획하기 위한 프로그램 전압을 인가하여(이때, 컨트롤게이트가 워드라인이 된다) 프로그램시 필요한 전압, 대개 10V이상의 고전압이 걸리게 되면 드레인과 소오스 바이어스하에서 소오스쪽에서 드레인으로 움직이는 전자가 플로팅 게이트에 선택적으로 충전(charge)되어 VT가 높아지게 된다. 이때, 선택적으로 프로그램전압을 인가함으로써 선택된 트랜지스터의 VT는 선택되지 않는 다른 트랜지스터보다 더 높아진다.Referring to the operation of the EPROM having such a structure, as described above, a program voltage for trapping electrons is applied to the floating gate 11 (in this case, the control gate becomes a word line), and a voltage required for programming, usually 10V or more. When a high voltage is caught under an electron source and a drain bias to the drain side of the moving source which can optionally be charged (charge) on the floating gate, the greater the V T. At this time, by selectively applying a program voltage, the V T of the selected transistor is higher than other transistors that are not selected.
통상 프로그램시 게이트에 약 12V이상의 고전압이 걸리는데, 정상적인 동작전압인 VD=VG=5V 인가시 전자가 포획된 상태의 트랜지스터는 전류가 흐르는데 필요한 VG전압 즉, VT가 낮기 때문에 전류를 흐르게 할 수 없다. 그러나 프로그램이 되지 않은 다른 트랜지스터는 정상적인 전류의 흐름이 이루어진다. 이를 센싱하여 1과 0로 데이터가 억세스되게 한다.Since normal program when the gate to greater than about 12V high voltage geolrineunde, the normal operating voltage of V D = V G = 5V of the electrons are trapping states when applied to the transistor that is V G voltage current flows required, V T is low, electric current Can not. However, other unprogrammed transistors have a normal current flow. This is sensed to allow data to be accessed with 1s and 0s.
상기한 구조의 종래의 EPROM소자를 구현하기 위해서는 게이트를 적층구조로 형성해야 하므로 공정단계가 많아지게 되어 제조비용이 많이 들게 되며, 플로팅게이트에 포획된 전자의 누설시 수율이 감소되는 문제점이 있다.In order to implement the conventional EPROM device having the above-described structure, since the gates must be formed in a stacked structure, many process steps are required and manufacturing costs are increased, and the yield of electrons trapped in the floating gate is reduced.
본 발명은 이와 같은 문제를 해결하기 위한 것으로, 공정을 단순화하고 칩의 크기를 줄일 수 있도록 한 비휘발성 반도체 메모리소자의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and an object thereof is to provide a method of manufacturing a nonvolatile semiconductor memory device, which can simplify the process and reduce the size of the chip.
상기 목적을 달성하기 위한 본 발명의 비휘발성 반도체 메모리소자 제조방법은 제1도전형 반도체기판상에 산화막을 형성하는 공정과, 제1도전형 불순물이온을 주입하는 공정, 상기 산화막상에 게이트 형성을 위한 도전층을 형성하는 공정, 상기 도전층 및 산화막을 소정패턴으로 패터닝하여 게이트를 형성하는 공정, 기판 전면에 절연막을 형성하는 공정, 상기 절연막상에 금속막을 형성하는 공정, 건식식각에 의해 상기 금속막을 식각하여 상기 게이트 측면에 금속측벽을 형성하는 공정, 제2도전형을 이온주입하여 기판 소정영역에 소오스 및 드레인영역을 형성하는 공정, 기판 전면에 층간절연막을 형성하는 공정, 상기 층간 절연막을 선택적으로 식각하여 상기 게이트와 소오스 및 드레인영역을 노출시키는 콘택홀을 형성하는 공정, 상기 콘택홀을 통해 상기 게이트와 소오스 및 드레인영역에 각각 접속되는 전극을 형성하는 공정을 포함하는 것을 특징으로 한다.The nonvolatile semiconductor memory device manufacturing method of the present invention for achieving the above object is a step of forming an oxide film on a first conductive semiconductor substrate, a step of implanting a first conductive type impurity ion, forming a gate on the oxide film Forming a conductive layer, forming a gate by patterning the conductive layer and the oxide film in a predetermined pattern, forming an insulating film on the entire surface of the substrate, forming a metal film on the insulating film, and forming the metal by dry etching. Etching the film to form a metal side wall on the side of the gate, implanting a second conductive type to form a source and drain region in a predetermined region of the substrate, forming an interlayer insulating film on the entire surface of the substrate, and selectively selecting the interlayer insulating film. Etching to form contact holes exposing the gate, source and drain regions, through the contact holes And forming electrodes connected to the gate, the source, and the drain regions, respectively.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제2도에 본 발명에 의한 EPROM소자의 제조방법을 공정순서에 따라 도시하였다.2 shows a method for manufacturing an EPROM device according to the present invention according to the process sequence.
먼저, 제2도(a)에 도시된 바와 같이 p형 반도체기판(21)에 LOCOS(Local Oxidation of Silicon)공정에 의해 소정영역에 필드산화막(20)을 형성한 후, 기판 전면에 850℃에서 습식산화(wet oxidation)에 의해 약 250Å 내지 500Å 정도 두께의 산화막(22)을 성장시킨다.First, as shown in FIG. 2A, a field oxide film 20 is formed in a predetermined region on a p-type semiconductor substrate 21 by a Local Oxidation of Silicon (LOCOS) process, and then at 850 ° C. on the entire surface of the substrate. By wet oxidation, an oxide film 22 having a thickness of about 250 Pa to 500 Pa is grown.
다음에 제2도(b)에 도시된 바와 같이 예컨대, BF2 +이온을 70KeV의 에너지로 5.2E12의 도우즈량으로 VT이온주입을 행한다.Next, a second example as shown in Figure (b), carried out in V T ion implantation dose of 5.2E12 the BF 2 + ion as energy of 70KeV.
이어서 제2도(c)에 도시된 바와 같이 기판 전면에 게이트 형성을 위한 제1도전층으로서, 620℃의 온도에서 약 4000Å두께의 폴리실리콘층(23)을 형성한다.Subsequently, as illustrated in FIG. 2C, a polysilicon layer 23 having a thickness of about 4000 kPa is formed at a temperature of 620 ° C. as a first conductive layer for gate formation on the entire surface of the substrate.
다음에 제2도(d)에 도시된 바와 같이 소정의 마스크를 이용한 사진식각공정을 통해 상기 폴리실리콘층(23)을 게이트패턴으로 패터닝한다. 이때, 과도식각(overetch)를 행하여 게이트 영역 이외의 상기 산화막(22)이 식각되도록 한다.Next, as illustrated in FIG. 2D, the polysilicon layer 23 is patterned into a gate pattern through a photolithography process using a predetermined mask. In this case, an overetch is performed to etch the oxide layer 22 other than the gate region.
게이트 형성후 AS +를 약하게 이온주입하여 게이트의 VT를 낮출 수도 있다.After the gate is formed it may be weakened by ion implantation to reduce the A + S gate of V T.
이어서 제2도(e)에 도시된 바와 같이 스텝커버리지(step coverage)가 우수한 CVD산화막(24)을 약 250Å두께로 얇게 기판 전면에 형성한다.Subsequently, as illustrated in FIG. 2E, a CVD oxide film 24 having excellent step coverage is formed on the entire surface of the substrate with a thickness of about 250 microns.
다음에 제2도(f)에 도시된 바와 같이 상기 CVD산화막(24) 상부에 금속층으로서, WSi2(25)를 약 4000Å두께로 증착한다. 이때, 상기 금속층으로서, TiW 또는 스텝커버리지가 우수한 MoSi2등을 사용할 수도 있다.Next, as shown in FIG. 2 (f), a WSi 2 25 is deposited to a thickness of about 4000 kPa as a metal layer on the CVD oxide film 24. At this time, TiW or MoSi 2 having excellent step coverage may be used as the metal layer.
이어서 제2도(g)에 도시된 바와 같이 건식식각에 의해 상기 WSi2를 식각하여 상기 게이트 측면에 WSi2측벽(25)을 형성한다.Subsequently, as illustrated in FIG. 2G, the WSi 2 is etched by dry etching to form the WSi 2 sidewall 25 on the side of the gate.
다음에 제2도(h)에 도시된 바와 같이 예컨대 AS +를 80KeV의 에너지로 4.5E15/㎠ 이온주입하여 N+소오스 및 드레인영역(26)을 기판 소정영역에 형성한다.Next, as shown in FIG. 2 (h), for example, A S + is implanted with 4.5E15 / cm 2 ion at an energy of 80 KeV to form an N + source and drain region 26 in the predetermined region of the substrate.
이어서 50:1 HF에서 세정공정을 행한 후,(100Å정도) 제2도(i)에 도시된 바와 같이 층간절연막으로서, BPSG(Borophospho-silicate glass)(27)한 다음, 이를 선택적으로 식각하여 상기 게이트(23)와 소오스 및 드레인영역(26)을 노출시키는 콘택홀을 형성한 후 그 전면에 금속을 스퍼터링에 의해 증착하고 이를 소정패턴으로 패터닝하여 상기 콘택홀을 통해 게이트와 소오스 및 드레인영역에 각각 접속되는 전극(28)을 형성한다.Subsequently, after the cleaning process was performed at 50: 1 HF (about 100 kPa), as shown in FIG. After forming a contact hole exposing the gate 23 and the source and drain regions 26, metal is deposited on the front surface by sputtering and patterned into a predetermined pattern to form a contact pattern in the gate, source and drain regions through the contact hole, respectively. The electrode 28 to be connected is formed.
이와 같이 제작되는 본 발명의 EPROM은 종래의 EPROM과 구조는 다르지만 그 동작원리는 유사하다.The EPROM of the present invention manufactured as described above is different in structure from the conventional EPROM, but its operation principle is similar.
먼저, 프로그램전압으로서, VG에 약 12V, VD에 5V, VS=VB=GND 바이어스하에서 프로그램이 이루어진다. 즉, VG=VPP의 고전압은 VD에 비해 훨씬 크다. 이때, 폴리실리콘 게이트(23) 측면에 형성된 금속 측벽(25)에 커패시터가 형성되며 이 측벽 하부에 극성이 생기며 실리콘기판 상부 채널 형성영역의 전자들이 금속 측벽으로 끌려 올라가면서 기판 표면의 저항이 커지게 된다. 이 저항은 채널이 온되기 위한 문턱전압을 크게 한다.First, as a program voltage, a program is performed under a bias of about 12 V for V G , 5 V for V D , and V S = V B = GND. In other words, the high voltage of V G = V PP is much larger than V D. At this time, a capacitor is formed on the metal sidewall 25 formed on the side of the polysilicon gate 23, and a polarity is formed below the sidewall, and the electrons of the upper channel forming region of the silicon substrate are attracted to the metal sidewall, thereby increasing the resistance of the substrate surface. do. This resistance increases the threshold voltage for the channel to turn on.
따라서 VG에 선택적으로 고전압을 가한 상태에서 리드 전압, 즉 VG=VD=5V, VD=0의 인가후의 VT는 프로그램되지 않은 트랜지스터에 비해 VT가 훨씬 커지게 된다. 이때의 전류량을 감지할 수 있도록 센싱회로를 구현함으로써 비휘발성 메모리소자를 제조할 수 있다.Therefore, the read voltage in the state of applying the high voltage selectively to V G, i.e. V G = V D = 5V, V T after application of the V D = 0 V T becomes a much higher compared to the non-programmed transistors. The nonvolatile memory device can be manufactured by implementing a sensing circuit to sense the current amount.
이상과 같이 본 발명은 폴리실리콘 게이트(23)와 WSi2(또는 TiW)측벽으로 EPROM 셀을 구현함으로써 공정을 단순화시킬 수 있다.As described above, the present invention can simplify the process by implementing the EPROM cell with the polysilicon gate 23 and the WSi 2 (or TiW) side wall.
또한, 종래의 2층구조의 게이트에서 꼭 필요했던 게이트 층간 절연막 형성시 양질의 절연막을 얻기 위해 1000℃이상의 고온에서 건식산화방법을 이용하여 얇은 두께의 산화막을 공정이 필요하였으나, 본 발명의 경우 이 공정이 필요없게 된다. 이에 따라 소자의 신뢰성을 향상시킬 수 있다.In addition, in order to obtain a high-quality insulating film when forming a gate interlayer insulating film, which is necessary for a conventional two-layered gate, a thin oxide film is required by using a dry oxidation method at a high temperature of 1000 ° C. or higher. No process is required. As a result, the reliability of the device can be improved.
또한, 필요에 따라서는 금속 측벽을 커패시터 전극으로 이용하여 커패시터를 구현하는 것도 가능하다.In addition, if necessary, the capacitor may be implemented using metal sidewalls as the capacitor electrode.
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