KR0162217B1 - Camera's sensitivity compensation device - Google Patents

Abstract

The present invention relates to a sensitivity compensation device of a camera which automatically compensates for a change in brightness of a screen by shortening an accumulation time in a charge control accumulation mode. In the present invention, when the signal generator generates a pulse signal of 1H period synchronized with the vertical synchronous signal, the integrator detects the erased amount of charge by integrating the CCD output signal. The signal of the integrator is stored in the storage device so that the output signal of the integrator is maintained for one field period, and the voltage control amplifier amplifies the CCD output signal according to the output voltage of the storage device and outputs an image signal whose sensitivity is compensated for. Therefore, the change of the brightness of the screen can be compensated in a wide range, the photographing convenience can be achieved, and the reproducibility of the screen can be improved.

Description

Camera's sensitivity compensation device

1 is a block diagram of a conventional FIT-CCD.

2 is a timing diagram showing vertical driving pulses required for FIT-CCD driving.

3 is a timing diagram illustrating the signal accumulation mode of the FIT-CCD.

(a) is the case of frame accumulation mode and (b) is the case of field accumulation mode.

4 is a timing diagram showing a vertical drive pulse signal required for charge control accumulation driving of the FIT-CCD.

(a) is a case of A field, and (b) is a case of B field.

6 (a) to 6 (f) are timing diagrams showing input / output signals of each part of FIG.

* Explanation of symbols for main parts of the drawings

1 imaging unit 2 accumulation unit

3: Horizontal CCD 4: Photodiode

5,6: Vertical CCD 10: Driving signal generator

40: Integrator 50: Memory

60: voltage controlled amplifier 70: signal generator

The present invention relates to a camera using the FIT-CCD as an image pickup device, and in particular, to compensate for the change in the brightness of the screen due to the reduction of the accumulation time when driving the CCD according to the charge control accumulation method to reproduce the picture at the original brightness A sensitivity compensator for a camera is provided.

In general, an image pickup device of a camera uses a charge coupled device (CCD), but a FIT-CCD is often used for a camera that pursues high image quality such as broadcasting or business.

FIG. 1 shows a configuration diagram of a conventional FIT-CCD, and is mainly composed of a live section 1, an accumulation section 2, and a horizontal CCD 3. The imaging unit 1 includes a plurality of PN junction photodiodes 4 for photoelectric conversion of incident light, and a vertical CCD (VCCD; 5) for transferring charge generated in the photodiode 4 by four-phase driving. It consists of. The accumulator 2 is constituted of a vertical CCD 6 by the same number of four-phase driving as in the image capturing unit 1, and accumulates charges transferred from the image capturing unit 1 for a predetermined time. The horizontal CCD 3 is a kind of register. The horizontal CCD 3 sequentially outputs electric charges moved from the storage unit 2 by one line in accordance with the horizontal drive pulse signals H1 and H2. The drain portion 7 is provided on the upper portion of the imaging unit 1 to absorb and remove unnecessary signal charges.

When light is incident on the imaging unit 1 in the FIT-CCD configured as described above, the incident light is photoelectrically converted by the photodiode 4, and the charge generated in the photodiode 4 is moved to the vertical CCD 5 to periodically. Accumulate for a certain period of time. The charge accumulated in the imaging section 1 enters the vertical CCD 6 of the adjacent accumulation section 2, but at this time part of the charge generated at the substrate core and the charge generated by leakage of light also enter the vertical CCD 6 It exists.

Since these charges become part of the smear, the charge can be reduced to reduce the smear phenomenon unique to the CCD. After this charge removing operation, the signal charge of the photodiode 4 is transferred to the vertical CCD 5 and transferred to the accumulation unit 2 within a short time. The charges transferred to the accumulator 2 are moved one by one to the horizontal CCD 3 and are sequentially output. Such a structure can improve the degree of freedom of the electronic shutter control.

2 is a timing diagram showing a vertical drive pulse signal required for normal operation of the FIT-CCD. The pulse signals of FIG. 2 are supplied from a timing generator of the camera, and removal of unnecessary charges (smear charges) and frame transfer of signal charges are performed in the vertical blank period V-BLK. As shown in FIG. 2, when the transfer pulses VA1 to VA4, VB1 and VB2 are applied to the vertical CCDs 5 and 6 in the period T1, smear charges are applied to the drain portion 7 or the accumulation portion 2; By transmitting to the horizontal CCD (3) through the erasing is possible.

At this time, the transfer pulses VB1 to VB4 are also applied to the vertical CCD 6 of the accumulation unit 2 to transfer the dark current to the drain unit 7 or the horizontal CCD 3 to remove the charge. The transmission direction of the signal charge is determined by the phases of the vertical CCD drive pulses VA1 to VA4 and VB1 to VB4. Since the charge cancellation using the horizontal CCD 3 is the same as the normal signal transmission direction, the vertical CCDs of the imaging unit 1 and the accumulation unit 2 can be driven by pulse signals of the same phase, thereby simplifying the driving circuit. . Therefore, a method of transmitting smear charges to the horizontal CCD 3 is generally used.

After the erase operation of the smear charge in the T1 period, a pulse voltage higher than the signal transmission pulse signal is supplied during the T2 period to move the signal charge generated in the photodiode 4 to the vertical CCD 5. Charges transferred to the vertical CCD 5 are transmitted at high speed to the vertical CCD 6 of the accumulation unit 2 in the period T3. After the frame transmission is finished and the vertical blank period V-BLK has passed, the signal charges of the accumulator 2 are moved to the horizontal CCD 3 by one line, and the horizontal driving pulse signals H1 and H2 are applied to the horizontal CCD 3. When is supplied, the signal is output from the CCD.

Next, the types of the signal accumulation mode of the FIT-CCD, the operation and the advantages and disadvantages of each accumulation mode will be described. The FIT-CCD has a frame accumulation mode (high vertical resolution mode) and a fill accumulation mode (high sensitivity mode) according to the light accumulation period, and FIG. 3 shows the difference between the two accumulation modes.

In general, in the CCD, when the signal charge accumulated in the photodiode is moved to the vertical CCD, the odd-numbered photodiode and even-numbered photodiode in the vertical direction can be read out separately. For example, if the charge accumulated in the odd-numbered photodiode by the driving pulse VA1 during the period T2 of FIG. 2 is transferred in the vertical CCD, the signal charge of the even-numbered photodiode is transferred by the other driving pulse VA3. This separation process is very important for realizing the frame accumulation mode and the field accumulation mode in the CCD.

3 is a timing diagram for explaining the signal accumulation mode of the FIT-CCD, where (a) is the frame accumulation mode and (b) is the field accumulation mode. In the frame accumulation mode, as shown in (a) of FIG. 3, first, the signal charges of the photodiodes in the vertical direction are filtered out one by one in the field A and read independently. The signal charges of the remaining photodiodes are then read in field B. In the field accumulation mode, as shown in (b) of FIG. 3, signal charges of two photodiodes adjacent in the vertical direction at the time of signal output in the A and B fields are added and read out.

Comparing the characteristic difference between the two accumulation modes, the frame accumulation mode has a merit that high resolution is obtained because the signal charges of the photodiodes are read out one by one. However, the signal accumulation time per photodiode is extended to one frame (two fields) period, and in particular, since the signal accumulation time of the vertical photodiode is shifted by one field period per one, there is a drawback that large afterimages occur.

The field accumulation mode reads by adding the signal charge in the vertical direction, so that the resolution is reduced by about 30% compared to the frame accumulation mode. However, since the signal accumulation time is shortened to one field period and the signal charges of all the photodiodes can be read out simultaneously, the afterimage is reduced.

An accumulation method to compensate for the disadvantages caused by the accumulation mode is a charge controlled frame accumulation drive. The charge control accumulation method reduces the afterimage by shortening the accumulation time of the photodiode to the field period, and takes into account that the afterimage is increased in the frame accumulation mode by increasing the accumulation time to the frame period. In this case, the signal is read once before and after the signal output of the photodiode, and the charge is erased by transferring the charge to the drain portion or the horizontal CCD as in the case of removing the smear charge. However, the charge control accumulation method has a disadvantage in that the sensitivity decreases ½ times as the accumulation time of the photodiode is shortened to ½.

The accumulation time of the frame accumulation mode is twice the accumulation time of the field accumulation mode. In the field accumulation mode, however, the charges of the two photodiodes are combined to form one pixel. In the frame accumulation mode, the accumulation time is long, while the charge of one photodiode becomes one pixel.

4 is a timing diagram showing a vertical drive pulse signal required for charge control accumulation driving of the FIT-CCD. These pulse signals are driving pulses supplied to the vertical CCDs in the A and B fields of the charge control accumulation mode, and signals other than the driving pulses VA3 and VA1 shown in FIG. See also).

In order to obtain the signal of the field B, a driving pulse as shown in FIG. Next, the signal charge is transferred from the even photodiode for the period T2 (b). In order to obtain the signal of the A field, a driving pulse as shown in Fig. 4A is supplied. That is, before the T1 period, the charge of the even-numbered photodiode is transferred to the vertical CCD (a), and the charge is wiped out in the T1 period, and then the signal charge is transferred from the odd-numbered photodiode (b) during the T2 period.

As described above, in the FIT-CCD, the timing of reading out the signal charge from the photodiode can be adjusted, and the electron shatter can be realized by removing the charge as in the smear charge removal method. In this case, the sensitivity falls in proportion to the shatter speed. The change in the sensitivity is a change in brightness of the screen, so compensation is required to reproduce the screen correctly. In the related art, the brightness of the screen is compensated by manually opening the iris installed in the optical path of the camera to open the original brightness.

However, according to the related art, there is a problem that the compensation of the brightness of the aperture completely impossible is impossible, and the aperture also serves to adjust the depth of the screen, thereby limiting the adjustment of the aperture for brightness compensation. In addition, the user manually adjusts the aperture while watching the screen to compensate for the original brightness, there was a problem in that it is inconvenient to use.

SUMMARY OF THE INVENTION The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to compensate for the change in the brightness of the screen due to the reduction of accumulation time when driving the FIT-CCD according to the charge control accumulation method. It is to provide a camera's sensitivity compensation device to reproduce the picture.

Another object of the present invention is to provide a sensitivity compensation device of a camera that can compensate for the change in the brightness of the screen by changing the accumulation mode of light extensively to improve the reproducibility of the screen and to make the compensation automatically, so as to facilitate the shooting. It is.

The sensitivity compensation device of the present invention for achieving the above objects is provided with a signal generator for generating a pulse signal of the 1H period synchronized with the vertical synchronization signal using the output signal of the drive signal generator. The output signal of the signal generator is input to the integrator and the memory, respectively, to control the integral timing and the operation of the memory. The integrator integrates the CCD output signal output from the preprocessor to detect the erased charge amount, and the memory device stores the integrated signal so that the output signal of the integrator is maintained for one field period. The voltage control amplifier connected to the output terminal of the preprocessor amplifies the CCD output signal according to the output voltage of the memory device and outputs an image signal whose sensitivity is compensated.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 and 6.

5 is a block diagram showing a sensitivity compensation device of the camera according to the present invention. In FIG. 5, the driving signal generator 10 and the pre-processor 30 are some blocks belonging to the CCD peripheral device of the conventional camera. The driving signal generator 10 generates a driving pulse signal to drive the CCD 20 and outputs vertical and horizontal reference timing signals necessary for signal processing of the camera. In general, the driving signal generator 10 is referred to as a timing generator in the camera. The preprocessor 30 connected to the output terminal of the CCD 20 performs various signal processing (CDS, CLAMP, BLANK, etc.) to remove noise included in the output signal of the CCD 20 and output a stable signal s2.

The sensitivity compensator of the present invention includes an integrator 40 connected to an output terminal of the preprocessor 30 to detect an erased charge amount by integrating the signal s2 output first in the horizontal CCD. The output signal of the integrator 40 is input to and stored in the storage device 50, and the storage device 50 allows the output signal of the integrator 40 to be maintained over one field period. The voltage control amplifier 60 connected to the output terminal of the preprocessor 30 amplifies the CCD output signal s2 according to the output voltage s4 of the memory device 50 and outputs an image signal whose sensitivity (screen brightness) is compensated for. do.

On the other hand, the signal generator 70 connected to the output terminal of the drive signal generator 10 generates the pulse signal s3 of the 1H period synchronized with the vertical synchronous signal using the input signal s1. The output signal s3 of the signal generator 70 is applied to the integrator 40 to control the integral timing, and is also applied to the memory device 50 to control its operation.

The basic operation of the sensitivity compensation device configured as described above is to detect the amount of charge erased in the charge erasing operation and amplify the signal by the erased amount. In the charge control mode, which produces excellent images with vertical resolution and afterimage, the brightness of the screen is lowered because it removes the charge accumulated in the field period. The present invention relates to a case in which the charge of a photodiode is transferred to a horizontal CCD in a FIT-CCD to remove the charge. The charge that enters the horizontal CCD is output by supplying the horizontal driving pulse signals H1 and H2. However, if the driving pulse is not supplied to the horizontal CCD when the charge of the accumulation portion is lowered, the charge is accumulated in the horizontal CCD.

FIG. 6 is a timing diagram showing the respective input and output force waveforms of FIG. 5, and (a) to (d) of FIG. 6 are horizontal driving pulse signals VA3 and VA1 and horizontal driving required for charge control accumulation driving of the FIT-CCD. The pulse signals H1 and H2 are shown. When the driving signal generator 10 supplies the driving pulses VA3 and VA1 to the vertical CCD, the charge of the photodiode is transferred to the vertical CCD at time a, and the vertical CCD transfers the charge to the accumulation part for the period T1. At the point b, the charge of the photodiode is transferred to the vertical CCD once more, and during the period T2, when the charge in the accumulator is transferred to the horizontal CCD, the charge read at the point b comes to the accumulator.

The drive signal generator 10 does not supply the drive pulses H1 and H2 to the horizontal CCD while the CCD 20 operates as described above by the vertical drive pulse signals VA3 and VA1. Charges accumulate in the horizontal CCD. When the driving signal generator 10 supplies the driving pulses H1 and H2 as shown in FIG. 6 (c) (d), the charge accumulated in the horizontal CCD is output to the outside of the CCD 20.

Therefore, the output signal to the CCD 20 outputted by the horizontal drive pulse signals H1 and H2 supplied for the first time after the T2 period is a signal to be erased, and when the signal is integrated, the amount of charge to be erased can be known. The integrator 40 connected to the CCD 20 via the preprocessor 30 is for the above integration operation, and the signal generator 70 generates a high potential signal s3 as shown in FIG. 6 (f). Only when outputting, the input signal s2 (see (e) of FIG. 6) is integrated.

The output signal s3 of the signal generator 70 is a pulse signal of the 1H period synchronized with the vertical synchronization signal, and is always generated when the horizontal driving pulse is first supplied after the T2 period. Since the time point of the generation of the signal s3 is fixed, the delay circuit of the signal generator 70 and the multivibrator use the signal having the same period as the vertical synchronization signal or the vertical synchronization signal of the drive signal generator 10. Since most drive signal generators 10 have a signal indicating a timing at which the horizontal drive pulses are supplied, the signal generator 70 may generate a control signal s3 using the signal directly.

The memory device 50 connected to the output terminal of the integrator 40 stores the integrated signal at the time when the integration operation ends (the time at which the s3 signal changes from the high potential to the low potential). Thus, the output signal of the integrator 40 is supplied as the control voltage s4 of the voltage control amplifier 60 for one field period. The voltage control amplifier 60 amplifies the signal s2 output from the preprocessor 30 according to the control voltage s4, and the image signal output from the voltage control amplifier 60 is large in proportion to the erased amount of charge. As a result, it is possible to compensate for the change in brightness of the screen due to the charge elimination.

As described above, the present invention detects the erased charge amount when driving the CCD according to the charge control accumulation method and amplifies the signal as much as it is erased, thereby making it possible to widely compensate for the change in screen brightness due to the reduction of the accumulation time. In addition, since the sensitivity (screen brightness) is automatically compensated for by the change of the light accumulation mode, the photographing can be conveniently performed, and the picture can be reproduced at the original brightness, thereby improving the reproducibility of the screen.

Claims (4)

A FIT-CCD peripheral device which processes a picture signal output from a CCD by a drive pulse of a drive pulse generator and a reference timing signal by a preprocessor, wherein the output signal of the drive signal generator is used to generate a 1H period synchronized with a vertical synchronous signal. A signal generator for generating a pulse signal; An integrator for integrating the CCD output signal output from the preprocessor according to the output signal of the signal generator to detect the erased charge amount; A storage device for storing the integrated signal according to the output signal of the signal generator so that the output signal of the integrator is maintained for one field period; And a voltage control amplifier for amplifying the CCD output signal output from the preprocessor according to the output voltage of the storage device and outputting an image signal whose sensitivity is compensated for. The vertical blank period according to claim 1, wherein the signal generator generates a pulse signal generated by using a vertical synchronizing signal of a driving signal generator, a signal having the same period as a vertical synchronizing signal, or a signal indicating a time point at which a horizontal driving pulse is supplied. Sensitivity compensator for the camera, characterized in that the output to the integrator and memory when the horizontal drive pulse is supplied at the end of the first time. 3. The sensitivity compensation device of claim 2, wherein the integrator integrates the CCD output signal output by the horizontal driving pulse supplied for the first time at the end of the vertical blank period. The apparatus of claim 1, wherein an output signal of the voltage control amplifier is increased in proportion to an erased charge amount.