KR100190928B1 - Semiconductor chips from TAB products with reduced scribe line width - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip in which a width of a scribe line of a semiconductor chip is reduced in order to prevent a defect due to sagging of a tab lead during a manufacturing process of a tab product. By reducing the chip scribe line width through the chip size, even if the tab lead sags between the semiconductor chip and the tab film during internal lead bonding (ILB) of the tab product, and the tab lead sags in contact with the edge of the semiconductor chip, the chip size Since the contact between the tab lead and the chip edge does not occur, the chip defects can be prevented, and the productivity is improved by increasing the total number of individual semiconductor chips formed on the wafer, and the pattern of the total main chip pattern patterned on the mask is increased. As the number increases, the process of transferring the pattern of the mask onto the wafer is shortened.

Description

Semiconductor chips from TAB products with reduced scribe line width

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip of a tab (TAB) product having a reduced width of a scribe line, and more particularly, in order to prevent a defect due to sag of a tab lead during a manufacturing process of a tab product. The present invention relates to a semiconductor chip having a reduced scribe line width.

A tab (TAB; Tape Automated Bonding, hereinafter referred to as "TAB") is one of the electrical connection methods between a semiconductor chip and a printed circuit board, and is comparable to conventional wire bonding. That is, wire bonding is a method in which the pads of the chip and the leads of the lead frame are individually connected as metal wires through a lead frame, whereas the TAB is a pattern in which the leads are previously patterned. The film can be used to collectively bond the chip pad and the TAB leads (Gang Bonding).

The TAB method is used in various semiconductor products including thin film transistor (TFT) liquid crystal display (LCD) drivers.

1 is a perspective view illustrating a state in which a general tab lead and a semiconductor chip are internally bonded, and FIG. 2 is a cross-sectional view taken along a line 2-2 of FIG. 1.

Referring to FIGS. 1 and 2, a general TAB product is described. In the TAB product 10, a set of tab leads 14 are patterned on the tab film 12, and a center portion of the tab film 12 is formed on the tab film 12. Openings 17 are formed to allow electrical connection between the tab leads 14 and the semiconductor chip 20. Four or two windows 16 are formed around the opening 17, and the tab leads 14 extend across the window 16 to the inside of the opening 17.

Like the opening 17, the window 16 refers to a shape through which the tab film 12 penetrates, and the tab leads 14 are physically attached to an external substrate (not shown) such as a printed circuit board. It is a window for electrically bonding and connecting. The tab leads 14 extending into the opening 17 are referred to as inner leads, and the tab leads 14 crossing the window 16 are referred to as outer leads.

A plurality of sprocket holes 18 are formed at both sides of the tab film 12, so that the tab film 12 can be automatically supplied in the form of a reel. The tab film 12 is typically of a plastic resin type such as polyimide, and the tab lead 14 is of the same copper alloy type as a conventional lead frame.

The tab film 12 having the structure in which the tab lead 14 is patterned as described above is electrically connected to the semiconductor chip 20 through the opening 17. The semiconductor chip 20 has a plurality of chip pads 26 formed and arranged on an upper surface thereof, and bumps 28 are formed on the chip pads 26. The semiconductor chip 20 extends and is formed into the opening 17. The semiconductor chip 20 is positioned under the tab leads 14 which are present, i.e., the inner leads, and the inner leads and the bumps 28 are aligned and bonded simultaneously in the same manner as thermal compression. It is referred to as inner lead bonding (ILB).

The outer lead portion of the tab lead 14 is then physically and electrically bonded and connected through an outer substrate (not shown) and the window 16 in a similar manner. This is called outer lead bonding (OLB). 1 is a shape before the inner lead bonding is completed and the outer lead bonding is performed.

FIG. 3 is a cross-sectional view showing a defect caused by a sag phenomenon of a tab lead according to the prior art by expanding the portion A of FIG. 2.

1 to 3, in the tab product 10, the tab lead 14 extends between the semiconductor chip 20 and the tab film 12 to contact the edge of the semiconductor chip 20 during internal lead bonding. Done. That is, the tab lead portion between the opening 17 and the window 16, that is, the tab lead portion formed on the tab film 12, and the bump 28 are connected according to the amount of forming during internal lead bonding. The height difference of the tapped lead portion is generated. This phenomenon is called lead sagging phenomenon.

When the lead sag occurs, poor characteristics tend to occur when the semiconductor chip 20 is operated. The semiconductor chip 20 is divided into a main chip 22 portion and a chip scribe line 24 ′, and the chip scribe line 24 ′ is a pure silicon state and has a constant outer portion of the main chip 22. It is enclosed by the width | variety d ', and is extended and formed to the bottom surface of the said main chip 22 which is a ground area | region. Therefore, when the tab lead 14 and the chip scribe line 24 ′ come into contact with each other due to a lead sag phenomenon, when the semiconductor chip 10 operates, a voltage value of 0 V or more is generated from the bumps 28 formed on the chip pads 26. The output having the path is formed through the chip scribe line 24 'to the ground region, which causes a characteristic defect, which is not normal operation.

Accordingly, an object of the present invention is to provide a semiconductor chip having a reduced scribe line width that can prevent chip defects even if the tab lead does not cause contact between the tab lead and the chip edge even when the tab lead sag occurs.

1 is a perspective view illustrating a state in which a general tab lead and a semiconductor chip are internally lead bonded;

FIG. 2 is a cross-sectional view taken along the line 2-2 of FIG. 1. FIG.

FIG. 3 is a cross-sectional view showing a defect caused by a sag phenomenon of a tab lead according to the prior art by expanding the portion A of FIG. 2.

4 is a cross-sectional view of a portion of a semiconductor chip having reduced scribe line width according to an embodiment of the present invention.

FIG. 5 is a plan view illustrating a mask for fabricating semiconductor chips according to an example embodiment of the inventive concepts illustrated in FIG. 4.

FIG. 6 is an enlarged plan view illustrating a cut region in a wafer state by enlarging portion B of FIG. 5;

7A and 7B are partial plan views of an example of a semiconductor chip of the prior art and the present invention, comparing their sizes.

Explanation of symbols for the main parts of the drawings

10: Tab product 12: Tab film

14: TAB Lead 16: Window

17: opening 18: sprocket hole

20: semiconductor chip 22: main chip

24, 24 ': Chip Scribe Line

26: Chip Pad 28: Bump

30: Mask 32: Main Chip Pattern

34: Mask Scribe Line

40: Sawing area

In order to achieve the above object, there is provided a semiconductor device comprising: a main chip having semiconductor integrated circuit devices, metal wirings electrically connecting the devices with each other, and a chip pad which is an electrical connection path between the devices and an external substrate; And a chip scribe line which surrounds an outer portion of the main chip with a predetermined width and extends to a bottom surface of the main chip, wherein the chip scribe line has a width of 20 μm to 25 μm. do.

In addition, to achieve the above object, a plurality of main chip pattern having a pattern of semiconductor integrated circuit elements and a metal wiring pattern for electrically connecting the elements; And a mask scribe line for separating the main chip patterns into a predetermined width, wherein the mask scribe line has a width of 80 μm.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

4 is a cross-sectional view illustrating a portion of a semiconductor chip having a reduced scribe line width according to an embodiment of the present invention, and FIG. 5 is a plan view illustrating a mask for manufacturing the semiconductor chips according to the embodiment of the present invention shown in FIG. 4. 6 is an enlarged plan view illustrating a cut region in a wafer state by enlarging the portion B of FIG. 5, and FIGS. 7A and 7B are examples of a semiconductor chip of the prior art and the present invention, comparing their sizes. Partial top view.

4 to 7 and FIGS. 1 and 2, the semiconductor chip 20 of the present invention is largely divided into a main chip 22 part and a chip scribe line 24 like the conventional semiconductor chip described above. The main chip 22 is a portion in which semiconductor integrated circuit devices are formed, and includes an oxide film, a polycrystalline silicon layer, a metal wiring layer, an insulating film, and the like, and the chip scribe line 24 is a pure silicon state of the main chip 22. The outer shell portion is surrounded by a constant width d and extends to the bottom surface of the main chip 22. The chip scribe line 24 is also an area remaining after being separated by cutting means when cutting and separating chips in a wafer state into individual chips.

In an embodiment of the present invention, the chip scribe line width d is reduced. The method is made through the modification of the mask 30 to manufacture the semiconductor chip 20. In general, in the semiconductor chip 20 of the TFT LCD driver, three to seven main chips 32 are patterned per mask 30 as shown in FIG. 5. In addition, a mask scribe line 34 is formed to separate the main chip patterns 32 into a predetermined width w. Therefore, the semiconductor chip 20 of the present invention can be manufactured by reducing the width w of the mask scribe line in the mask 30 state.

The mask scribe line width w, which is generally used in the related art, is 170 mu m. This is reduced to 80 mu m in the present invention. The width w is also a limit value that can be reduced on the mask 30. However, the chip scribe line width d may vary depending on the width s of the cutting means. However, in consideration of the chip scribe line width d and the impact applied to the chip at the time of cutting, cutting means having a width s of 30 μm and 40 μm is used in the present invention.

When the width s of the cutting means is 30 m, when the mask scribe line width w is reduced from 170 m to 80 m, the chip scribe line width d is reduced from 70 m to 25 m. This can be confirmed in Equation 1 and FIG. 6.

When the width s of the cutting means is 40 mu m, when the mask scribe line width w decreases from 170 mu m to 80 mu m, the chip scribe line width d decreases from 65 mu m to 20 mu m.

This is summarized as follows.

Mask scribe line width (w) Chip scribe line width (d) When cutting means width s is 30 μm When 40㎛ Prior art 170 μm 70㎛ 65 μm The present invention 80㎛ 25 μm 20 ㎛

Therefore, according to the structure of the present invention, the chip scribe line, which is the outer portion of the semiconductor chip is reduced, the overall size of the chip is reduced, so that even if the tab lead sag occurs, no contact between the tab lead and the chip edge prevents chip defects. There is an advantage to this.

However, the same effect as the present embodiment may be obtained even if the position of the chip pad is moved to the outside of the chip without reducing the width of the chip scribe line as in the above-described embodiment. In other words, in the case of a conventional semiconductor chip in which the chip pad is formed at a depth of 30 μm from the edge of the main chip, reducing the distance to 10 μm may have the same effect as reducing the width of the chip scribe line by 20 μm in this embodiment. will be. However, even in that case, since the maximum reduction limit is only 30 μm, the effect may be inferior to the present embodiment.

In addition, according to the structure according to the present invention, not only the above advantages but also the effect that the total number of individual semiconductor chips formed on the wafer increases.

For example, based on a 6-inch wafer commonly used in a thin film transistor liquid crystal display driver (TFT LCD Driver), the cutting means width (s) is 30㎛.

When the size (a × b) of the main chip on the mask is 10005 μm × 1005 μm, when the mask scribe line width w decreases from 170 μm to 80 μm, the size of one individual chip manufactured and separated on the wafer ((a + 2d) × (b + 2d)) decreases from 10145 μm × 1145 μm to 10055 μm × 1055 μm, and the total number of individual chips increases from 1272 to 1399.

When the size (a × b) of the main chip on the mask is 9905 μm × 905 μm, if the mask scribe line width w is reduced from 170 μm to 80 μm, the size of one individual chip manufactured and separated on the wafer ((a + 2d) × (b + 2d)) is reduced from 10045 μm × 1045 μm to 9955 μm × 955 μm, and the total number of individual chips increases from 1415 to 1569.

This is summarized as follows.

Mask scribe width (w) When main chip size (a × b) is 10005 × 1005 When 9905 × 905 Chip size (a + 2d) × (b + 2d) Number of chips Chip size (a + 2d) × (b + 2d) Number of chips Prior art 170 10145 × 1145 1272 10045 × 1045 1415 The present invention 80 10055 × 1055 1399 9955 × 955 1569

In this manner, the total number of individual semiconductor chips formed on the wafer may be increased, as well as the total number of main chip patterns patterned on the mask. In other words, the number of main chip patterns per mask for up to seven masks can increase to eight, depending on the mask's acceptable range.

The advantages according to the structure of the present invention described above so far can be largely classified as follows.

Since the chip scribe line, which is an outer portion of the semiconductor chip, is reduced to reduce the overall size of the chip, even if the tab lead sag occurs, contact between the tab lead and the chip edge does not occur, thereby preventing chip defects.

Productivity is improved by increasing the total number of individual semiconductor chips formed on the wafer.

By increasing the total number of main chip patterns patterned on the mask, the process of transferring the pattern of the mask onto the wafer is shortened.

Claims (6)

A main chip having semiconductor integrated circuit devices, metal wirings electrically connecting the devices with each other, and a chip pad which is an electrical connection path between the devices and an external substrate; A chip scribe line which surrounds an outer portion of the main chip with a predetermined width and extends to a bottom surface of the main chip; Including; The semiconductor chip, characterized in that the width of the chip scribe line is 20㎛ 25㎛. The semiconductor chip of claim 1, wherein bumps are formed on a chip pad of the main chip. The semiconductor chip according to claim 2, wherein the bump and the external substrate are electrically connected by a tab method. The semiconductor chip according to claim 1, wherein said semiconductor chip is used for a thin film transistor liquid crystal display driver. A plurality of main chip patterns having a pattern of semiconductor integrated circuit elements and a metal wiring pattern electrically connecting the elements to each other; A mask scribe line separating the main chip patterns into a predetermined width; Including; A mask for manufacturing a semiconductor chip, wherein the width of the mask scribe line is 80 µm. The mask for manufacturing a semiconductor chip according to claim 5, wherein the mask is a mask used for manufacturing a semiconductor chip used in a thin film transistor liquid crystal display driver.