KR100206937B1 - Data Synchronization Device and Method - Google Patents

Abstract

The present invention relates to an apparatus and method for data synchronization. In the conventional apparatus and method for data synchronization, the video decoder must compare the byte count value stored in the first-in, first-out unit every time the image data is stored. The host processor and the video decoder must be equipped with a counter for byte counting the image data, which causes the device to be loaded during byte counting, thereby increasing the capacity of the device such as gate count, chip size, current and amount of power. There was a problem.

The present invention was devised to solve the above-mentioned conventional problems. The present invention provides a header after all image data and audio data coming from a host processor and stores the header information so that the header information can be used to decode the image data. It is a simple device to synchronize the video data and audio data so that the display value and the information value indicating the transmission time of the audio data can be accurately known. This eliminates the need for a counter to count bytes in the host processor. In addition to lowering the processor load, performance gains can be achieved, as well as reduced gate count, resulting in reduced power and size.

In addition, like the host processor, the video decoder and the audio decoder can eliminate the counter for byte counting and the circular buffer to store the PTS, and also eliminate the need for a comparator to reduce power consumption and to synchronize video and audio while increasing the density. There is an effect that can be achieved.

Description

Data Synchronization Device and Method

The present invention relates to an apparatus and a method for synchronizing data, and in particular, by storing a header after all image data and audio data coming from a host processor so that the information of the header can be used for decoding, the display time of the image data during decoding. And a data synchronizing apparatus and method for precisely knowing an information value indicating a transmission point of audio data so as to be suitable for synchronizing video data and audio data with a simpler apparatus.

In the conventional data synchronizing apparatus, as shown in FIG. 1, an image data, an information PTS value indicating a display time of image data, and a bit stream BS are encoded and input through an encoder (not shown). After extracting the system clock signal SCR value, the byte counting value BC1 of the extracted video data VD is obtained, and the extracted video data VD is stored in the first data storage unit 10. The host processor 20 and the image data VD stored in the first data storage unit 10 are retrieved and stored in the second data storage unit 30, and the stored image data is retrieved and decoded and byte counted. After the BC2 is obtained, the information counting value (PTS), the system clock signal (SCR) value, and the byte counting value indicating the display count value BC2 and the display time of the image data extracted by the host processor 20 ( The second by BC1) And a video decoder 40 for controlling the decoding speed of the video data drawn out from the data storage unit 30 and outputting the decoded video data (DVD) according to the controlled decoding speed.

The host processor 20 includes a counter 2 that counts the video data extracted from the encoded bitstream BS and obtains the byte counting value BC1.

The video decoder 40 includes a first-in, first-out unit 4 that first-in-first-outs the byte counting value BC1 obtained from the counter 2 of the host processor 20 and the information PTS value indicating the display time of the image data. And a counter 14 for byte counting the image data drawn out from the second data storage unit 30 to obtain the byte counting value BC2.

As shown in FIG. 4, in the conventional data synchronization method, an information PTS value, a system clock signal SCR value, and image data indicating a display time of image data in a bit stream BS input S1 are respectively. After extraction (S2), the byte counting value BC1 of the extracted image data (S2) is obtained (S3), and the extracted image data (S2) is stored in the first data storage unit 10 (S3). The first step, the PTS value extracted in the first step (S2), BC1 is stored in the first-in first-out part 40 (S4), and the SCR value is stored in the memory of the video decoder 40 (not shown). After the storage (S4) in the second process, the second process of retrieving the image data stored in the first process (S3) to be stored in the second data storage unit (S5), and stored in the second process (S5) ) Extracts and decodes the image data, obtains a byte counting value BC2 (S6), and calculates the obtained byte counting value BC2 and the second process. A third step of comparing the length S4 of the byte counting value BC1 is the same (S7), and if the result of the comparison (S7) in the third step is BC1 = BC2, the third step is repeated, and BC1 = BC2, the fourth step of comparing (S8) whether the PTS value stored in the second step (S4) and the SCR value is the same; and the result of the comparison (S8) of the fourth step (P8), if the PTS value = SCR value, the PTS. Outputting decoded video data having a value (S9), and comparing the PTS value to a value less than or equal to an SCR value (S10) and (S12) if the PTS value is not an SCR value; If the PTS value is smaller than the SCR value as a result of comparison (S10) (S12), the video data to be decoded is skipped without decoding (S11). If the PTS value is larger than the SCR value, the displayed image data is redisplayed (S13). The process takes place.

The operation of the conventional data synchronization device configured as described above will be described in detail with reference to FIGS. 2 to 4 as follows.

First, a bit stream BS encoded through an encoder (not shown) is input to the host processor 20 (S1).

Here, the general bit stream includes image data, audio data, information indicating the display time of the video data (hereinafter, abbreviated as PTS), information values indicating the time of transmission of the audio data, and a system clock signal (System Clock). Reference siginal: hereinafter referred to as SCR) value and the like.

By the way, in the bit stream BS shown in FIG. 2, only the PTS and the image data are displayed for ease of explanation.

As such, when the bit stream BS illustrated in FIG. 2 is input to the host processor 20 (S1), the host processor 20 generates a PTS value, an SCR value, and an image from the input bit stream BS. Data VD is extracted respectively (S2).

For example, when the PTS value PTS1, the image data VD1, and the SCR value (not shown) included in the bit stream BS shown in FIG. 2 are input to the host processor 20 (S1), the host As described above, the processor 20 extracts the PTS value PTS1, the image data VD1, and the SCR value from the input bit stream BS (S2).

Thereafter, the counter 2 of the host processor 20 performs byte counting on the extracted image data VD1 to obtain its byte counting value BC1, that is, k1 bytes shown in FIG. 2 (S3). ). In addition, the host processor 20 stores the extracted image data VD1 in the first data storage unit 10 (S3).

Then, the video decoder 40 selects the PTS value PTS1 and the byte counting value BC1, which are extracted (S2) by the host processor 20, as shown in FIG. ) And the video decoder 40 also stores the system clock signal (SCR) value extracted by the host processor 20 (S2) in an internal memory (not shown) (S4). .

The video decoder 40 extracts the image data VD1 stored in the first data storage unit 10 and stores the image data VD1 in the second data storage unit 30 (S5).

Here, as shown in FIG. 3, the first-in, first-out part 3 is a 32-bit memory, and the PTS value is stored in 33 bits, so that the byte counting value k1 and the most significant bit of the PTS value are one word (32 bits). ), And the PTS value is stored in the next word (32 bits).

The SCR value stored in the memory of the video decoder 40 is increased by 1 every 90 KHz by the video decoder 40.

Thereafter, the video decoder 40 extracts and decodes the image data VD1 stored in the second data storage 30, and the counter 14 of the video decoder 40 decodes the extracted image data VD1. ) Is counted by byte, and the byte counting value BC2 and k1 bytes are obtained (S6).

The comparator 24 of the video decoder 30 stores the byte counting value BC1, k1 byte, and the byte counting value BC2 and k1 byte obtained in the step S6. The comparison is the same (S7).

If the result of the comparison (S7) is not BC1 = BC2, the video decoder 40 repeats the steps S6 and S7.

However, in this case, since BC1 = BC2, that is, k1 = k1, the image data VD1 decoded by the video decoder 40 has the PTS value PTS1 stored in the first-in, first-out part 4.

At this time, the comparator in the video decoder 40 compares the PTS value when the result of the comparison (S7) coincides with the SCR value stored in the memory of the video decoder 40 in the step S4 (S8). .

As a result of the comparison (S8), if the PTS value = SCR value, decoded video data (DVD) having the PTS value is output and displayed on the display device (not shown).

On the other hand, if the result of the comparison (S8) is not a PTS value = SCR value, the comparator compares whether the PTS value is smaller or larger than the SCR value (S10) (S12).

If the PTS value is smaller than the SCR value as a result of the comparison (S10) or (S12), the video decoder 40 is not the image data to be displayed at present, but the image data displayed in the past, so that the video decoder 40 determines the PTS. After skipping without decoding the image data having a value (S11), the step (S10), (S11) is repeated until the PTS value = SCR value.

On the other hand, if the comparison (S10) and (S12) result in the PTS value larger than the SCR value, the video decoder 40 does not match the PTS value and the SCR value since the image data having the PTS value is not yet to be displayed. Decoding is stopped until (S13) and the video data VDO stored in the second data storage unit 300 is output.

In this way, the image data output from the video decoder 40 is displayed on a display device (not shown).

Here, the steps S12 and S13 are repeatedly performed until the PTS value = SCR value.

The voice data included in the bit stream is also compared with the SCR value by comparing the information value indicating the time point at which the voice data is transmitted by the host processor 20 and the audio decoder (not shown). The decoding speed of the audio data is controlled accordingly, so that the video data and the audio data in the bit stream are synchronized with each other and output to the display device (not shown), the speaker (not shown), or the like.

Meanwhile, as described above, since the image data VD1 is displayed and then encoded and input to the host processor 20, the image data VD2 is also displayed on the display apparatus in the same manner as described above, and thus a detailed description thereof will be omitted. .

However, in the conventional data synchronizing apparatus and method, the video decoder has to compare with the byte count value stored in the first-in, first-out unit every time the image data stored in the second data storage unit is fetched. .

In addition, since the host processor and the video decoder must have a counter for byte counting the image data, the device loads when the byte counts and the device capacity such as gate count, chip size, current, and power amount accordingly. There was an increasing problem.

The present invention was devised to solve the above-mentioned conventional problem, and the header information is stored after all the video data and audio data coming from the host processor, so that the information of the header can be used to decode the video. It is an object of the present invention to provide an apparatus and method for synchronizing data so that an information value indicating a data display time and a voice data transmission time can be accurately known.

1 is a block diagram of a conventional data synchronization device.

2 is a schematic representation of a general bit stream.

3 is a detailed configuration diagram of the first-in first-out part in FIG.

4 is a control flowchart of a conventional data synchronization method.

5 is a block diagram of a data synchronization device of the present invention.

6 is a block diagram of a memory map of FIG.

7 is a control flowchart of the data synchronization method of the present invention.

* Explanation of symbols for main parts of the drawings

100: host processor 200: first data storage

300: video decoder 310: first register

400: second data storage unit 410 ~ 430: header

The data synchronization method of the present invention for achieving the above object, the system clock signal and the information value indicating the video data, audio data, the display time of the video data and the transmission time of the audio data in the encoded (S1) bitstream A first step of extracting values (S2) and storing the extracted image data and audio data in the first and second data storage units (S2), respectively; and the image data extracted in the first process (S2). A second process of storing (S3) information values indicating a display time point and a time point of transmission of the audio data in the first and second registers; and image information and audio stored in the first and second data storage units in the first process, respectively. A third process of extracting the information and storing it in the third and fourth data storage units (S4); and extracting the video data and the audio data stored in the third and fourth data storage units in the third process, respectively. The fourth step of decoding (S5), comparing the head information in the decoded video data (S6), and comparing the head information in the decoded audio data (S6); If the data to be decoded as a result of the comparison does not contain information of the head, the fourth process is repeated (S5) (S6). A fifth process of controlling the decoding speed (S7) is performed.

The data synchronization apparatus according to the present invention for implementing the above method extracts the video data, the audio data, the information value indicating the display time of the video data and the transmission time of the audio data and the system clock signal from the encoded bitstream. A host processor for storing the extracted image data in the first and second data storage units, and a video data value of the third data storage unit indicating an area in which the extracted image data is to be stored and information of the inserted header. A video decoder for controlling the decoding speed of the extracted video data, and a decoding speed of the extracted audio data by the voice data value of the fourth data storage unit indicating an area in which the extracted audio data is to be stored and the information of the inserted header. It consists of an audio decoder to control it.

The video decoder and the audio decoder include first and second registers for storing information values indicating the display time point of the image data and the transmission point point of the audio data.

This operation of the present invention will be described in more detail with reference to FIG. 6 as follows.

First, when the encoded bitstream BS is input to the host processor 100, the host processor 100 extracts a PTS value, an SCR value, and image data from the input bitstream BS, respectively. In operation S2, the extracted image data is stored in the first data storage unit 200 (S2).

Then, the video decoder 300 stores the PTS1 value extracted from the host processor 100 (S2) in the first register 310 (S3) and stores the SCR value in an internal memory (not shown) (S3). Let's do it.

Thereafter, the video decoder 300 extracts the image data stored in the first data storage unit 200 (S2) and stores the image data in the second data storage unit 400 (S4), wherein the image data is stored in the first data. The storage unit 200 stores the data (S4) and then attaches the header to the storage (S4).

That is, after storing the image data (k0 byte) in the second data storage unit 400 (S4), the specific header 410 is stored after the image data (k0 byte) (S4), and the next PTS value is stored. The first register 310 is stored (S4) and the image data (k1 byte) is stored in the second data storage unit 400 (S4), and the header 420 is stored after the image data (k1 byte). (S4)

Thereafter, the video decoder 300 extracts the data stored in the second data storage 400 (S4) and decodes the data (S5). After reading and decoding the image data (k0 bytes), the lead point increases. When the header is met and decoded (S6), the PTS value of the first register 310 indicated by the header 410 is assigned to the restored image data (k0 bytes).

At this time, the decoding of the header 410 may be implemented in a micro program format or hardware.

Similarly, the PTS values corresponding to the image data k1 and k2 may be provided using the headers 420 and 430.

In this way, the PTS value is assigned to the decoded video data, and then the decoding rate is controlled by comparing the PTS value with the SCR value in the same manner as in the prior art (S7).

In addition, as described above by the host processor 100 and the audio decoder (not shown), the information value PTS indicating the time point at which the voice data is transmitted is compared with the SCR value. Since the decoding speed is controlled according to the comparison result, the video data and the audio data included in the bit stream BS are synchronized with each other and output to the display device (not shown), the speaker (not shown), or the like.

Meanwhile, another embodiment of the present invention will be described.

The first and second registers storing the PTS values may be configured as circular buffers to store PTS values of video data and audio data. The circular buffer does not need to store byte count values.

In addition, a header code that is not reserved may be used as a format of the header used as the address of the first register or the circular buffer. The decoding of the header attached to the video data and the audio data may be implemented in a micro program format or hardware. .

In addition, a method of inserting a specific header after the encoded video data and audio data may have the same effect by inserting a specific header between reserved headers in front of the data.

As described above, the present invention eliminates the need for a counter to count bytes in the host processor, thereby reducing the load on the host processor, thereby improving performance, and reducing power and size by reducing the gate count. It works.

In addition, like the host processor, the video decoder and the audio decoder can eliminate the byte count counter and the circular buffer to store the PTS, and also eliminate the need for the comparator to reduce power consumption and to synchronize the video and audio while increasing the density. There is an effect that can be achieved.

Claims (5)

The first and second data storage units extract extracted image data, system clock signals, and information values representing the image data, the audio data, the display time of the image data, and the transmission time of the audio data, respectively, from the encoded bitstream. A host processor configured to respectively store a video processor, a video decoder configured to control a decoding speed of the extracted video data by information of an inserted header and an image data value of a third data storage unit indicating an area in which the extracted image data is to be stored; And an audio decoder for controlling the decoding speed of the extracted voice data by the voice data value of the fourth data storage unit indicating the area where the extracted voice data is to be stored and the information of the inserted header. Device. The data synchronization device as set forth in claim 1, wherein the specific header inserted after the data stored in the third and fourth data storage units is sandwiched between reversed headers before the data. The data synchronization device of claim 1, wherein the video decoder comprises a circular buffer for storing a PTS value without counting bytes. The data synchronization device of claim 1, wherein the audio decoder comprises a circular buffer which stores a PTS value without counting bytes. In the encoded and input bitstream, information data and system clock signal values indicating video data, audio data, display time of audio data and transmission time of audio data are respectively transmitted, and the extracted video data and audio data are first and second. A second process of storing the first and second registers in the first and second registers; A third process of extracting image information and audio information stored in the first and second data storage units in the first process, and storing the image information and audio information in the third and fourth data storage units; and the third and fourth processes in the third process. The video data and audio data stored in the data storage unit are extracted and decoded, and the head data is compared with the decoded video data. The fourth step of comparing the head data in the voice data and repeats the fourth step if there is no head information in the data decoded as a result of the comparison in the fourth step, and the data decoded as a result of the comparison And a fifth step of controlling the decoding speed of the video data and the audio data in the fourth step if the head information is present.