KR100200806B1 - Time base correction circuit - Google Patents

Abstract

The time base compensation circuit is a feed forward method using automatic phase control and automatic frequency control without using a memory and a phase locked loop. An analog / digital converter for converting a video signal to be reproduced into a digital signal for this purpose; An automatic frequency controller for automatically controlling the frequency of the reproduced video signal by delaying the digital signal output from the analog / digital converter to a predetermined phase and selecting and outputting a signal having a corresponding delay value; Clock generating means for generating a clock signal having a predetermined period; Delaying the phase of the clock signal to the same phase as the predetermined phase by using the clock signal output from the clock generating means as an input signal and selecting and outputting a signal having a corresponding delay value to automatically control the phase of the reproduced video signal. Automatic phase controller; Synchronization separating means for separating the vertical and horizontal synchronization signals from the reproduced video signal; Pseudo-synchronization generating means for generating a pseudo horizontal synchronizing signal in synchronization with a clock signal outputted from the clock generating means and reset controlled by the vertical synchronizing signal output from the synchronizing separation means; Phase comparing means for comparing the phase of the horizontal synchronization signal output from the synchronization separating means and the pseudo horizontal synchronization signal output from the pseudo synchronization generating means; Control signal generating means for generating a control signal for controlling the driving of the automatic frequency controller and the automatic phase controller according to the signal output from the phase comparing means; Phase-controlled by the signal output from the autophase controller is configured to include a digital / analog converter for converting the output signal from the autofrequency controller into an analog signal.

Description

Time base compensation circuit

1 is a block diagram of a conventional time base compensation circuit.

2 is a block diagram of a time base compensation circuit according to the present invention.

3 is an embodiment incorporating FIG.

4A to 4C are waveform diagrams of a recording signal and a reproduction signal.

* Explanation of symbols for main parts of the drawings

10: A / D converter 30: D / A converter

40: synchronization separation means 70: clock generation means

80: pseudo-synchronization means 90: phase comparison means

100: control signal generating means 110: automatic frequency controller

120: automatic phase controller

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for compensating for time axis fluctuations in a video signal recording and reproducing apparatus, and more particularly to a time axis compensating circuit for compensating for time axis fluctuations (jitters) generated at high speed.

In general, the video signal recording and reproducing apparatus inevitably generates jitter when the recorded signal is reproduced precisely in synchronization. Accordingly, conventionally, jitter generated during regeneration is removed through a circuit as shown in FIG. That is, when the signal picked up from the playhead is amplified to a predetermined value and applied, the A / D converter 10 converts the signal into a digital signal. At this time, the reproduction signal including jitter applied to the A / D converter 10 is also applied to the synchronous separation means 40 to separate the horizontal synchronous signal and output it to the phase synchronous loop 50. At this time, the phase synchronization loop 50 is for generating the write clock signal WCLK of the memory 20 in synchronization with the period change of the horizontal synchronization signal applied from the synchronization separation means 40 due to the generation of jitter. A frequency corresponding to 1H (horizontal synchronization signal) always outputs a signal with a constant frequency regardless of the period change. This signal becomes a write clock signal WCLK, which is applied to the A / D converter 10 and the memory 20 to synchronize the A / D converted signal with the signal stored in the memory 20, in particular, the memory ( 20) to control the storage mode. Therefore, the signal stored in the memory 20 is in a state where the reproduction signal including jitter is stored as it is.

In order to remove jitter from the reproduction signal, the read clock generator 60 is operated such that the read clock signal RCLK for the information stored in the memory is constantly generated. Accordingly, the memory 20 reads the stored information at regular intervals and outputs a jitter-free reproduction signal, and the output signal is applied to the D / A converter 30 to be converted into an analog signal and output.

However, this feedback time-base compensation method has a problem in that it cannot keep up with high-speed jitter due to a large memory capacity and a circuit limitation of the phase-locked loop.

Accordingly, an object of the present invention is to provide a feed-forward time-base compensation circuit using an automatic phase control and an automatic frequency control method without using a memory and a phase locked loop in order to overcome the above problems.

In order to achieve the above object, the present invention provides a time-base compensation circuit for eliminating time-base shaking that is included in a video signal to be reproduced during playback control of an apparatus for recording and reproducing video and audio signals;

An analog / digital converter for converting the reproduced video signal into a digital signal;

An automatic frequency controller for automatically controlling the frequency of the reproduced video signal by delaying the digital signal output from the analog / digital converter to a predetermined phase and selecting and outputting a signal having a corresponding delay value;

Clock generating means for generating a clock signal having a predetermined period;

The clock signal output from the clock generating means is used as an input signal to delay the phase of the clock signal to the same phase as the predetermined phase, and to select and output a signal having a corresponding delay value to automatically output the phase of the reproduced video signal. An automatic phase controller for controlling;

Synchronization separating means for separating vertical and horizontal synchronization signals from the reproduced video signal;

Pseudo-synchronization generating means for generating a pseudo horizontal synchronizing signal in synchronization with a clock signal outputted from the clock generating means and reset controlled by the vertical synchronizing signal output from the synchronizing separating means; Phase comparing means for comparing phases of the horizontal synchronization signal output from the synchronization separating means and the pseudo horizontal synchronization signal output from the pseudo synchronization generating means; Control signal generating means for generating a control signal for controlling the driving of the automatic frequency controller and the automatic phase controller according to the signal output from the phase comparing means;

It is characterized in that it comprises a digital / analog converter for phase-controlled by the signal output from the automatic phase controller to convert the output signal from the automatic frequency controller into an analog signal.

Next, the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a time-base compensation circuit according to the present invention, which includes a synchronization separating means 40 for separating and outputting a horizontal synchronization signal from a reproduction signal including jitter picked up through a reproduction head, and a clock signal having a constant period. When the clock generation means 70 for generating, the phase comparing means 90 for comparing the phase of the signal output from the clock generating means 70 and the signal output from the synchronous separation means 40, the reproduction signal is applied A / D converter 10 for converting the digital signal in synchronization with the clock signal output from the clock generating means 70, output from the A / D converter 10 in synchronization with the signal output from the clock generating means 70 Auto frequency controller (110) for automatically controlling the frequency of the signal to be delayed, the phase of the signal output from the clock generating means (70) to a predetermined phase in the automatic frequency controller (110) Output Automatic phase controller 120 for automatically controlling the phase of the signal, and operation of the automatic frequency controller 110 and the auto phase controller (APC) 120 by the signal output from the phase comparing means 90 The control signal generating means for generating a control signal for controlling the control means 100, the phase controlled by the value output from the automatic phase controller 120 for converting the value output from the automatic frequency controller 110 into an analog signal It consists of a D / A converter 30.

In particular, the automatic frequency controller 110 includes a delay means 111 for delaying a signal output from the A / D converter 10 to a predetermined phase in synchronization with a clock signal output from the clock generation means 70, and generating a control signal. Data selection means 112 for selecting and outputting an output image having a corresponding delay amount among a plurality of images output according to different delay values output from the delay means 111 according to the control signal output from the means 100. ) The automatic phase controller 120 delays the clock signal output from the clock generating means 70 with a different delay amount to output phases having a plurality of delay amounts, and the clock generating means 70. And a phase selection means 121 for selecting a value output from the phase delay means 122 in synchronization with the clock signal output from the P / A signal and outputting the D / A conversion clock signal of the D / A converter 30.

FIG. 3 is a detailed embodiment of the block diagram of FIG. 2, and the circuit diagram of the control signal generating means 100, the automatic frequency controller 110, and the automatic phase controller 120 shown in FIG. to be.

That is, the control signal generating means 100 includes a low pass filter 101 for low pass filtering the signal output from the phase comparing means 90, and an A signal for converting the signal output from the low pass filter 101 into a digital signal. / D converter 102. Delay means 111 of the automatic frequency controller 110 is a plurality of delay (D ₀ ) for delaying the signal output from the A / D converter 10 in 16 phases in synchronization with the clock signal output from the clock generating means 70 D ₁₅ ). The data selecting means 112 of the automatic frequency controller 110 includes a first decoder 1122 for decoding a signal of a higher bit among the signals output from the A / D converter 102 of the control signal generating means 100, and a clock. Selection for selecting the signals output from the delayers D ₀ to D ₁₅ of the delay means 111 by the signals output from the first decoder 1122 in synchronization with the clock signal output from the generating means 70. The unit 1121 and a delay unit 1123 for delaying a signal output from the selection unit 1121 for a predetermined time in order to match the time difference with the operation made by the automatic phase control unit 120.

The phase selector 120 of the automatic phase controller 120 may include a second decoder 1211 for decoding the lower bit of the signal output from the A / D converter 102 of the control signal generator 100, and a second decoder 1211. A delay delay 1212 for delaying a signal output from the decoder 1211 for a predetermined time to match a time difference with the operation made by the automatic frequency control unit 110, and a phase delay controlled by the signal output from the delay 1212. Phase selector for selecting a phase signal of the 16-phase delay value such as the delay means 111 output from the means 122 and outputting it as a clock signal for D / A conversion of the D / A converter 30 ( 1213).

FIG. 4A is a waveform of a signal recorded without generating jitter, FIG. 4B is a waveform diagram of a signal reproduced with jitter, and FIG. 4C is a waveform diagram of a reproduction signal compensated for jitter using the circuit diagram of the present invention. .

The operation of FIGS. 2 and 3 will now be described in conjunction with FIG.

When the reproduction signal is applied, the synchronous separation means 40 separates the vertical and horizontal synchronous signals (V.SYNC, H.SYNC), and outputs the horizontal synchronous signal to the phase comparing means 90, and generates a vertical synchronous signal. It outputs by the reset signal of the means (80).

The pseudo synchronizing signal generating means 80 generates a horizontal synchronizing signal having the same period as in writing by the clock signal output from the clock generating means 70. The clock signal output from the clock generating means 70 is a signal having a certain period. Here, the clock signal output from the clock generating means 70 is generated as a main clock signal capable of A / D conversion and D / A conversion.

The phase comparing means 90 compares the phases of the horizontal synchronization signal H.SYNC output from the synchronization separating means 40 and the pseudo horizontal synchronization signal output from the pseudo synchronization generating means 80. At this time, the comparison method is performed in the same manner as the phase comparison made in the phase synchronization loop 50 of FIG.

The control signal generating means 100 applies the comparison result output from the phase comparing means 90 to the low pass filter 101 shown in FIG. 3 to perform low pass filtering. That is, the phase comparison result outputs a high signal when the phase of the horizontal synchronizing signal output from the synchronizing separation means 40 is ahead of the phase of the pseudo horizontal synchronizing signal output from the pseudo synchronizing means 80, and a low signal is output after the phase comparison result. Filter as low as possible. The signal output from the low pass filter 101 is applied to the A / D converter 102 and digitally converted to n bits to be output.

The n bits output from the A / D converter 102 are divided into half, and the upper n / 2 bits are output to the first decoder 1122 in the automatic frequency controller 110, and the lower n / 2 bits are output to the automatic phase controller. It is output to the second decoder 1211 in 120.

On the other hand, the video signal reproduced through the head is A / D conversion through the A / D converter 10 is applied to the delay means (111). At this time, the A / D converter 10 and the delay means 111 perform signal processing in synchronization with the clock signal generated by the clock generation means 70. That is, in the case of the delay means 111, the video signal having different delay amounts is output to the data selection means 112 by delaying 16 phases in synchronization with the clock signal. In this case, the 16-phase delay is a case in which the control signal output from the control signal generating means 100 is 8 bits. Phase is set. Therefore, if the output bit of the control signal changes, the delay amount may also change. The selector 1121 is also controlled by a signal output from the first decoder 1122 in synchronization with a clock signal generated by the clock generating means 70 to output a signal having a corresponding delay amount among the signals output from the delay means 111. It selects and outputs to the next stage delayer 1123.

In other words, when the predetermined n bits output from the control signal generating means 100 are 8 bits as described above, the upper 4 bits are increased by the value of 1 only when the lower 4 bits are all high, so that the '1' of the upper bits is increased. Is the same number as '15' of the lower bits. That is, the upper 4 bits are 0 to 16, and the lower 4 bits are also 0 to 16. '1' of the upper bit means conversion of 0 ~ 15 of the lower bit. When the upper four bits are decoded by the first decoder 1122 and outputted to the selector 1121, the selector 1121 is synchronized by the clock signal of the clock generator 70 and the clock is delayed by one clock. The delayed output is performed to select one of the video signals and output the delayed signal to the delayer 1123. Referring to Figure 4 will be described in more detail.

FIG. 4A is a waveform diagram at the time of recording, a signal having no jitter, and FIG. 4B is a reproduction signal containing jitter, where the position of b0 is shifted by b1 by the position b0 and the position of d0 is shifted by d1 by c2. The first decoder 1122 controls the selection of the value output from the delay means 111 so as to pull or delay the shifted amount in order to control the automatic frequency. That is, when the output of the low pass filter 101 becomes low, the first decoder 1122 outputs values from ₀ to ₇ so as to select up to the delays D ₀ to D _{7 in} the delay means 110. When the output of the low pass filter 101 becomes high, a value from 8 to 15 is outputted to the selection unit 1121 to select one of the delay units D ₈ to D ₁₅ in the delay unit 110. Print decoded values.

In the phase delay unit 122 of the automatic phase controller 120, the phase delay unit 122 divides and outputs 16 phases within one cycle of the clock signal generated by the clock generation unit 122, and the A / D converter of the control signal generation unit 100 outputs. The lower 4 bits (by the above-described example) output from the 102 are decoded by the second decoder 1211 and output in synchronization with the time required by the automatic frequency controller 110 through the delay 1212. do. The output of the second decoder 1211 is a value that can select a phase within one clock. That is, the phase between b1 and b2 in FIG. 4 can be selected. The signal output from the delayer 1212 is applied to the phase selector 1213 to select a phase value having a corresponding delay amount among the phases delayed by the delay amount of the 16 phases output from the phase delay means 122, so that D / The A converter 30 outputs the clock signal. For high accuracy, the image divided by the phase delay unit 122 as well as the delay unit 111 described above may be set differently.

The D / A converter 30 converts the signal output from the delay unit 1123 of the automatic frequency controller 110 into an analog signal and converts and outputs in synchronization with the signal output from the automatic phase controller 120 in this conversion. . As a result, the reproducing means such as the 4c degree with jitter compensation is outputted.

As described above, the present invention provides a time-base compensation circuit capable of following jitter generated at high speed by performing automatic frequency control and automatic phase control by using a delay and a phase delay circuit instead of a conventional memory and phase synchronization loop circuit. There is an advantage that can provide.

Claims (6)

A time axis compensation circuit for eliminating time axis fluctuations included in a reproduced video signal during reproduction control of an apparatus for recording and reproducing video and audio signals; An analog / digital converter for converting the reproduced video signal into a digital signal; An automatic frequency controller for automatically controlling the frequency of the reproduced video signal by delaying the digital signal output from the analog / digital converter to a predetermined phase and selecting and outputting a signal having a corresponding delay value; Clock generating means for generating a clock signal having a predetermined period; The phase of the reproduced video signal is delayed by delaying the phase of the clock signal to the same phase as the predetermined phase and selecting and outputting a signal having a corresponding delay value using the clock signal output from the clock generating means as an input signal. An automatic phase controller for automatic control; Synchronization separating means for separating vertical and horizontal synchronization signals from the reproduced video signal; Pseudo-synchronization generating means for generating a pseudo horizontal synchronizing signal in synchronization with a clock signal outputted from the clock generating means and reset controlled by the vertical synchronizing signal output from the synchronizing separating means; Phase comparing means for comparing phases of the horizontal synchronization signal output from the synchronization separating means and the pseudo horizontal synchronization signal output from the pseudo synchronization generating means; Control signal generating means for generating a control signal for controlling the driving of the automatic frequency controller and the automatic phase controller according to the signal output from the phase comparing means; And a digital / analog converter for phase-controlling the signal output from the automatic phase controller and converting and outputting the signal output from the automatic frequency controller into an analog signal. 2. The automatic frequency controller of claim 1, wherein the automatic frequency controller comprises delay means for delaying a reproduction signal including jitter output from the A / D converter to a predetermined phase, and a first predetermined bit of the control signal output from the control signal generating means. And a selection unit for selecting a phase having a corresponding delay value among a plurality of delay images controlled by a signal output from the first decoder and decoded by the first decoder to decode. Time base compensation circuit. 3. The automatic phase controller of claim 2, wherein the automatic phase controller comprises: phase delay means for delaying a phase of a clock signal output from the clock signal generating means to a predetermined delay phase, and the first of the bits output from the control signal generating means; Phase selection for selecting a signal having a corresponding phase delay amount among the signals that are controlled by the second decoder and the signal output from the second decoder to decode the second predetermined bit except the predetermined bit. A time base compensation circuit comprising a portion. 4. The time-base compensation circuit according to claim 3, wherein the first predetermined bit is an upper bit of an output bit of the control signal generating means, and the second predetermined bit is a lower bit of an output bit of the control signal generating means. 4. The time-base compensation circuit according to claim 3, wherein the number of bits of the first predetermined bit and the second predetermined bit is the same. The method of claim 1, wherein the control signal generating means 100 is a low pass filter 101 for low-pass filtering the signal output from the phase comparing means, and a signal output from the low pass filter 101 as a digital signal A time base compensation circuit comprising an analog / digital converter for conversion.