KR100202542B1 - Luma/chroma signal separating circuit of image processor - Google Patents

Abstract

The present invention relates to a technique for separating a luminance signal and a color signal from a composite video signal in a video signal processor such as a digital television receiver. In the actual implementation of the conventional luminance signal and color signal separation circuit, when a non-standard signal is inputted, horizontal synchronization is performed. Since there is a lot of signal shaking, there is a defect that a lot of jitter occurs in the line-lock clock signal synchronized with it, and three line memories are used to process separated luminance and color signals as standard signals. In order to solve this problem, in order to solve the problem, the present invention has put the line memory 22 used for converting the non-standard signal into a standard signal in front of the decoder 23 to reduce the memory used. The non-standard signal is stored in the line memory 23 by using the light control unit 25 and the read control unit 25. In the clearance by reading the emitter standard signal, a line-burst do not use the lock clock signal by using only lock the clock signal to reduce the capital of the PLL, it was to be able to operate the system in a more stable state.

Description

Luminance / Color Signal Separation Circuit of Image Signal Processor

1 is a block diagram of luminance / color signal separation of a general image signal processor.

2 is a block diagram of a luminance / color signal separation circuit of the image signal processor of the present invention.

FIG. 3 is a detailed block diagram showing an embodiment of the light control unit in FIG.

4 is a detailed block diagram showing an embodiment of a read control unit in FIG.

(A)-(g) of FIG. 5 is an output waveform diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

21: A / D converter 22: line memory

23 decoder 24 burst-lock clock and synchronization

25: light control unit 25: lead control unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for separating luminance signals and color signals from composite video signals in a video signal processor such as a digital television receiver. In particular, the present invention has a configuration in which a single line memory and a burst-lock clock signal generator are added. The present invention relates to a luminance / color signal separation circuit of an image signal processor suitable for accurately separating luminance signals and color signals from non-standard composite video signals such as reproduction signals.

In general, a color shift signal is formed in the form of a composite video signal, and includes a sum of horizontal and vertical synchronization signals, a luminance signal, and an I / Q color difference signal that is orthogonally modulated by a color subcarrier. In order to digitally process such a signal, a clock signal is required. For this, a clock signal in which PLL is applied to a color subcarrier is commonly referred to as a burst-lock clock signal. In addition, the clock signal having the PLL applied to the horizontal synchronization signal is referred to as a line-lock clock signal.

FIG. 1 is a block diagram of a luminance / color signal separation of a general video signal processor that separates a luminance signal and a color signal from a composite image signal digitally processed using a burst-lock clock signal and a line-lock clock signal. And a burst-lock clock generator 11 for generating clock signals B-CLK and W-CLK by applying a PLL to a color subcarrier of a composite image signal CV input from the outside, and the composite image signal CV. A line-lock clock generator (12) generating a read clock signal (R-CLK) by applying a PLL to the horizontal synchronizing signal of the < RTI ID = 0.0 >),< / RTI > The analog (A) / digital (D) converter 13 for converting a digital signal into a digital signal, and a composite video signal converted into a digital signal from the A / D converter 13 and outputted, and receiving a luminance signal Y and a color signal. A decoder 14 for separating (U) and (V), and for outputting a desired pixel signal Under the control of the light clock signal W-CLK, the luminance signal Y, the color signals U, and V are stored in each line memory, and then the read clock signal R-CLK is controlled. A synchronization signal generator 16 that receives a buffer 15 that receives the output and an output signal of the line-lock clock generator 12 and generates a horizontal synchronization signal H _sync and a vertical synchronization signal V _sync . It is composed of, the operation of which is described as follows.

The analog composite video signal (CV) supplied from the outside is converted into a digital signal through the A / D converter 13 and then separated into the luminance signal (Y) and the color signal (C) by the Y / C separator (14A). Then, the color signal C is separated into the color signals U and V through the color demodulator 14B.

When the composite video signal CV is a standard signal, the A / D converter 13 converts the digital signal into a digital signal by using the clock signal B-CLK output from the burst-lock clock generator 11. During the period, exactly 910 pixels are obtained, and the color demodulator 14B uses the clock signal B-CLK to separate the color signals U and V to obtain a good picture quality, because the standard signal is obtained. This is because the horizontal period is always constant when is input.

However, when the input composite video signal CV is not a standard signal, for example, a clock signal B- generated from a non-standard signal whose horizontal period is irregularly changed according to mechanical characteristics such as the reproduction output of BC When the analog composite video signal (CV) is converted into a digital signal using CLK, more than 910 pixels are obtained per horizontal line, and more or less pixels are obtained. In addition, since the cycles are different for each line, it is difficult to process using a large memory such as a frame memory.

In view of this, a buffer 15 composed of three line memories 15A, 15B, and 15C is provided at the rear end of the color demodulator 14B, and the luminance signal Y output from the color demodulator 14B. And write the color signals U and V to the respective line memories 15A, 15B, and 15C using the write clock signal W-CLK outputted from the burst-lock clock generator 11. After reading the luminance signal Y, the color signals U, and V using the read clock signal R-CLK output from the line-lock clock generator 12, the non-standard composite video signal CV is generated. Even when inputted, 910 pixels can be obtained.

Because the light clock signal W-CLK is a clock signal generated by applying a PLL to the color carrier, the light clock signal W-CLK is irregular, and thus the number of pixels stored in the buffer 15 is lined. This may be more or less than 910, but the read clock signal R-CLK is synchronized with the horizontal period signal of the input composite video signal CV, so that 910 is output exactly per line. As a result, since 910 pixels can be read per line, there is no problem in displaying or processing the frame memory.

However, in the actual implementation of such a conventional luminance signal and color signal separation circuit, when the non-standard signal is input, a lot of jitter occurs in the horizontal synchronization signal, so jitter is generated in the line-lock clock signal synchronized thereto. You can't get a clear image. In order to eliminate such jitter, a complicated circuit must be added, and a cost increases, and three line memories are used to process separate luminance and color signals.

Accordingly, an object of the present invention is to provide a luminance / color signal separation circuit that accurately separates a luminance signal and a color signal from a non-standard composite video signal by adding one line memory and a burst-lock clock signal generator.

FIG. 2 is a block diagram of the luminance / color signal separation circuit of the image signal processor of the present invention for achieving the above object. As shown therein, an analog composite video signal (CV) input from the outside is converted into a digital signal. A / D converter 21 and a line memory for receiving a composite video signal output from the A / D converter 21 and storing pixel information in units of horizontal lines, and then selectively outputting a standardized number of pixel signals. (22) and located next to the line memory 22 to restore the luminance signal Y, the color signals U, and V from the composite video signal supplied from the line memory 22. A burst-lock clock supplied with the decoder 23 and the composite video signal CV to generate a clock signal 4FSC, a composite synchronization signal C _sync , and a vertical synchronization signal V _sync synchronized with a color burst signal. and a synchronization separation unit 24, the composite sync signal (C _sync) and a clock No. (4FSC) to supply the received based on the input timing of the horizontal synchronous signal (H _sync) synchronous to the line memory 22 is supplied to the write reset signal (WRST), and the horizontal synchronizing signal (H _sync) to a predetermined value A write control unit 25 for counting 910 and disabling the write enable signal WE supplied to the line memory 22 at each time; and the vertical synchronization signal V _sync and the clock signal 4FSC. The read control unit 26 supplies the read reset signal RRST to the line memory 22 by counting the horizontal period 910 at each time while being cleared by the vertical synchronization signal V _{sync that} has been delayed for a predetermined time. When described in detail with reference to Figures 3 to 5 attached to the operation and effects of the present invention configured as described above are as follows.

The input composite video signal CV is converted into a digital signal through the A / D converter 21 on the one hand and supplied to the line memory 22 side, and to the burst-lock clock and the sync separator 24 on the other hand. The supplied composite sync signal (C _sync ), which includes horizontal, vertical and retrace sections, is separated and supplied to the light control unit 25, and the vertical sync signal (V _sync ) separated from the combined sync signal (C _sync ) is again provided. Is supplied to the read control section 26, and a clock signal 4FSC synchronized with the color burst signal is generated and supplied to the write control section 25, the read control section 26, and the decoder 23.

The light control unit 25 receives the complex sync signal C _sync and separates the horizontal sync signal H _sync therefrom, and then supplies the write reset signal WRST to the line memory 22 based on the received _sync signal C _sync . Therefore, even if the inputted composite synchronous signal (CV) is a non-standard signal, the first data of the horizontal line is recorded at the first position on the first-in first-out line memory.

The composite video signal CV of the non-standard signal may include 910 or more pixel signals per horizontal line or 910 or less pixel signals, and the line memory 22 may store 910 pixels or less. Since the capacitor has a capacity, no problem occurs when more than 910 pixel signals are input.

However, when including more than 910 pixel signals, the line memory 22 overflows so that the first data of several lines is not stored at the first address of the line memory 22. Thus, the light controller 25 in the first when the 910 counter (25C) and a JK flip-flop (25D) used by the 910 after the horizontal sync signal (H _sync) input counts, as in FIG. 3 Added To solve this problem, The enable signal WE is disabled.

That is, as shown in FIG. 3, the composite synchronization signal C _sync is supplied to the horizontal synchronization separator 25A, and the horizontal synchronization signal H _sync is separated therefrom, and the edge detector 25B receives the horizontal synchronization signal H. The edge of _sync is detected and the write reset signal WRST is supplied to the line memory 22. Since the complex sync signal C _sync is generated irregularly, the write reset operation is irregular.

However, the read reset operation is performed in exactly 910 units by the control operation of the read control unit 26 configured as shown in FIG. 4, which will be described below.

The vertical synchronization signal V _sync is delayed 1/2 line through the 1/2 line delay 26A, and is then supplied to the edge detector 26B so that the edge signal of the 1/2 line delayed vertical synchronization signal V _sync is in that the detection point rear of the 910 counter (26C) signal (CLR) is supplied to the 910 counter (26C) is cleared, as thus cleared a predetermined period by the vertical synchronizing signal (V _sync) the horizontal exactly by 910 each time The period is counted to supply the read reset signal RRST to the line memory 22.

The reason why the 1/2 line delay unit 26A is used is that the read operation is performed 1/2 line after the time at which the write reset signal WRST is generated.

However, when the vertical synchronization signal V _sync is supplied while counting the horizontal period by 910 as described above, the read reset signal RRST is output when the horizontal period is not 910, and the reset is performed at this time. The operation was performed in the blank section of the vertical sync signal (V _sync ) so as not to affect the screen.

As a result, the start data of the line is set by the write operation as described above. Since the 910 pixel data is read after the first reset from the vertical synchronization signal V _sync by the 910 counter 26C of the read control unit 26, even if the input composite video signal CV is a non-standard signal, the line memory The pixel data read out at 22 is output in the same form as when a standard signal is input.

However, in this case, the first data of the line is matched, but the data at the end of the line is truncated, and thus discontinuity occurs in the unit of line.

In general, the decoder 23 that separates the luminance signal from the color signal and performs color demodulation is supplied with color signal information for distinguishing which color signal the input composite data is. This is called ICLK. Since the ICLK is four times the clock of the 4FSC and the phase is synchronized with the color carrier of the input data, color separation can be performed using the ICLK.

That is, as described above, in order to solve the problem that the color demodulation is not performed because the phase data between the ICLK and the image data separated from the PLL is not in phase because the data of the latter part of the horizontal line is manipulated, the ICLK is similar to the image data. 22) and then lead.

When writing to the first-in first-out line memory 22, the data and phase are synchronized, so there is no problem. Even if a discontinuity is generated at the end of the horizontal line, the ICLK also generates discontinuities at the same position. The phases of and ICLK are synchronized so that color separation can be performed accurately. For this purpose, only one bit of the line memory 22 needs to be added.

The image data read-out through the above process is supplied to the decoder 23 so that the luminance signal Y and the color signal C are separated, and the separated color signal C is demodulated and the decoder 23 is then decoded. The luminance signal Y and the color signals U and V are output from the.

For reference, a first-in-first-out line memory 22 is constructed in front of the decoder 23, and the composite video signal CV of the non-standard signal digitally converted using the write control unit 25 and the read control unit 26 is used. By converting to a standard signal, the memory can be reduced by 1/3 compared to the conversion of the standard signal to the luminance signal Y, the color signal U, and the V output from the decoder 23.

As described in detail above, the present invention adds one line memory and a burst-lock clock signal generator to the image signal processor, and controls the read / write operation of the line memory through the write / read controller. It is possible to save the memory by converting a composite video signal to a standard signal, and the number of PLLs can be reduced by using only the burst-lock clock signal instead of the line-lock clock signal. By using only, the system can be operated in a more stable state.

Claims (4)

A line memory 22 that receives the composite video signal CV output from the A / D converter 21 and stores pixel information in units of horizontal lines, and selectively outputs only a standardized number of pixel signals, and the line memory A decoder 23 which is located at the next stage after 22 and recovers the luminance signal Y, the color signals U, and V from the composite video signal supplied from the line memory 22; A clock signal (4FSC), a composite synchronization signal (C _sync ) and a vertical synchronization signal (V _sync ) synchronized with the color burst signal by receiving the image signal (CV), and a burst-lock clock and synchronization separator (24) , by counting the horizontal synchronization signal synchronized to the line memory 22 write reset signal a predetermined value (910) based on the input timing of the supply, and the horizontal sync signal (H _sync) to (WRST) in the (H _sync) The write control for disabling the write enable signal WE supplied to the line memory 22 at each time. 25, a predetermined time lead control unit for while each time cleared by counting the horizontal period (910) fed by the line memory 22. Lee give reset signal (RRST) by the delay processed vertical synchronizing signal (V _sync) And a luminance / color signal separation circuit of a video signal processor, comprising: (26). The luminance / color signal separation circuit according to claim 1, wherein the line memory (22) is configured to store and output a clock signal (ICLK) together with pixel information in units of horizontal lines. The light control unit 25 is a horizontal synchronous separator (25A) for separating the horizontal synchronous signal (H _sync ) from the composite synchronous signal (C _sync ) and the edge of the horizontal synchronous signal (H _sync ) An edge detector 25B for detecting a signal and generating a write reset signal WRST synchronized with the signal, and a 910 counter 25C for counting a predetermined value 910 after the signal is cleared by the horizontal sync signal H _sync . And a JK flip-flop 25D for generating a write enable signal WE by inputting the horizontal sync signal H _sync and the output signal of the 910 counter 25C. / Color signal separation circuit. 2. The readout control unit 26 is a half line delay unit 26A for delaying and outputting a vertical synchronization signal V _sync for 1/2 horizontal line, and the 1/2 line delay unit 26A. Edge detector 26B which detects an edge of the delayed vertical synchronization signal V _sync and outputs a clear signal CLR according to the delayed output signal, and is cleared in synchronization with the clear signal CLR, and at a predetermined value. And a 910 counter (26C) for outputting a read reset signal (RRST) after counting.