KR100225237B1 - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- KR100225237B1 KR100225237B1 KR1019960062303A KR19960062303A KR100225237B1 KR 100225237 B1 KR100225237 B1 KR 100225237B1 KR 1019960062303 A KR1019960062303 A KR 1019960062303A KR 19960062303 A KR19960062303 A KR 19960062303A KR 100225237 B1 KR100225237 B1 KR 100225237B1
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- molding
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- semiconductor
- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
본 발명은 반도체 패키지에 관한 것으로, 특히 BGA(Ball Grid Array; 볼 그리드 어레이) 반도체 패키지를 몰딩할 때 상기 몰딩물의 상면을 단차지는 피라미드 형상의 다층으로 형성하여 몰딩공정이나 열가공 공정에서 발생되는 반도체 패키지의 휨 현상을 방지하고, 다이패드 상에 부착된 반도체칩의 계면박리 및 크랙을 방지하여 반도체 패키지의 휨 현상을 최소화한 반도체 패키지이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package. In particular, when molding a ball grid array (BGA) semiconductor package, a semiconductor generated in a molding process or a thermal processing process is formed by forming a pyramid-shaped multilayer that blocks the upper surface of the molding. The semiconductor package prevents warpage of the package and minimizes warpage of the semiconductor chip attached to the die pad and minimizes warpage of the semiconductor chip.
Description
본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 BGA(Ball Grid Array : 볼 그리드 어레이) 반도체 패키지를 몰딩할 때 상기 몰딩물의 형상을 단차지는 피라미드형상의 다층으로 형성하여 반도체 패키지의 휨 현상을 최소화하도록 된 것이다.The present invention relates to a semiconductor package, and more particularly, to molding a ball grid array (BGA) semiconductor package, to form a pyramid-shaped multilayer that blocks the shape of the molding to minimize warpage of the semiconductor package. It is to be done.
일반적인 BGA 반도체 패키지는 첨부도면 제1a, b도에 도시된 바와 같이 상면 중앙에 다이패드(21)가 형성되고, 표면에는 회로패턴(22)이 형성되며, 상기 회로패턴(22)을 보호하기 위해 솔더마스크(23)가 코팅된 회로기판(20)과, 상기 회로기판(20)의 상면 중앙에 부착된 반도체칩(10)과, 상기 반도체칩(10)과 상기 회로기판(20)의 회로패턴(22)을 연결하여 신호를 전달하는 와이어(30)와, 상기 회로기판(20)의 회로패턴(22)에 융착되어 외부로 신호를 전달하는 솔더볼(40)과, 상기 반도체칩(10)과 그외 주변구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 몰딩몰(50)로 구성된다.In the general BGA semiconductor package, as shown in FIGS. 1A and 1B, a die pad 21 is formed in a center of an upper surface thereof, a circuit pattern 22 is formed on a surface thereof, and the circuit pattern 22 is protected. A circuit board 20 coated with a solder mask 23, a semiconductor chip 10 attached to a center of an upper surface of the circuit board 20, and circuit patterns of the semiconductor chip 10 and the circuit board 20. A wire 30 for connecting the wires 22 to transmit the signal, a solder ball 40 fused to the circuit pattern 22 of the circuit board 20 to transmit a signal to the outside, and the semiconductor chip 10 In order to protect other peripheral components from external oxidation and corrosion, it is composed of a molding mall 50 wrapped around the outside thereof.
그러나, 이러한 BGA 반도체 패키지(100)는, 몰딩몰(50)로 몰딩된 형상이 단순히 정사각형이나 직사각형의 모양을 가지고 있으며, 단층으로 형성되어 있다. 또한, 이러한 BGA 반도체 패키지는 회로기판(20)의 일측면만을 몰딩하는 원사이드(One-Side)몰딩 방식이기 때문에 몰딩공정 후에 회로기판(20)과 몰딩몰(50)과의 서로 다른 열팽창 계수로 인하여 발생되는 응력(스트레스; Stress)을 충분히 감쇄시켜 줄 수 없으므로, 고온의 환경에서 이루어지는 공정(회로기판(PCB)의 다이패드상에 실리콘재의 반도체칩을 부착하는 공정, 와이어 본딩 공정, 와이어 본딩을 완료한 후 몰딩물로 그 외부를 감싸는 몰딩 공정 등)에서는 자재의 휨 현상이 극대화된다.However, the BGA semiconductor package 100 has a shape in which the molded part 50 is simply square or rectangular, and is formed in a single layer. In addition, since the BGA semiconductor package is a one-side molding method of molding only one side of the circuit board 20, the BGA semiconductor package may have different thermal expansion coefficients between the circuit board 20 and the molding mold 50 after the molding process. Because the stress caused by stress cannot be attenuated sufficiently, a process performed in a high temperature environment (a process of attaching a semiconductor chip of silicon material on a die pad of a circuit board (PCB), a wire bonding process, and a wire bonding process) In the molding process, such as wrapping the outside of the molding after completion, the warpage of the material is maximized.
또한, 반도체 패키지의 휨을 발생시키는 응력은 몰딩몰(50)의 경화시 발생되는 수축에 의해서 반도체 패키지(100)에 휨이 발생되는데, 이러한 휨 현상은 반도체 패키지의 측벽에서 발생되며, 특히 반도체 패키지의 측벽이 서로 만나는 각각의 코너부에서 가장 심하게 발생되는 것이다.In addition, the stress that causes the warpage of the semiconductor package is warp occurs in the semiconductor package 100 by the shrinkage generated during the curing of the molding mold 50, this warpage phenomenon occurs in the sidewall of the semiconductor package, in particular It occurs most severely at each corner where the side walls meet each other.
즉, 첨부도면 제2a, b도와 같이 몰딩물(50)의 내무에 있는 다이패드(21)가 휘게되어 회로기판(20)의 회로패턴(22)에 융착된 솔더볼(40)(Solder Ball; 납공, 집적회로의 리드핀 역할)의 평탄성이 문제가 된다.That is, the solder ball 40 (Solder Ball; lead ball) fused to the circuit pattern 22 of the circuit board 20 by bending the die pad 21 in the interior of the molding 50 as shown in the attached drawings 2a, b. , The flatness of the lead pin of the integrated circuit) becomes a problem.
특히, 다이패드(21)의 휨은 반도체칩(10)과의 접착력을 저하시켜 계면박리 및 크랙을 가져오므로 집적회로패키지(100)의 기능 및 신뢰성에 큰 문제로 대두되며, 또한 솔더볼(40)의 비평탄성으로 인하여 바더보드에 BGA 반도체 패키지를 실장시 솔더볼(40)이 마더보드에 접속되지 않아 반도체 패키지(100)의 기능 수행에 문제가 발생된다.In particular, since the bending of the die pad 21 lowers the adhesive force with the semiconductor chip 10 and brings about interfacial peeling and cracking, it is a big problem in the function and reliability of the integrated circuit package 100, and also solder balls 40 Due to the non-flatness of the), when the BGA semiconductor package is mounted on the motherboard, the solder ball 40 is not connected to the motherboard, thereby causing a problem in performing the function of the semiconductor package 100.
본 발명의 목적은 이와 같은 문제점을 해결하기 위하여 발명된 것으로서, 반도체 패키지를 외부로 부터 보호하기 위하여 감싸진 몰딩물의 상면을 단차진 피라미드형상의 다층으로 형성하여 몰딩 공정이나 열가공 공정에서 반도체 패키지의 휨을 방지하고, 다이패드 상에 부착된 반도체칩의 계면박리 및 크랙을 방지하도록 된 반도체 패키지를 제공함에 있다.An object of the present invention is to solve the above problems, in order to protect the semiconductor package from the outside by forming the upper surface of the encapsulated molding in a stepped pyramid-shaped multilayer of the semiconductor package in the molding process or thermal processing process A semiconductor package is provided to prevent warpage and to prevent interfacial peeling and cracking of a semiconductor chip attached on a die pad.
제1a, b도는 종래의 반도체 패키지를 나타낸 도면으로서,1a and b show a conventional semiconductor package,
제1a도는 반도체 패키지의 단면도.1A is a cross-sectional view of a semiconductor package.
제1b도는 반도체 패캐지 평면도.1B is a plan view of a semiconductor package.
제2a, b도는 종래의 반도체 패키지의 휨 상태를 나타낸 정면도.2A and 2B are front views showing the bending state of the conventional semiconductor package.
제3도는 본 발명에 따른 반도체 패키지의 구조를 나타낸 단면도.3 is a cross-sectional view showing the structure of a semiconductor package according to the present invention.
제4도는 본 발명에 따른 반도체 패키지의 평면도.4 is a plan view of a semiconductor package according to the present invention.
제5도는 본 발명의 실시 예를 나타낸 반도체 패키지의 정면도.5 is a front view of a semiconductor package showing an embodiment of the present invention.
제6도는 본 발명의 다른 실시 예를 나타낸 반도체 패키지의 정면도.6 is a front view of a semiconductor package according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 반도체칩 20 : 회로기판10: semiconductor chip 20: circuit board
30 : 와이어 40 : 솔더볼30: wire 40: solder ball
50 : 몰딩물50: molding
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
제3도는 본 발명에 따른 BGA 반도체 캐키지를 나타낸 단면도이고, 제4도는 본 발명에 따른 BGA 반도체 패키지의 평면도로서, 그 구조는 상면 중앙에는 다이패드(21)가 형성되고, 표면에는 회로패턴(22)이 형성되며, 상기 회로패턴(22)을 보호하기 위해 솔더마스크(23)가 코팅된 회로기판(20)과, 상기 회로기판(20)의 상면 중앙에 부착된 반도체칩(10)과, 상기 반도체칩(10)과 상기 회로기판(20)의 회로패턴(22)을 연결하여 신호를 전달하는 와이어(30)와, 상기 회로기판(20)의 회로패턴(22)에 융착되어 외부로 신호를 전달하는 솔더볼(40)과, 상기 반도체칩(10)과 그 외 주변 구성품들을 외부의 산화 및 부식으로부터 보호하기 위하여 그 외부를 감싼 몰딩물(50)로 구성되는 반도체 패키지에 있어서, 상기 몰딩물(50)의 상면 중앙의 중심부분이 몰딩물(50)의 테두리부분 보다 두꺼운 두께(t)로 형성되도록 단차진 두 개의 층으로 형성하여 열에 의한 휨 현상을 최소화하도록 된 것을 특징으로 한다.3 is a cross-sectional view showing a BGA semiconductor package according to the present invention, and FIG. 4 is a plan view of the BGA semiconductor package according to the present invention, the structure of which is formed with a die pad 21 at the center of an upper surface thereof, and a circuit pattern on the surface thereof. 22, a circuit board 20 coated with a solder mask 23 to protect the circuit pattern 22, a semiconductor chip 10 attached to a center of an upper surface of the circuit board 20, and A wire 30 is connected to the semiconductor chip 10 and the circuit pattern 22 of the circuit board 20 to transmit a signal, and the circuit pattern 22 of the circuit board 20 is fused to the outside signal. In the semiconductor package consisting of a solder ball 40 for delivering a, and a molding 50 wrapped around the outside to protect the semiconductor chip 10 and other peripheral components from external oxidation and corrosion, the molding The center portion of the upper surface center of the (50) is more than the edge of the molding Characterized in that the stepped so as to minimize the warpage due to heat to form the two layers so as to form a cloud thickness (t).
여기서, 상기 몰딩물(50)은 상면 중앙의 중심부분이 몰딩물(50)의 테두리 부분보다 두꺼운 두께(t)로 형성되도록 피라미드 형상의 단차진 두개 이상의 다층으로 형성할 수 있다.Here, the molding 50 may be formed in two or more multi-layered pyramid-shaped stepped so that the central portion of the center of the upper surface is formed to a thickness (t) thicker than the edge portion of the molding 50.
이와 같이 몰딩물(50)을 피라미드형상의 단차진 다층으로 형성하면, 몰딩물(50)의 경화시 발생되는 수축에 의한 응력을 감쇄시켜 반도체 패키지의 휨을 방지할 수 있다. 즉, 몰딩물(50)의 경화시 발생되는 수축에 의한 반도체 패키지(100)의 변형을 최소화함으로서 반도체 패키지의 휨을 방지할 수 있는 것이다.When the molding 50 is formed in a pyramidal stepped multilayer, the stress due to shrinkage generated during curing of the molding 50 may be attenuated to prevent warpage of the semiconductor package. That is, the bending of the semiconductor package can be prevented by minimizing deformation of the semiconductor package 100 due to shrinkage generated during curing of the molding 50.
상기와 같이 몰딩물(50)을 단차진 피라미드형상으로 형성함에 있어서, 제3도와 같이 두개의 층으로 형성할 수 있으나, 필요에 따라서 제5도에 도시된 바와 같이 두개 이상의 다층으로 형성하여 몰딩물(50)의 수축에 의한 응력을 최소화할 수 있다. 또한, 제6도에 도시된 바와 같이 상기의 몰딩물(50)을 그 중심부분이 볼록한 형상으로 돌출 형성하여도 휨 현상을 방지할 수 있다.In forming the molding 50 in a stepped pyramid shape as described above, it may be formed in two layers as shown in FIG. 3, but if necessary formed in two or more multilayers as shown in FIG. The stress due to shrinkage of 50 can be minimized. In addition, as shown in FIG. 6, even if the molded part 50 is protruded to have a convex shape, the warpage phenomenon can be prevented.
이와 같이 구성되는 본 발명의 반도체 패키지(100)는 몰딩물(50)의 경화시 발생되는 몰딩물(50)의 수축에 의해서 반도체 패키지(100)에 휨이 발생된다. 이때, 회로기판(20)과 몰딩물(50)과는 열팽창계수가 상이함으로서 열적불일치(Thermal Mismatch)가 발생되고, 이러한 열적불일치는 응력에 의해 몰딩물(50)의 테두리부분에 집중되는 것으로, 상기 몰딩물(50)의 상면에 새로운 두께(t)를 갖는 층을 단차지게 피라미드형상으로 형성함으로서 각각의 층에서 응력을 분담함으로서 반도체 패키지의 휨을 최소화시키는 것이다.In the semiconductor package 100 of the present invention configured as described above, warpage occurs in the semiconductor package 100 due to shrinkage of the molding 50 generated when the molding 50 is cured. In this case, the thermal mismatch occurs because the thermal expansion coefficient is different from the circuit board 20 and the molding 50, and the thermal mismatch is concentrated on the edge of the molding 50 by stress. By forming a layer having a new thickness t on the upper surface of the molding 50 in a stepped pyramid shape, the stress of each layer is shared to minimize warpage of the semiconductor package.
이상의 설명에서와 같이 본 발명은 BGA 반도체 패키지의 몰딩시나 열가공 공정에서 발생하는 반도체 패키지의 휨 현상을 몰딩물의 형상을 변형시켜 열팽창에 따른 반도체칩의 파손이나 솔더볼의 비평탄성 문제 등을 해결할 수 있는 것이다. 또한, 반도체 패키지화 되는 여타의 반도체 패키지를 본 발명에 의한 몰딩물의 디자인을 적용함으로써 보다 향상된 반도체 패키지를 제조할 수 있어 제조 공정상에서 발생되는 반도체칩의 기능 및 신뢰성을 높일 수 있는 것이다.As described above, the present invention can solve the warpage phenomenon of the semiconductor package caused by the molding or thermal processing of the BGA semiconductor package by modifying the shape of the molding to solve the problem of breakage of the semiconductor chip due to thermal expansion or non-flatness of the solder ball. will be. In addition, by applying the design of the molded article according to the present invention to other semiconductor packages to be packaged in the semiconductor, it is possible to manufacture a more improved semiconductor package to improve the function and reliability of the semiconductor chip generated in the manufacturing process.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062303A KR100225237B1 (en) | 1996-12-06 | 1996-12-06 | Semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019960062303A KR100225237B1 (en) | 1996-12-06 | 1996-12-06 | Semiconductor package |
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| Publication Number | Publication Date |
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| KR19980044241A KR19980044241A (en) | 1998-09-05 |
| KR100225237B1 true KR100225237B1 (en) | 1999-10-15 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1019960062303A Expired - Fee Related KR100225237B1 (en) | 1996-12-06 | 1996-12-06 | Semiconductor package |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987904B2 (en) | 2012-07-09 | 2015-03-24 | Samsung Electronics Co., Ltd. | Substrate of semiconductor package and method of fabricating semiconductor package using the same |
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| KR20020043671A (en) * | 2000-12-02 | 2002-06-12 | 마이클 디. 오브라이언 | Warpage reduction structure of heat sink for manufacturing semiconductor package |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0230170A (en) * | 1988-07-19 | 1990-01-31 | Matsushita Electric Works Ltd | Semiconductor package and manufacture thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH0230170A (en) * | 1988-07-19 | 1990-01-31 | Matsushita Electric Works Ltd | Semiconductor package and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8987904B2 (en) | 2012-07-09 | 2015-03-24 | Samsung Electronics Co., Ltd. | Substrate of semiconductor package and method of fabricating semiconductor package using the same |
| US9082871B2 (en) | 2012-07-09 | 2015-07-14 | Samsung Electronics Co., Ltd. | Substrate of semiconductor package and method of fabricating semiconductor package using the same |
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| KR19980044241A (en) | 1998-09-05 |
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