KR100226503B1 - Manufacturing Method of Semiconductor Device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, comprising: forming a mask layer defining a gate region in an active region on a first conductive semiconductor substrate having an active region and a field region; Forming a sacrificial oxide film on a portion not formed, removing the mask layer and the sacrificial oxide film so that the surface of the semiconductor substrate has a step at a predetermined inclination angle, and forming a field oxide film in the field region of the semiconductor substrate And forming a gate oxide film and a gate so as to cover an inclined surface on the stepped portion on the semiconductor substrate, and forming an impurity region of a second conductivity type used as a source and a drain region in the semiconductor substrate. . Therefore, since the channel length is increased because the surface of the gate region of the semiconductor substrate has a predetermined inclination angle, the short channel effect can be reduced and a second concentration used as a low concentration region and a source and drain region. Since the first high concentration region surrounds the high concentration region in a pocket shape near the channel, the punch-through phenomenon can be prevented.

Description

Manufacturing Method of Semiconductor Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of improving punch through and short channel effect characteristics.

As semiconductor devices become highly integrated, each cell becomes finer and the internal electric field strength increases. This increase in electric field strength causes a hot-carrier effect in which the carrier of the channel region is accelerated and injected into the gate oxide layer in the depletion layer near the drain during operation of the device. The carrier injected into the gate oxide film creates a level at the interface between the semiconductor substrate and the gate oxide film, thereby changing the threshold voltage (V _TH ) or decreasing the mutual conductance, thereby degrading device characteristics. Therefore, in order to reduce the deterioration of device characteristics due to the hot-carrier effect, a structure in which the drain structure is changed such as LDD (Lightly Doped Drain) or the like should be used.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

Referring to FIG. 1A, a field oxide film 13 is formed on a predetermined portion of a surface of a P-type semiconductor substrate 11 by a conventional selective oxidation method such as LOCOS (Local Oxidation of Silicon) to form an active region and a field region of a device. To qualify.

Referring to FIG. 1B, a gate oxide film 15 is formed by thermally oxidizing the surface of the semiconductor substrate 11. Then, polycrystalline silicon is deposited on the field oxide film 13 and the gate oxide film 15 by chemical vapor deposition (hereinafter, referred to as CVD), and patterned by photolithography to form the gate 17. ). A low concentration region 19 for forming an LDD structure is formed by implanting N-type impurities at low concentration into the exposed portion of the semiconductor substrate 11 using the gate 17 as a mask.

Referring to FIG. 1C, the sidewall 21 is formed on the side of the gate 17. In this case, the sidewall 21 is formed by etching back the silicon oxide and the gate 17 and the semiconductor substrate 11 after deposition. N-type impurities are implanted at high concentration into the semiconductor substrate 11 using the gate 17 and the sidewall 21 as a mask to form a high concentration region 23 used as a source and a drain region. In this case, the high concentration region 23 is formed to overlap the low concentration region 19.

However, as described above, the conventional technology has a problem in that a short channel effect is generated and a punch-through is increased because the length of the gate is shortened as the length of the gate is shortened as the size of the device is reduced due to the high integration of the semiconductor device.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device which can reduce the occurrence of a short channel effect by suppressing the decrease in the length of the channel even if the size of the device is reduced.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can prevent an increase in punch-through even when the size of an element is reduced.

A method of manufacturing a semiconductor device according to the present invention for achieving the above objects comprises the steps of forming a mask layer defining a gate region in the active region on a first conductivity type semiconductor substrate having an active region and a field region; Forming a sacrificial oxide film on a portion where the mask layer is not formed on the substrate, removing the mask layer and the oxidized oxide film so that the surface of the semiconductor substrate has a step at a predetermined inclination angle, and a field region of the semiconductor substrate Forming a field oxide film on the semiconductor substrate, forming a gate oxide film and a gate so as to cover an inclined surface on the stepped portion on the semiconductor substrate, and forming a second conductivity type impurity region to be used as a source and a drain region in the semiconductor substrate. It is equipped with the process of doing.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

2A through 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

2A to 2E are manufacturing process diagrams of a semiconductor device according to the present invention.

Referring to FIG. 2A, a buffer oxide film 33 is formed on a P-type semiconductor substrate 31 by a thermal oxidation method, and silicon nitride is deposited on the buffer oxide film 33 by a CVD method to form a mask layer 35. ). The mask layer 35 and the buffer oxide film 33 are patterned by the photolithography method so as to remain only in the gate region.

Referring to FIG. 2B, the first high concentration region 37 is formed by implanting P-type impurities such as boron B at a high concentration in a portion where the mask layer 35 of the semiconductor substrate 31 is not formed. The thick sacrificial oxide film 39 is formed by thermally oxidizing a portion where the mask layer 35 of the semiconductor substrate 31 is not formed. In this case, the sacrificial oxide layer 39 is also grown under the mask layer 35 to form a bird'd beak.

Referring to FIG. 2C, the mask layer 35 is removed and the buffer oxide film 33 and the sacrificial oxide film 39 are removed to expose the semiconductor substrate 31. At this time, the surface of the semiconductor substrate 31 is stepped by the sacrificial oxide film 39 to have a predetermined inclination angle, thereby increasing the size of the surface. A field oxide film 41 is formed in a predetermined portion of the semiconductor substrate 31, that is, in the field region, to define the active region of the device by a selective oxidation method such as LOCOS (Local Oxidation of Silicon). In the above description, the field oxide film 41 may be formed in the semiconductor substrate 31 by filling the trench with silicon oxide.

Referring to FIG. 2D, the gate oxide film 43 is formed in the gate region in the active region on the semiconductor substrate 31, and the gate 45 is formed on the gate oxide film 43. The gate 45 is formed by forming and then patterning a polyside structure of polycrystalline silicon or polycrystalline silicon / silicide doped with impurities. In this case, the gate 45 is formed to cover the inclined surface forming the step of the semiconductor substrate 31. In addition, using the gate 45 as a mask, a low concentration for forming an LDD structure to be included in the first high concentration region 37 by ion implantation of N-type impurities such as phosphorus (P) or ethnic (As) at low concentrations. Area 47 is formed. The low concentration region 47 under the gate 45 is used as a channel, and the channel length is increased because the channel is formed to include an inclined surface forming a step. Therefore, it is possible to suppress that the length of the channel is reduced to reduce the occurrence of the short channel effect.

Referring to FIG. 2E, a sidewall 49 is formed on the side of the gate 45 to overlap a predetermined portion of the low concentration region 47. The sidewalls 41 are formed by depositing silicon oxide to cover the gate 45 by CVD and then etching back by anisotropic etching such as reactive ion etching to expose the gate 45 and the semiconductor substrate 31. . N-type impurities, such as phosphorus (P) or arsenic (As), are implanted at high concentration into the semiconductor substrate 31 by using the gate 45 and the sidewalls 49 as masks, which are used as source and drain regions. The second high concentration region 51 is formed. In this case, the second high concentration region 51 is formed so as to overlap a predetermined portion of the first high concentration region 37 and the low concentration region 47. Therefore, since the first high concentration region 37 surrounds the second high concentration region 51 and the low concentration region 47 in the pocket shape near the channel, the punch-through phenomenon can be prevented. The first high concentration region 37 under the field oxide film 41 becomes a channel stopper.

Therefore, the present invention has the advantage that the short channel effect can be reduced because the channel length is increased because the surface of the gate region of the semiconductor substrate has a predetermined angle of inclination. In addition, since the first high concentration region is enclosed in the pocket shape in the vicinity of the channel, the second high concentration region used as the low concentration region and the source and drain regions has an advantage of preventing the punch-through phenomenon.

Claims (4)

Forming a mask layer defining a gate region in the active region on the first conductive semiconductor substrate having an active region and a field region, and forming a sacrificial oxide film on a portion where the mask layer on the semiconductor substrate is not formed And removing the mask layer and the sacrificial oxide film so that the surface of the semiconductor substrate has a stepped angle at a predetermined inclination angle, forming a field oxide film in the field region of the semiconductor substrate, and forming a stepped portion on the semiconductor substrate. Forming a gate oxide film and a gate so as to cover the inclined surface; and forming a second conductive impurity region used as a source and a drain region in the semiconductor substrate. The method of manufacturing a semiconductor device according to claim 1, wherein the mask layer is formed of silicon nitride. The method of manufacturing a semiconductor device according to claim 1, further comprising forming the mask layer and forming a high concentration region of a first conductivity type in a portion of the semiconductor substrate where the mask layer is not formed. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity region of the second conductivity type is formed so as to surround the high concentration region of the first conductivity type in a pocket shape in a portion adjacent to the gate.

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