KR100223676B1 - Method for manufacturing interlayer insulating film of memory cell used in nonvolatile semiconductor memory device - Google Patents

Abstract

와 희석 가스를 함유하는 분위기로 나이트라이데이션시키는 단계와; 상기

가스를 배출한후 연속적으로 순수

가스를 유입시키면서 950∼1050℃에서 소정 두께로 하부 산화막을 형성시키는 단계와; 연속적으로 순수

가스 분위기에서 상기 하부 산화막에 질소를 침투시키는 단계와; 상기 반응한 가스를 배출시킨후 750∼950℃에서

와

의 반응으로 질화막을 침적시키는 단계와; 연속적으로 상기 반응한 가스를 배출시킨후 750∼950℃에서

와

의 반응으로 상부 산화막을 침적시키는 단계와; 연속적으로 950∼1050℃의 온도범위에서

가스 분위기에서 상기 상부 산화막에 질소를 침투시키는 단계를 포함하는 것을 특징으로 한다.The present invention relates to a method of manufacturing an interlayer insulating film of a memory cell used in an electrically erasable and programmable nonvolatile semiconductor memory device, which method is performed at 800 to 900 ° C to prevent the growth of a native oxide film.

And nitridating to an atmosphere containing the diluent gas; remind

Pure water continuously after releasing gas

Forming a lower oxide film at a predetermined thickness at 950 to 1050 ° C. while introducing gas; Continuously pure

Infiltrating nitrogen into the lower oxide film in a gas atmosphere; After discharging the reacted gas at 750 ~ 950 ℃

Wow

Depositing a nitride film in response to; At 750-950 ° C. after continuously discharging the reacted gas

Wow

Depositing an upper oxide film by reaction of; Continuously in the temperature range of 950 ~ 1050 ℃

And infiltrating nitrogen into the upper oxide film in a gas atmosphere.

Description

Method for manufacturing interlayer insulating film of memory cell used in nonvolatile semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a method of manufacturing an interlayer insulating film of a memory cell used in an electrically erasable and programmable nonvolatile semiconductor memory device.

The flash EEPROM, one of the promising devices in the next-generation memory market, is one of the important limitations in the integration of sub-micron devices under thresholds due to deterioration of tunnel oxide and interlayer dielectrics due to stress caused by program-erase cycles. It is the narrowing of the voltage and the degradation of the data retention characteristics. In particular, the data retention property of nonvolatile memory depends on the thickness or property of interlayer insulating film where defects are relatively large, so that the scaling constraint is large, and the thickness of ONO structure is set even in coupling ratio. It is a disadvantage in doing this. A schematic process for a memory cell using such an ONO structure is shown in FIG.

1A to 1C are sequential vertical cross-sectional views for manufacturing a memory cell of a nonvolatile semiconductor memory device, and FIG. 2 is a specific vertical cross-sectional view of a region 200 indicated by a dotted line in FIG. 1C.

FIG. 1A is a cross-sectional view illustrating a process of forming an en-type or a dopant impurity layer by a CMOS process, and then forming the field oxide films 102A and 102B and then filling the first electrode layer 104. After forming the impurity layer using photo, ion implantation technology, and high temperature heat treatment technology on the silicon substrate 100, and then defining the substrate and the well region by a photo process to make an electrical insulating layer between the elements High concentrations of boron are ion implanted (101A, 101B), well-known partial oxidation method (LOCOS) and the like to form the device isolation layer and field oxide film (102A, 102B) and then remove unnecessary films and silicon surface layer or field oxide film A process of forming a 70100 터널 tunnel oxide film 103 on 102A and 102B, and then depositing impurities to stack the first electrode layer 104 made of a conductive layer is shown.

FIG. 1B shows a process from the first electrode layer 104 to the lamination of the interlayer insulating film 105.

) 또는

나 Ar등과 같은 희석된 혼합가스 분위기에서 나이트라이데이션을 시켜 폴리 실리콘의 네이티브 옥사이드(Native Oxide)층의 성장을 방지한후 반응로에서 반응한 가스를 700℃ 이하로 온도를 하강시켜 배출시키고 연속적으로 9501100℃, 순수

가스 분위기에서 소정량의 하부 옥사이드층(201)을 형성한 후 순수한

또는

가스를 사용 옥시나이트라이데이션시킨다. 그후 750950℃ 범위에서 500 torr 이하로

와

의 반응으로 질화막(202)을 침적시키고, 연속적으로

와

가스 반응으로 이루어지는 LPCVD에 의한 상부 옥사이드층(203)을 침적시킨다. 이 침적된 상하부 옥사이드(201, 203)층의 밀도를 높이고 층간 절연막 강도와 누설전류를 낮추기 위해 순수한

또는

가스를 사용하여, 다시 9501100℃ 온도범위에서 옥시나이트라이데이션시켜 ONO 층간절연막을 형성한다.Referring to FIG. 1B, after the peripheral circuit part is coated with a photosensitive agent by using a photo and etching process, a pattern of the first electrode layer 104 in the memory cell is formed. Next, after removing all the photosensitizer, the interlayer insulating film 105 is laminated as shown in FIG. 2 after the cleaning process. In this case, an RTP system capable of ramping up the temperature to about 25 ° C./sec or more is used. First, pure ammonia in the temperature range between 750 ℃ and 1000 ℃

) or

After nitration in a dilute mixed gas atmosphere such as Ar or the like to prevent growth of the native oxide layer of polysilicon, the reacted gas is discharged by lowering the temperature below 700 ° C and continuously discharged. 9501 100 ℃, pure water

After forming a predetermined amount of the lower oxide layer 201 in a gas atmosphere

or

The gas is used oxynitride. Then below 500 torr in the range of 750950 ° C.

Wow

The nitride film 202 is deposited by the reaction of

Wow

The upper oxide layer 203 is deposited by LPCVD, which is a gas reaction. In order to increase the density of the deposited upper and lower oxide layers 201 and 203 and lower the interlayer dielectric strength and leakage current,

or

The gas was used to further oxynitride at a temperature range of 9501 100 ° C. to form an ONO interlayer insulating film.

를 침적시키거나, 이온주입기술을 통해 불순물을 이온주입하여 도전층으로 만들고, 그 위에 도전율을 높이기 위해 금속과 실리콘의 화합물인 폴리사이드를 10001500Å정도 도포한다. 그리고 메모리 셀의 스택형 게이트가 형성되는 영역만을 한정하여 동일 마스크에 의해 여러 막질을 차례로 식각하는 자기정합(self align) 식각법을 이용하여 적층된 제2전극층(107)과 층간절연층막(105) 그리고 제1전극층(104)을 차례로 식각하고 감광제를 모두 제거한 다음 제2전극층(107)으로 이루어진 주변회로부의 일반적인 모오스 트랜지스터의 게이트 형성을 위해 사진, 식각 기술을 이용하여 메모리 셀 영역은 감광제로 모두 가리고 주변회로부 영역만 한정하여 트랜지스터의 게이트를 형성한다. 이와는 반대로 상기 공정과 동일하게 사진 식각 공정으로 주변회로부의 트랜지스터의 게이트를 먼저 형성한 후 또 하나의 사진, 식각공정으로 셀 스택형 게이트를 상기와 같은 자기정합 식각법으로 형성한다. 이후 메모리 셀 트랜지스터와 주변회로부 트랜지스터를 완성한다.Referring to FIG. 1C, the gate oxide film 107 of the peripheral circuit portion is grown to a predetermined thickness (about 120300 GPa), and polysilicon is stacked on the second electrode layer 107 of the memory cell by about 10001500 GPa, and then phosphorus is formed. Massive

Or by impregnating impurities through ion implantation technology to form a conductive layer, and to increase the conductivity thereon, 10001500 kPa of polyside, a compound of metal and silicon, is applied. The second electrode layer 107 and the interlayer dielectric layer film 105 which are stacked by using a self align etching method in which only the regions in which the stacked gates of the memory cells are formed are sequentially etched by the same mask. Then, the first electrode layer 104 is sequentially etched and all of the photosensitive agent is removed, and then the memory cell region is covered with the photosensitive agent by using photolithography and etching techniques to form a gate of a general MOS transistor of the peripheral circuit part formed of the second electrode layer 107. Only the peripheral circuit portion region is limited to form the gate of the transistor. On the contrary, the gate of the transistor of the peripheral circuit part is first formed by the photolithography process in the same manner as the above process, and then the cell stack gate is formed by the self-aligned etching method as described above. After that, the memory cell transistor and the peripheral circuit part transistor are completed.

분위기로 폴리실리콘을 소정량 산화 시킨후 상온 CVD 기술로

등의 실리콘 소오스와

를 반응시켜 질화막을 침적시키고 9001000℃에서 장시간 상기 질화막을 산화시켜 40-60Å 정도의 상부 옥사이드층을 형성시켜 제조된다. 이러한 구조에서, 디바이스 스케일링 다운시의 가장 큰 제약으로는 현재 사용중인 적층형(stacked) ONO층의 상부 산화막 형성시의 고온에 의한 버젯(high thermal budget)으로 인해 플로팅 게이트를 구성하는 폴리실리콘(polysilicon)에 도핑(doping)된 인의 침투에 의한 게이트 옥사이드의 열화 현상이다. 상기 상부 옥사이드층의 열적 버젯을 줄이기 위해서는 낮은 온도에서 형성되는 CVD 옥사이드층이나 상기 상부 옥사이드층의 대용으로 사용될 수 있는 고품질의 옥사이드층을 형성하기 위한 공정이 필요한 실정이다.The characteristics of the ONO structure are sensitive to the leakage ratio and reliability of the thickness ratio of the ONO layer, the physical properties of each layer, and the absolute thickness of the upper and lower oxide layers, so that the quality improvement of each layer is urgent in the application of the development of next generation high density and low power devices. . In addition, as described above, the conventional interlayer insulating film technology having the ONO structure is 800900 DEG C in pure water resistance.

After oxidizing a predetermined amount of polysilicon in the atmosphere,

With silicon sources such as

The reaction was carried out to deposit a nitride film and to oxidize the nitride film at 9001000 ° C. for a long time to form an upper oxide layer of about 40-60 Pa. In this structure, the biggest limitation in scaling down the device is the polysilicon constituting the floating gate due to the high thermal budget at the time of forming the top oxide of the stacked ONO layer in use. Degradation of the gate oxide due to the penetration of phosphorus doped (doped). In order to reduce the thermal budget of the upper oxide layer, a process for forming a CVD oxide layer formed at a low temperature or a high quality oxide layer that can be used as a substitute for the upper oxide layer is required.

However, the CVD oxide layer itself is difficult to control the thickness or form a high quality integrated oxide structure. In addition, another problem of the thermal ONO layer is that the thickness of the upper and lower oxide layers serving as the hole barrier during scaling down is not large. Therefore, the thickness reduction of the nitride film, which is an intermediate layer, is effective, and the use of a budget due to high temperature in the formation of the upper oxide layer increases the risk of oxidizing the entire nitride film as the thickness of the nitride film becomes thinner. In addition, if the uniformity of the nitride film characteristics is not maintained at a severe stepped portion in the memory cell, it is greatly limited when scaling down. The second is the quality of the lower oxide layer formed on polysilicon. The presence of the native oxide layer reduces the quality of the interface, and defects are caused by the presence of the native oxide layer which is the deciding factor in the effective thickness reduction. The thick bottom oxide layer has to be formed to compensate, which is a limitation of vertical scaling down and is an important cause of increase of leakage current.

In addition, conventional techniques that require the use of conventional furnaces and room temperature CVD tubes do not prevent the growth of such native oxide layers, and the complexity of the process increases the probability of contamination and has been one of the factors of quality deterioration.

An object of the present invention for solving the above problems is to provide a method for manufacturing an interlayer insulating film of a memory cell that can prevent the degradation of the quality of the contact by the native oxide layer.

Another object of the present invention is to provide a method for manufacturing an interlayer insulating film of a memory cell capable of forming a thin high quality interlayer insulating film.

It is still another object of the present invention to provide a method of manufacturing an interlayer insulating film of a memory cell having upper and lower oxide layers having improved quality using oxynitride.

1A to 1C are vertical cross-sectional views sequentially showing a manufacturing process for manufacturing a conventional nonvolatile memory cell,

2 is a vertical cross-sectional view showing an interlayer insulating film of a nonvolatile memory cell implemented according to the prior art,

3 is a vertical cross-sectional view showing an interlayer insulating film of a nonvolatile memory cell implemented according to the present invention;

4 is a waveform diagram showing a temperature range required for producing an interlayer insulating film according to the present invention.

의 프로그램과 소거 사이클을 수행한 후에 200℃에서 종래기술과 본 발명의 차아지 손실율을 비교한 파형도.5 is

Waveform diagram comparing the charge loss rate of the prior art and the present invention at 200 ° C. after performing the program and erase cycles.

6 is a waveform diagram comparing breakdown electric fields of an interlayer dielectric film according to two opposing bias polarities;

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, it should be noted that like elements and parts in the drawings represent the same numerals wherever possible.

분위기에서 나이트라이데이션(301, nitridation)을 실시한다. 다음으로 상기

가스를 700℃에서 배출한후 950∼1050℃(T2)에서 폴리 실리콘으로 이루어진 플로팅 게이트를 소정량 산화(302)시킨후

또는

분위기에서 옥시나이트라이데이션(303, Oxynitridation)에 의한 하부 옥사이드층(301, 302, 303)을 형성한다. 다음으로, 연속적인 공정(in-situ process)에 의해 750∼950℃(T3)의 조건에서

과

의 반응으로 질화막(304)을 도포한 후 반응가스를 700℃이하로 램프다운(Ramp down)시킬 때 배출된다. 다음으로 750℃∼950℃(T4)의 조건에서

와

의 반응에 의한 상부 옥사이드층(305)을 낮은 압력에서 형성하여 침적시키고, 다시 950℃∼1050℃(T5)의 조건과 두께조절이 용이한

또는

분위기에서 고밀도화와 나이트라이데이션시키는 RTP에 의한 연속된 다중공정에 의해 적층형의 ONO막(105)을 형성하기 위한 방법이다.In order to overcome the limitations mentioned in the prior art in the implementation of a nonvolatile memory device and to form a reliable interlayer insulating film on the floating gate, as shown in FIGS. 3 and 4, first, Rapid Thermal Processing (RTP) 800 to 900 ° C (T1), 100torr and a small amount to prevent native oxide growth in the system

Nitridation (301) is performed in an atmosphere. Next to the above

After the gas was discharged at 700 ° C, the floating gate made of polysilicon was oxidized 302 at 950-1050 ° C (T2).

or

In the atmosphere, lower oxide layers 301, 302, and 303 are formed by oxynitridation 303. Next, in a condition of 750-950 ° C. (T3) by a continuous in-situ process.

and

After the coating of the nitride film 304 by the reaction of the reaction gas is discharged when ramped down to 700 ° C or less. Next, under the conditions of 750 ° C to 950 ° C (T4)

Wow

The upper oxide layer 305 formed by the reaction at low pressure was deposited and deposited again, and the conditions of 950 ° C. to 1050 ° C. (T5) were easily adjusted.

or

It is a method for forming a laminated ONO film 105 by successive multiple processes by RTP which densify and nitrate in an atmosphere.

분위기에서 얇은 산화막(302)을 성장시킨후 옥시나이트라이데이션시켜 하부 옥사이드층(301,302,303)의 품질을 높이고, 연속된 공정으로

또는

등의 실리콘 소오스와

를 750950℃범위에서 화학반응시켜 도포된 질화막(304)을 형성한 후 열적 버젯(thermal budget)을 감소시키는 CVD 옥사이드층(305)을 침적(deposition)한 후 마지막으로 기공이 있는(porous)한 질화막(304) 구조의 결함(defect)을 감소시키고 상부 CVD 옥사이드층(305)의 밀도를 높이고 특성을 향상시키기 위해, 9501100℃ 온도범위에서 옥시나이트라이데이션을 하여 상기 질화막(304)상에 얇은 옥사이드층(305)을 형성하는 적층구조를 갖는 유전층을 형성한다.3 is a diagram illustrating a lamination structure of an ONO film 105 formed by RTP multiprocessing on a polysilicon layer 104. First, a small amount of nitride film 301 is formed to prevent native oxide growth and to form a polysilicon layer. Pure in conventional

After growing the thin oxide film 302 in the atmosphere to oxynitride to improve the quality of the lower oxide layer (301, 302, 303), in a continuous process

or

With silicon sources such as

Chemical reaction in the range of 750950 ° C. to form a coated nitride film 304, and then deposited a CVD oxide layer 305 which reduces the thermal budget, and finally a porous nitride film. A thin oxide layer on the nitride film 304 is subjected to oxynitride at a temperature range of 9501 to 100 ° C. to reduce defects in the structure, increase the density of the upper CVD oxide layer 305, and improve characteristics. A dielectric layer having a laminated structure forming 305 is formed.

FIG. 5 shows a lower oxide layer having 65 ° C. at 850 ° C. and a nitride film having 100 ° C. at 680 ° C. and CVD and wet oxidation at 950 ° C. using a conventional furnace and a CVD tube. The charge loss ratio was compared through a bake retention test performed at 200 ° C. after cycling (repetitive operation of program and erase) in a memory cell having an ONO film made of an oxide layer and an ONO film used in the present invention. Similarly, when the interlayer insulating film 105 was made to have a thickness of about 180 mm, the embodiment in which the interlayer insulating film 105 used in the present invention was applied reduced the charge loss by 35%.

FIG. 6 is a data comparing the breakdown electric field of the present invention and the prior art. In particular, the present invention provides improved properties over the conventional ONO film under the condition of applying a negative bias to P1 (-), that is, a floating gate. Got it. P2 (-) indicates when a negative bias is applied to the control gate.

As described above, the present invention is a method of manufacturing a continuous high quality interlayer insulating film using an RTP system, the advantage of forming a thin high quality interlayer insulating film that can be applied to the next generation flash memory in a system Has In addition, the present invention has the advantages of ease of scaling and removal of contaminating sources and removal of native oxide layers. In addition, the present invention has the advantage of improving the quality of the upper and lower oxide layer using the oxynitride.

Claims (3)

In the method of manufacturing an interlayer dielectric film used for a memory cell of a nonvolatile semiconductor memory device: In order to prevent the growth of the native oxide film, at 800 to 900 ° C

And nitridating to an atmosphere containing the diluent gas; remind

Pure water continuously after releasing gas

Forming a lower oxide film at a predetermined thickness at 950 to 1050 ° C. while introducing gas; Continuously pure

Infiltrating nitrogen into the lower oxide film in a gas atmosphere; After discharging the reacted gas at 750 ~ 950 ℃

Wow

Depositing a nitride film in response to; At 750-950 ° C. after continuously discharging the reacted gas

Wow

Depositing an upper oxide film by reaction of; Continuously in the temperature range of 950 ~ 1050 ℃

Infiltrating nitrogen into the upper oxide film in a gas atmosphere. The method of claim 1 wherein the diluent gas is Ar. A nonvolatile semiconductor comprising a gate oxide formed on a portion of a semiconductor substrate, a polysilicon layer formed on the gate oxide, an interlayer insulating film formed on the polysilicon layer, and a control gate electrode formed on the interlayer insulating film. In the memory device, the method of manufacturing the interlayer insulating film: In order to prevent the growth of the native oxide film, at 800 to 900 ° C

Nitridating to an atmosphere containing and Ar; remind

Pure water continuously after releasing gas

Forming a lower oxide film at a predetermined thickness at 950 to 1050 ° C. while introducing gas; Continuously infiltrating nitrogen into the lower oxide film in a pure NO gas atmosphere; After discharging the reacted gas at 750 ~ 950 ℃

Wow

Depositing a nitride film in response to; At 750-950 ° C. after continuously discharging the reacted gas

Wow

Depositing an upper oxide film by reaction of; Continuously permeating nitrogen to the upper oxide film in a NO gas atmosphere at a temperature in the range of 950 to 1050 ° C.

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