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KR100223825B1 - Method of forming an element isolation region in a semiconductor device - Google Patents

Method of forming an element isolation region in a semiconductor device Download PDF

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KR100223825B1
KR100223825B1 KR1019970015977A KR19970015977A KR100223825B1 KR 100223825 B1 KR100223825 B1 KR 100223825B1 KR 1019970015977 A KR1019970015977 A KR 1019970015977A KR 19970015977 A KR19970015977 A KR 19970015977A KR 100223825 B1 KR100223825 B1 KR 100223825B1
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forming
insulating film
trench
region
film
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KR19980078443A (en
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이승호
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

트랜치를 이용한 반도체 소자의 격리영역을 형성방법에 관한 것으로 이와 같은 반도체 소자의 격리영역 형성방법은 반도체 기판에 제 1 절연막과 제 2절연막을 패터닝하여 활성영역과 필드영역을 정의하는 단계, 상기 반도체 기판의 필드영역에 트랜치를 형성하는 단계, 상기 트랜치내에 채우도록 필드절연막을 형성하는 단계, 상기 제 1 절연막과 제 2 절연막을 제거하는 단계, 상기 전면에 동일두께의 제 3 절연막을 형성하는 단계, 상기 제 3 절연막을 등방성식각하여 제거하는 단계, 상기 활성영역상에 게이트절연막을 형성하는 단계, 상기 활성영역상의 소정부분에 게이트 전극을 형성하는 단계를 포함하여 제조되는 것을 특징으로 한다.A method of forming an isolation region of a semiconductor device using a trench is provided. The method of forming an isolation region of a semiconductor device may include: forming an active region and a field region by patterning a first insulating layer and a second insulating layer on a semiconductor substrate; Forming a trench in a field region of the substrate, forming a field insulating film to fill the trench, removing the first and second insulating films, and forming a third insulating film having the same thickness on the entire surface of the trench; Isotropically removing the third insulating film, forming a gate insulating film on the active region, and forming a gate electrode on a predetermined portion of the active region.

Description

반도체 소자의 격리영역 형성방법Method of forming an isolation region of a semiconductor device

본 발명은 반도체 소자의 격리영역 형성에 대한 것으로, 특히 트랜치를 이용한 반도체 소자의 격리영역을 형성방법에 관한 것이다.The present invention relates to the formation of an isolation region of a semiconductor device, and more particularly to a method of forming an isolation region of a semiconductor device using a trench.

첨부 도면을 참조하여 종래의 반도체 소자의 격리영역 형성방법에 대하여 설명하면 다음과 같다.Referring to the accompanying drawings, a method of forming an isolation region of a conventional semiconductor device is as follows.

종래 반도체 소자의 격리영역 형성방법은 도 1a에 도시한 바와 같이 반도체 기판(1)에 열산화공정으로 얇은 초기산화막(2)을 증착한다. 이후에 초기산화막(2)상에 질화막(3)을 증착한다. 이때 상기 질화막(3)대신에 폴리실리콘을 증착할 수도 있다. 이후에 질화막(3)상에 감광막(4)을 도포한 후 노광 및 현상공정으로 격리영역을 형성시킬 부분의 감광막(4) 선택적으로 패터닝한다.In the method of forming an isolation region of a conventional semiconductor device, a thin initial oxide film 2 is deposited on a semiconductor substrate 1 by a thermal oxidation process as shown in FIG. 1A. Thereafter, the nitride film 3 is deposited on the initial oxide film 2. In this case, polysilicon may be deposited instead of the nitride film 3. Thereafter, the photoresist film 4 is applied onto the nitride film 3 and then selectively patterned on the photoresist film 4 of the portion where the isolation region is to be formed by the exposure and development processes.

그리고 도 1b에 도시한 바와 같이 상기 패터닝된 감광막(4)을 마스크로 이용하여 질화막(3)과 초기산화막(2)을 플라즈마식각법으로 반도체 기판(1)이 노출될 때까지 식각한다. 이후에 감광막(4)를 제거한다.As shown in FIG. 1B, the patterned photoresist film 4 is used as a mask to etch the nitride film 3 and the initial oxide film 2 until the semiconductor substrate 1 is exposed by plasma etching. Thereafter, the photosensitive film 4 is removed.

다음에 도 1c에 도시한 바와 같이 남은 질화막(3)과 초기산화막(2)을 마스크로 이용하여 건식식각으로 반도체 기판(1)내에 트랜치(5)를 형성한다. 이때 트랜치는 75°∼85°의 각을 갖도록 경사지게 형성한다. 이후에 트랜치(5)가 형성된 반도체 기판(1)의 식각 데미지(damage)를 보상함과 동시에 트랜치(5) 상부 모서리를 라운딩(rounding)하기 위하여 트랜치(5) 측벽 및 그 하부에 3%∼5%의 DCE(DiChloroEthylene) 분위기에서 열산화막(26)을 형성한다.Next, as shown in FIG. 1C, the trench 5 is formed in the semiconductor substrate 1 by dry etching using the remaining nitride film 3 and the initial oxide film 2 as a mask. At this time, the trench is formed to be inclined to have an angle of 75 ° to 85 °. Thereafter, 3% to 5 on the sidewalls and lower portions of the trenches 5 to compensate for the etch damage of the semiconductor substrate 1 on which the trenches 5 are formed and to round the upper edges of the trenches 5. The thermal oxide film 26 is formed in a DCE (DiChloroEthylene) atmosphere of%.

그리고 도 1d에 도시한 바와 같이 상기 트랜치(5)를 매립하도록 전면에 질화막이나 산화막으로 절연막(7)을 형성한다.As shown in FIG. 1D, an insulating film 7 is formed of a nitride film or an oxide film on the entire surface of the trench 5 to fill the trench 5.

이후에 도 1e에 도시한 바와 같이 화학적 기계적 연막법(Chemical Mechanical Polishing:CMP)이나 에치백으로 상기 절연막(7)을 제거하여 반도체 기판(1)의 질화막(23)까지 평탄화 시켜서 필드절연막(7a)을 형성한다.Subsequently, as shown in FIG. 1E, the insulating film 7 is removed by chemical mechanical polishing (CMP) or etch back to planarize to the nitride film 23 of the semiconductor substrate 1 so that the field insulating film 7a is formed. To form.

다음에 도 1f에 도시한 바와 같이 핫(Hot) 인산으로 상기 질화막(3)을 제거한다. 이후에 전면에 웰 형성을 위한 이온주입을 한다.Next, as shown in FIG. 1F, the nitride film 3 is removed with hot phosphoric acid. Thereafter, ion implantation is performed on the front surface to form a well.

그리고 도 1g에 도시한 바와 같이 희석(Dilute) HF나 BOE(Buffered Oxide Etchant)를 이용하여 상기 초기산화막(2)을 제거한다. 이때 상기 절연막(7)의 에지영역에 리세스영역(8)이 형성된다.As shown in FIG. 1G, the initial oxide layer 2 is removed using dilute HF or BOE (Buffered Oxide Etchant). At this time, a recess region 8 is formed in the edge region of the insulating film 7.

도 1h에 도시한 바와 같이 전면에 제 1 게이트산화막(9)을 형성한후 화학기상 증착법으로 제 1 게이트 산화막(9)상에 제 2 게이트 산화막(10)을 동일한 두께를 갖도록 증착한다. 다음에 전면에 폴리실리콘을 증착한후 패터닝하여 제 2 게이트 산화막(10) 상에 게이트 전극(11)을 형성한다.As shown in FIG. 1H, the first gate oxide film 9 is formed on the entire surface, and then the second gate oxide film 10 is deposited on the first gate oxide film 9 by chemical vapor deposition to have the same thickness. Next, polysilicon is deposited on the entire surface, and then patterned to form the gate electrode 11 on the second gate oxide film 10.

상기와 같은 종래의 반도체 소자의 격리영역 형성방법은 다음과 같은 문제점이 있었다.The conventional method of forming an isolation region of a semiconductor device as described above has the following problems.

첫째, 트랜치를 이용한 종래의 반도체 소자의 격리영역 형성방법은 필드절연막의 에지영역의 리세스 영역이 매우 클경우에 두층의 게이트 산화막으로도 리세스 영역을 충분히 매립하기가 어려우므로 이 리세스 영역에서 기생 트랜지스터가 생겨서 전류가 누설될 수 있으므로 공정 마진이 매우 적어진다.First, in the conventional method of forming an isolation region of a semiconductor device using a trench, when the recess region of the edge region of the field insulation layer is very large, it is difficult to sufficiently fill the recess region even with two gate oxide layers. Parasitic transistors can be created to leak current, resulting in very low process margins.

둘째, 필드절연막의 에지영역의 리세스영역을 매우기 위하여 게이트 산화막을 두층으로 형성하므로 질좋은 게이트 산화막을 형성할 수가 없다.Second, since the gate oxide film is formed in two layers so as to form the recess region of the edge region of the field insulating film, a good gate oxide film cannot be formed.

본 발명은 상기와 같은 문제점을 해결하기 위하여 안출한 것으로 공정마진을 높이고 동작시 신뢰성이 높은 반도체 소자의 격리영역 형성방법을 제공하는 데 그 목적이 있다.An object of the present invention is to provide a method for forming an isolation region of a semiconductor device having high process margin and high reliability during operation.

도 1a내지 1h는 종래의 반도체 소자의 격리영역 형성방법을 도시한 공정단면도1A to 1H are cross-sectional views illustrating a method of forming an isolation region of a conventional semiconductor device.

도 2a 내지 2i는 본 발명 반도체 소자의 격리영역 형성방법을 도시한 공정단면도2A through 2I are cross-sectional views illustrating a method of forming an isolation region of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

21: 반도체 기판 22: 초기산화막21: semiconductor substrate 22: initial oxide film

23: 질화막 24: 감광막23: nitride film 24: photosensitive film

25: 트랜치 26: 열산화막25: trench 26: thermal oxide film

27: 절연막 27a: 필드절연막27: insulating film 27a: field insulating film

28: 리세스영역 29: 실리콘산화막28: recess region 29: silicon oxide film

30: 게이트산화막 31: 게이트 전극30: gate oxide film 31: gate electrode

상기와 같은 목적을 달성하기 위한 본 발명 반도체 소자의 격리영역 형성방법은 반도체 기판에 제 1 절연막과 제 2절연막을 패터닝하여 활성영역과 필드영역을 정의하는 단계, 상기 반도체 기판의 필드영역에 트랜치를 형성하는 단계, 상기 트랜치내에 채우도록 필드절연막을 형성하는 단계, 상기 제 1 절연막과 제 2 절연막을 제거하는 단계, 상기 전면에 동일두께의 제 3 절연막을 형성하는 단계, 상기 제 3 절연막을 등방성식각하여 제거하는 단계, 상기 활성영역상에 게이트절연막을 형성하는 단계, 상기 활성영역상의 소정부분에 게이트 전극을 형성하는 단계를 포함하여 제조되는 것을 특징으로 한다.In order to achieve the above object, the method of forming an isolation region of a semiconductor device according to the present invention may include: forming an active region and a field region by patterning a first insulating layer and a second insulating layer on a semiconductor substrate, and forming a trench in a field region of the semiconductor substrate. Forming a field insulating film to fill the trench, removing the first insulating film and the second insulating film, forming a third insulating film having the same thickness on the entire surface, and isotropically etching the third insulating film. And forming a gate insulating film on the active region, and forming a gate electrode on a predetermined portion of the active region.

도면을 참조하여 본 발명 반도체 소자의 격리영역 형성방법에 대하여 설명하면 다음과 같다.A method of forming an isolation region of a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

본 발명 반도체 소자의 격리영역 형성방법은 도 2a에 도시한 바와 같이 반도체 기판(21)에 열산화공정으로 100Å∼200Å 정도의 초기산화막(22)을 증착한다. 이후에 초기산화막(22)상에 1000Å∼2500Å 정도의 두께를 갖도록 질화막(23)을 증착한다. 이때 상기 질화막(23)대신에 폴리실리콘을 증착할 수도 있다. 이후에 질화막(23)상에 감광막(24)을 도포한 후 노광 및 현상공정으로 격리영역을 형성시킬 부분의 감광막(24) 선택적으로 패터닝한다.In the method for forming an isolation region of the semiconductor device of the present invention, as shown in FIG. 2A, an initial oxide film 22 having a thickness of about 100 to 200 Å is deposited on the semiconductor substrate 21 by a thermal oxidation process. Thereafter, the nitride film 23 is deposited on the initial oxide film 22 so as to have a thickness of about 1000 mW to 2500 mW. In this case, polysilicon may be deposited instead of the nitride layer 23. Thereafter, the photoresist film 24 is coated on the nitride film 23, and then the photoresist film 24 is selectively patterned in a portion to form an isolation region by an exposure and development process.

그리고 도 2b에 도시한 바와 같이 상기 패터닝된 감광막(24)을 마스크로 이용하여 질화막(23)과 초기산화막(22)을 플라즈마식각법으로 반도체 기판(21)이 노출될 때까지 식각한다. 이후에 감광막(24)를 제거한다.As shown in FIG. 2B, the patterned photoresist layer 24 is used as a mask to etch the nitride layer 23 and the initial oxide layer 22 until the semiconductor substrate 21 is exposed by plasma etching. Thereafter, the photosensitive film 24 is removed.

다음에 도 2c에 도시한 바와 같이 남은 질화막(23)과 초기산화막(22)을 마스크로 이용하여 건식식각으로 반도체 기판(21)내에 트랜치(25)를 형성한다. 이때 트랜치는 75°∼85°의 각을 갖도록 경사지게 형성한다. 이후에 트랜치(25)가 형성된 반도체 기판(21)의 식각 데미지(damage)를 보상함과 동시에 트랜치(25) 상부 모서리를 라운딩(rounding)하기 위하여 트랜치(25) 측벽 및 그 하부에 50Å∼400Å 정도의 두께를 갖도록 3%∼5%의 DCE(DiChloroEthylene) 분위기에서 열산화막(26)을 형성한다.Next, as shown in FIG. 2C, the trench 25 is formed in the semiconductor substrate 21 by dry etching using the remaining nitride film 23 and the initial oxide film 22 as a mask. At this time, the trench is formed to be inclined to have an angle of 75 ° to 85 °. Thereafter, in order to compensate for etch damage of the semiconductor substrate 21 on which the trench 25 is formed, and to round the upper corner of the trench 25, the trench 25 sidewalls and the lower portion of the semiconductor substrate 21 may have a width of about 50 μs to 400 μs. The thermal oxide film 26 is formed in a 3% to 5% DCE (DiChloroEthylene) atmosphere to have a thickness of.

그리고 도 2d에 도시한 바와 같이 상기 트랜치(25)를 매립하도록 전면에 질화막이나 산화막으로 절연막(27)을 형성한다.As shown in FIG. 2D, an insulating film 27 is formed of a nitride film or an oxide film on the entire surface of the trench 25 to fill the trench 25.

이후에 도 2e에 도시한 바와 같이 화학적 기계적 연막법(Chemical Mechanical Polishing:CMP)이나 에치백으로 상기 절연막(27)을 제거하여 반도체 기판(21)의 질화막(23)까지 평탄화 시켜서 필드절연막(27a)을 형성한다.Subsequently, as shown in FIG. 2E, the insulating film 27 is removed by chemical mechanical polishing (CMP) or etch back to planarize the nitride film 23 of the semiconductor substrate 21 to form the field insulating film 27a. To form.

다음에 도 2f에 도시한 바와 같이 핫(Hot) 인산으로 상기 질화막(23)을 제거한다. 이후에 전면에 웰 형성을 위한 이온주입을 한다.Next, as shown in FIG. 2F, the nitride film 23 is removed by hot phosphoric acid. Thereafter, ion implantation is performed on the front surface to form a well.

그리고 도 2g에 도시한 바와 같이 희석(Dilute) HF나 BOE(Buffered Oxide Etchant)를 이용하여 상기 초기산화막(22)을 제거한다. 이때 상기 절연막(27)의 에지영역에 리세스영역(28)이 형성된다.As shown in FIG. 2G, the initial oxide layer 22 is removed using dilute HF or BOE (Buffered Oxide Etchant). In this case, a recess region 28 is formed in the edge region of the insulating layer 27.

도 2h에 도시한 바와 같이 전면에 상기 리세스영역(28)을 매립하도록 100Å∼300Å 정도의 두께를 갖도록 실리콘산화막(SiO2)(29)을 증착한다. 이후에 전면에 채널스톱 이온주입을 한다.As shown in FIG. 2H, a silicon oxide film (SiO 2 ) 29 is deposited to have a thickness of about 100 GPa to 300 GPa so as to fill the recess region 28 on the entire surface thereof. After this, channel stop ion implantation is performed on the front surface.

도 2i에 도시한 바와 같이 희석(Dilute) HF나 BOE(Buffered Oxide Etchant)나 에치백으로 상기 실리콘산화막(29)을 제거한다. 이때 활성영역상의 실리콘산화막(29)을 모두 제거한다. 이후에 전면에 산화막을 형성하는데 활성영역상에는 게이트산화막(30)이 형성된다.As shown in FIG. 2I, the silicon oxide film 29 is removed by dilute HF, BOE (Buffered Oxide Etchant), or etch back. At this time, all of the silicon oxide film 29 on the active region is removed. Thereafter, an oxide film is formed on the entire surface, and a gate oxide film 30 is formed on the active region.

다음에 전면에 폴리실리콘 이나 도전성 물질을 증착한 후 패턴하여 게이트 전극(31)을 형성한다.Next, polysilicon or a conductive material is deposited on the entire surface, and then patterned to form the gate electrode 31.

상기와 같은 본 발명 반도체 소자의 격리영역 형성방법은 다음과 같은 효과가 있다.The isolation region forming method of the semiconductor device of the present invention as described above has the following effects.

트랜치에 형성된 필드절연막의 상부 에지부분의 리세스 영역에서 기생트랜지스터가 생성되는 것을 막을 수 있으므로 이부분으로 전류가 누설되는 것을 방지할 수 있으므로 공정 마진 및 소자의 신뢰성을 높일 수 있다.Since parasitic transistors can be prevented from being generated in the recessed region of the upper edge portion of the field insulating film formed in the trench, current leakage can be prevented in this portion, thereby increasing process margin and reliability of the device.

Claims (1)

반도체 기판에 제 1 절연막과 제 2절연막을 패터닝하여 활성영역과 필드영역을 정의하는 단계, 상기 반도체 기판의 필드영역에 트랜치를 형성하는 단계, 상기 트랜치내에 채우도록 필드절연막을 형성하는 단계, 상기 제 1 절연막과 제 2 절연막을 제거하는 단계,Patterning a first insulating film and a second insulating film on the semiconductor substrate to define an active region and a field region, forming a trench in the field region of the semiconductor substrate, forming a field insulating film to fill the trench; Removing the first insulating film and the second insulating film, 상기 전면에 동일두께의 제 3 절연막을 형성하는 단계, 상기 제 3 절연막을 등방성식각하여 제거하는 단계, 상기 활성영역상에 게이트절연막을 형성하는 단계, 상기 활성영역상의 소정부분에 게이트 전극을 형성하는 단계를 포함하여 제조되는 것을 특징으로 하는 반도체 소자의 격리영역 형성방법.Forming a third insulating film having the same thickness on the front surface, removing the third insulating film by isotropic etching, forming a gate insulating film on the active region, and forming a gate electrode on a predetermined portion of the active region. Method for forming an isolation region of a semiconductor device comprising the step of manufacturing.
KR1019970015977A 1997-04-28 1997-04-28 Method of forming an element isolation region in a semiconductor device Expired - Fee Related KR100223825B1 (en)

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